US20070150136A1

US20070150136A1 - Periodic rate sensor self test

Info

Publication number: US20070150136A1
Application number: US11/345,350
Authority: US
Inventors: Kenneth Doll; Arnold Spieker
Original assignee: Individual
Current assignee: Individual
Priority date: 2005-11-30
Filing date: 2006-02-01
Publication date: 2007-06-28
Also published as: KR20080071621A; WO2007064782A1; JP2009519438A; US8050816B2; US20090277244A1; DE112006003237T5; JP4987010B2

Abstract

A periodic test signal is injected into a motion sensor and the sensor output is compared to a threshold to determine whether the sensor is functioning properly.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

Not Applicable

BACKGROUND OF THE INVENTION

This invention relates in general to motion sensors and in particular to a method for periodically testing the operation of such sensors.
Vehicle electronically controlled brake systems are becoming increasing sophisticated to include the capability to correct vehicle directional movement upon detection of an undesired vehicle motion, such as, for example, loss of directional control on a low mu surface or potential vehicle roll over. Such detection typically involves motion sensors, to include accelerometers and/or angular rate sensors and also usually includes input from other vehicle operating parameter sensors, such as, for example, wheel speed sensors and a steering angle sensor. Vehicle brake control systems typically include an Electronic Control Unit (ECU) that receives the various sensor output signals. A microprocessor within the ECU that is controlled by a stored algorithm monitors the received sensor signals. The microprocessor is operative, upon detection of a potential vehicle directional stability problem, to selectively apply the vehicle brakes and/or vary engine torque to correct the problem.
The motion sensors utilized by the brake control system are also becoming increasingly miniaturized and sophisticated to include signal conditioning circuits. Multiple motion sensors with associated signal conditioning circuits for the sensor outputs may be included on a single sensor chip. The signal conditioning circuits also may include a self testing capacity for monitoring the sensor output signal to detect a malfunctioning sensor. Typically, the self test is carried out during initial vehicle start-up and will generate an error code if the signal conditioning circuit determines that the senor output signal exceeds a predetermined threshold Additionally, upon detecting a malfunctioning sensor, the self test capability may disable the sensor output so an erroneous signal is not sent to the ECU.
However, because vehicles are operated for increasingly lengthy periods of time, the operational time of motion sensors between self tests also has increased. As a result, if motion sensors begin to malfunction the problem may not be detected in a timely fashion. Accordingly, it would be desirable to provide a periodic self test method for the motion sensors that would occur while the vehicle is in operation.

BRIEF SUMMARY OF THE INVENTION

This invention relates to a method for periodically testing the operation of motion sensors.
The present invention contemplates a method for verifying proper operation of a motion sensor that includes injecting a test signal into the motion sensor and then, after a predetermined delay, measuring the output of the sensor. The measured sensor output is then compared to an acceptable range of output values and, upon determining that the output is either above or below the acceptable range of output values, a fault is declared and an error signal generated. Additionally, the present invention contemplates that the test signal is a periodic signal and that the error signal is generated only after a predetermined number of consecutive faults have been detected. Furthermore, the invention also contemplates that the output of the sensor is blocked for a period of time following the injection of each test single. In the preferred embodiment, the test signal comprises a series of pulses of one millisecond duration. The pulses may all be positive, all negative, alternately positive and negative or selected or random combinations of positive and negative pulses.
Various objects and advantages of this invention will become apparent to those skilled in the art from the following detailed description of the preferred embodiment, when read in light of the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a portion of a control circuit for an electronic vehicular brake control system that includes motion sensors and that is in accordance with the invention.
FIG. 2 is a graph of typical voltage waveforms produced by the accelerometer shown in FIG. 1.
FIG. 3 is a graph of a periodic test voltage that is injected into the accelerometer shown in FIG. 1.
FIG. 4 is a graph of the accelerometer voltage waveform produced by the accelerometer shown in FIG. 1 after the test voltage shown in FIG. 3 has been injected.
FIG. 5 is an enlarged graph that illustrates the response of the acceleration sensor to the test voltage shown in FIG. 3.
FIG. 5A is a graph of waveform shown in FIG. 4 after digital filtering.
FIG. 6 is a flow chart of a method of testing the accelerometer shown in the circuit shown in FIG. 1 that is in accordance with the invention.
FIG. 7 is a flow chart for a subroutine included in the method illustrated in FIG. 6.
FIG. 8 is a graph of typical voltage waveforms produced by the yaw sensor shown in FIG. 1.
FIG. 9 is graph of a periodic test voltage that is injected into the yaw sensor shown in FIG. 1.
FIG. 10 is a graph of the yaw sensor voltage waveform produced by the yaw sensor shown in FIG. 1 after the test voltage shown in FIG. 9 has been injected.
FIG. 11 is an enlarged graph that illustrates the response of the yaw sensor to the test voltage shown in FIG. 9.
FIG. 11A is a graph of waveform shown in FIG. 10 after digital filtering.
FIG. 12 is a flow chart of a method of testing the yaw sensor shown in the circuit shown in FIG. 1 that is in accordance with the invention.
FIG. 13 is a flow chart for an alternate embodiment of the method of testing illustrated in FIG. 6.
FIG. 14 is a flow chart for another alternate embodiment of the method of testing illustrated in FIG. 6.
FIG. 15 is a flow chart for another alternate embodiment of the method of testing illustrated in FIG. 6.
FIG. 16 is a flow chart for another alternate embodiment of the method of testing illustrated in FIG. 6.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to the drawings, there is illustrated in FIG. 1 a portion of a control circuit 10 for an electronic vehicular brake control system (not shown) in accordance with the invention. The control circuit 10 includes a microprocessor 12 having an acceleration sensor test signal output port 13 that is connected to a test signal input port of an acceleration sensor 14. The acceleration sensor 14 has output port connected through a first analog hardware anti-aliasing filter 15 to the input of a first analog to digital converter 16. As shown in FIG. 1, the first analog to digital converter 16 is included in the microprocessor 12. The output of the first analog to digital converter 16 is connected to both an acceleration sensor test signal input port 17 of a signal processing and diagnostic portion 12A of the microprocessor 12 and the input of a first digital filter 18. As shown in FIG. 1, the first digital filter 18 is included in the microprocessor 12. The first digital filter 18 has an output connected to an accelerometer input port 19 of the microprocessor portion 12A. Similarly, as also shown in FIG. 1, the microprocessor 12 also has a pair of angular rate sensor test signal output ports 20 and 22 connected to an angular rate sensor 24. The angular rate sensor 24 has an output port connected through a second analog hardware anti-aliasing filter 26 to the input of a second analog to digital converter 28. As shown in FIG. 1, the second analog to digital converter 28 is included in the microprocessor 12. The output of the second analog to digital converter 28 is connected to both an angular rate sensor teat signal input port 29 of the microprocessor portion 12A and the input of a second digital filter 30. As shown in FIG. 1, the second digital filter 30 is included in the microprocessor 12. The second digital filter 30 has an output connected to an angular rate sensor input port 31 of the microprocessor portion 12A.
The analog anti-aliasing filters 15 and 26 are operative to remove frequency components from the sensor signals that are beyond the range of the corresponding analog to digital converters 16 and 28, respectively. The acceleration sensor test signal output port 13 of the microprocessor 12 is operative, as will be described below, to apply a periodic test signal to the acceleration sensor 14. Similarly, the pair of angular rate sensor test signal output ports 20 and 22 of the microprocessor 12 are operative, as also will be described below, to apply periodic test signals to the angular rate sensor 24. The microprocessor 12 also has an output port 32 connected to a brake system Electronic Control Unit (ECU) 34. The microprocessor 12 is operative to supply acceleration and angular rate signals to the ECU 34. The microprocessor 12 also has additional output ports that are connected to additional vehicle dynamic controllers, such as, for example a Vehicle Stability Control (VSC) system. The group of additionally vehicle dynamic controllers is labeled with the numerical identifier 36. While individual connecting wires are shown between the controller 12 and the control systems in FIG. 1, the invention also may be practiced with a CAN bus connecting output of the controller 12 to the systems (not shown).
While one acceleration sensor 14 and one yaw rate sensor 24 are shown in FIG. 1, it will be appreciated that the invention also may be practiced with more sensors than are shown in the figure. Additionally, the invention also may be practiced with only one of the sensors shown. Furthermore, while the sensor test signals are shown as being generated within the microprocessor 12 and being applied directly to the sensor test signal ports, it will be appreciated that the a test signal generator (not shown) may be provided external to the microprocessor 12 with the controller programmed to provide the test signal generator with trigger signals. The test signal generator would then generate the test signals that would be applied to the accelerometer and angular rate sensor test signal ports.
The operation of the invention relative to the acceleration sensor 14 will now be described in light of the graphs of voltage vs. time shown in FIGS. 2 through 5. In FIG. 2, the dashed smooth curve labeled 40 represents the analog output signal generated within the acceleration sensor 148 and amplified by a signal conditioning circuit within the accelerometer sensor. The conditioned sensor signal 40 is passed through the first analog anti-aliasing filter 15 and the filtered signal is applied to the input of the first analog to digital converter 16. The analog to digital converter 16 periodically samples the filtered analog signal at a rate N₁to generate the solid stepped voltage curve labeled 42 in FIG. 2. In the preferred embodiment, the conditioned sensor signal 40 is sampled every millisecond, which is then equal to N₁; however, faster or slower sampling rates also may be utilized. The first digital filter 18 operates on the digitized sensor signal 42 and generates a filter output signal 43 at a rate of N₂, which, in the preferred embodiment, is selected as an integer multiple of N₁. However, it will be appreciated that the invention also may be practiced with the rate N₂being a non-integer multiple of the rate N₁.
The present invention contemplates periodically injecting a test signal consisting of a voltage pulse into the acceleration sensor test port at a testing rate N₃, which, in the preferred embodiment, is selected as an integer multiple of the digital filter rate N₂. However, it will be appreciated that the invention also may be practiced with the rate N₃being a non-integer multiple of the rate N₂. In the preferred embodiment, each test pulse has a relatively short duration, such as, for example one millisecond; however, the invention also may be practiced using a test pulse having other durations. The test signal is illustrated in FIG. 3 where the voltage pulses are labeled 44. The resulting analog to digital converter output signal 46, as modified by the test pulse, but before filtering by the first digital filter 18, is shown in FIG. 4. This signal, having a sampling rate of N₁, is applied directly to the acceleration test signal input port 17 of the microprocessor portion 12A.
A typical voltage response 48 of the circuit to the test pulse 44 is illustrated in FIG. 5, where ST is the magnitude of the test pulse 44. The invention contemplates measuring the magnitude of the sensor output signal after a predetermined time period passes following the application of the test pulse 44. In the preferred embodiment, a one millisecond delay is utilized; however, the invention also may be practiced with other time delays. The resulting response voltage is labeled ΔST and is less than ST. For clarity, only the test pulse 44 and the response voltage ΔST are shown in FIG. 5. While the preferred embodiment measures the response voltage one millisecond after the test pulse is applied, it will be appreciated that the measurement may be taken after any selected time period has passed. As will be explained in more detail below, the response voltage ΔST is compared by the microprocessor 12 to minimum and maximum thresholds values that are stored in a Non-Volatile Random Access Memory (NVRAM) and the sensor is deemed to operating satisfactorily only if the response voltage ΔST falls within the range defined by the thresholds. For clarity in FIG. 5, ΔST has been shown as an excursion from the zero voltage axis; however, the invention contemplates that ΔST would actually be measured relative to the digitized sensor signal 46 shown in FIG. 4. Accordingly, the voltage response threshold values also would be adjusted relative to the sensor signal.
As described above, the digitized signal 46, including the periodic test pulses 44 is fed to the first digital filter 18. By selecting the digital filter sampling rate N₂to be large enough relative to the analog to digital converter rate N₁, the transient effect of the test pulse 44 is ended by time that the digital filter 18 samples the signal 46. Thus, the digital filter 18 effectively “steps over” the signals generated by the testing of the acceleration sensor and produces the output signal 47 shown in FIG. 5A that is supplied to the acceleration sensor input port 19 of the controller 12 and then subsequently to the individual vehicle systems. In the preferred embodiment, the digital filter sampling rate N₂is selected to be sufficiently large that the digital filter output signal 47 is very similar to, or exactly the same as, the signal 43 shown in FIG. 2 that does not include test pulses 44. Additionally, the sampling rates N₁, N₂and N₃are selected with consideration of the response times of the controlled vehicle systems. Thus, the selected sampling rates are sufficiently faster than the system response times such that the loss of the sampled acceleration sensor signals following insertion of the sensor test pulses does not adversely affect the system responses.
While the preferred embodiment has been illustrated in FIG. 3 with a test signal consisting a plurality of positive test pulses, it will be appreciated that the invention also may be practiced with a test signal consisting of a plurality of negative test pulses (not shown). As illustrated in FIGS. 4 and 5A, the invention effectively discards a number of analog to digital converter output data samples during the sensor test. In the preferred embodiment, four data points following the initial application of the test pulse are discarded; however, the application also may be practiced with the discarding of more or less than four data points. Thus, in the preferred embodiment, the test voltage pulse ST is applied at every N₃milliseconds in FIG. 4 and the data points that are taken at (N₃+N₁), (N₃+2N₁), (N₃+3N₁,) and (N₃+4N₁) milliseconds are discarded. In place of the discarded data points, the last filter output signal, which would be at (N₃−N₁) milliseconds in FIG. 5, is used as input to the microprocessor portion 12A.
As will also be described in greater detail below, after detecting a response signal ΔST that is outside the acceptable range of values, the microprocessor 12 declares a fault and begins counting the consecutive number of resultant voltage faults. Only upon counting a predetermined number of consecutive faults, or fault threshold, will the microprocessor set an error flag. Thus, a potential false error signal is avoided being triggered by one or a few consecutive faults. If, during the counting of the response voltage errors, the response signal ΔST returns to being within the acceptable range, the error count is reset to zero.
Once set, the error flag remains set for a relatively long period without further detection of response voltage errors before being reset. In the preferred embodiment, the time required without detection of an error for resetting the error flag, or flag reset delay, is 100N₁, although other greater or shorter time periods also could be utilized. Additionally, the error flag reset delay will begin again whenever the response signal fault count exceeds the fault count threshold. Upon setting the error flag, the control circuit would then take corrective action which may include providing a warning message to the vehicle operator and disabling the control system.
The method is implemented by an algorithm that is stored in a memory unit accessible by the microprocessor 12. The algorithm is illustrated by the flow chart shown in FIG. 6 and is entered through block 50. The first three functional blocks initialize the program. Thus, in functional block 52, the error flag is reset while the an error flag count EC and a fault count FC are set to zero in functional blocks 54 and 56, respectively. The algorithm continues to block 58 which is an error flag count/clear subroutine that is shown in FIG. 7 and will described below. After the error flag has been set, the error flag count/clear subroutine is operative to track the time that the flag has been set without a reoccurrence of a response voltage error; and, upon reaching the predetermined time period without an additional error, to reset the error flag.
The algorithm then proceeds to functional block 60 where the operation is delayed for a time period DELAY1 corresponding to the test voltage rate N₃. As described above, during this period, sensor output signals are being supplied to the controller 12 by the first digital filter 18 at a rate of N₂. Upon reaching the end of the first time delay, the algorithm advances to functional block 62 where a test voltage pulse ST is inserted into the acceleration sensor test signal input port. Then, after a time delay that, in the preferred embodiment, corresponds to the digital converter sampling rate of N₁, the response voltage, ΔST is measured in functional block 66 and the result applied to the test signal input port 17 of the microprocessor portion 12A. As described above, the first digital filter 18 continues to supply acceleration sensor signals to the input port 19 of the microprocessor portion 12A at a rate of N₂.
Following sampling of the acceleration sensor response to the test signal in functional block 66, the algorithm reaches decision block 72 where the response voltage ΔST is compared to allowed maximum and minimum values in accordance with the following relationship:
Is T _MAx ≧ΔST≧T _MIN?, where,
T_MAXis the upper limit for the allowable output voltage range and
T_MINis the lower limit for the allowable output voltage range.
In decision block 72, if the response voltage ΔST is within the allowable voltage range, the algorithm transfers to functional block 73 where the fault count FC is again zeroed. The algorithm then returns to functional block 58 and continues as described above. If, in decision block 72, the response voltage ΔST is outside of the allowable voltage range, a fault is declared and the algorithm transfers to decision block 74 where the algorithm counts the number of consecutive iterations FC that the response voltage ΔST is outside of the allowable voltage range. It is to be noted that, if, subsequent to beginning to increase the fault count FC, the response voltage ΔST returns to be within the allowable voltage range, decision block 72 will cause the fault count FC to be reset to zero, beginning the counting over. The algorithm then continues to decision block 76.
In decision block 76, the total number of consecutive fault iterations FC that the response voltage ΔST is out of the allowed voltage range is compared to the maximum allowable number of fault iterations, or threshold, FC_MAX. If the maximum number of consecutive fault iterations FC_MAXhas not been reached, the algorithm transfers to functional block 58 where the error flag count/clear subroutine is entered and the algorithm continues as described above. If, in decision block 76, the maximum number of consecutive iterations has been reached, the algorithm transfers to functional block 78 where the error flag is set. The algorithm then continues to functional block 80 where the reset error flag count, EC, is set to zero. Thus, the error flag reset counter is reset every time that the maximum number of consecutive fault iterations FC_MAXis exceeded. The algorithm then continues to decision block 82 where it is determined whether or not the algorithm should continue. A specific test regarding the vehicle is applied at this point, such as for example, checking to determine if the vehicle ignition is still on. If the continuation is needed, the algorithm transfers back to functional block 58 and the algorithm continues as described above. If the continuation is not needed, the algorithm transfers to exit block 84 and terminates.
Returning now to the error flag count/clear subroutine shown in the block 58, a flow chart for the subroutine is shown in FIG. 7. The subroutine is entered though block 90 and proceeds to decision block 92, where it is determined whether or not the error flag has been previously set. If the error flag has not been set, as would. occur upon the first time through the algorithm shown in FIG. 6, the subroutine immediately exits through block 94 to functional block 60 for the time delay as shown in FIG. 6. If it is determined in decision block 92 that the error flag has been set, the subroutine transfers to functional block 96 where the error count EC is indexed by one. The subroutine then continues to decision block 96.
In decision block 96, the subroutine determines whether or not the maximum error count EC_MAXhas been reached. If the maximum error count has not been reached, the subroutine exits through block 94 to functional block 60 as shown in FIG. 6. However, if the maximum error count has been reached, the subroutine transfers to decision block 98 where the error flag is reset and then continues to decision block 100 where the error flag count EC is set to zero. The subroutine then exits through block 94 to functional block 60 as shown in FIG. 6. Thus, the subroutine is operative to reset the error flag upon the time period without the response voltage ΔST being outside of its allowable range reaching the predetermined value EC_MAX. As described above, the time period for resetting the error flag is 100N₁, seconds in the preferred embodiment.
Regarding angular rate, sensors, the present invention contemplates that the above described self-test also may be applied to an angular rate sensor with periodic test pulses being injected into the sensor and the sensor response measured and compared to an allowable range of values. As with the acceleration sensor test described above, the sampling rates of the components shown in FIG. 1 are selected such that the second digital filter 30 “steps over” the output of the second analog to digital converter 28 during the test. Either positive or negative test pluses may be applied to the angular rate sensor 24.
The present invention also contemplates an alternate embodiment of the self-test for angular rate sensors. In the alternate embodiment, alternating positive and negative test pulses are applied to the angular rate sensor. The resulting sensor output is compared to an allowable range of values with a first range corresponding to positive test pulses and a second range corresponding to negative test pulses. Each time that the response voltage is outside of its allowable range constitutes a sensor fault. The number of consecutive sensor faults that result from positive test pulses is counted. Similarly, the number of consecutive sensor faults that result form negative test pulses is counted. Each of the fault counts is then compared to a corresponding fault count threshold. Additionally, the sum of the fault counters is compared to a sum count threshold. Upon either one of the fault count thresholds or the sum count threshold being exceeded, an error flag is set. Furthermore, as will be described below, the invention also contemplates that the yaw sensor response signal thresholds are temperature compensated.
The operation of the alternate embodiment of the invention relative to the an angular rate sensor 24 shown in FIG. 1 will now be described in light of the graphs of voltage vs. time shown in FIGS. 8 through 11. In FIG. 8, the dashed smooth curve labeled 100 represents the analog output signal generated by the angular rate sensor 24 and amplified by a signal conditioning circuit within the angular rate sensor. The conditioned sensor signal 100 is passed through the second analog anti-aliasing filter 26 and the filtered signal is applied to the input of the second analog to digital converter 28. The analog to digital converter 17 periodically samples the filtered analog signal at a rate N₁to generate the solid stepped voltage curve labeled 101 in FIG. 9. In the preferred embodiment, the conditioned sensor signal 100 is sampled every millisecond, which is then equal to N₁; however, faster or slower sampling rates also may be utilized. The second digital filter 30 operates on the digitized angular rate sensor signal 101 and generates a filter output signal at a rate of N₂, which, in the preferred embodiment, is selected as an integer multiple of N₁. However, it will be appreciated that the invention also may be practiced with the rate N₂being a non-integer multiple of the rate N₁. The digital filter output signal shown by the solid stepped voltage curve labeled 102 in FIG. 8.
The alternate embodiment of the invention contemplates periodically injecting a test signal consisting of alternating positive and negative voltage pulses into the angular rate sensor test port at a testing rate N₃which, in the preferred embodiment, is selected as an integer multiple of N₂. However, it will be appreciated that the invention also may be practiced with the rate N₃being a non-integer multiple of the rate N₂. While two input test ports are shown for the angular rate sensor 24 in FIG. 12, it will be appreciated that both test signals may injected into a single test port. Thus, for the preferred embodiment, a test pulse is injected at N₃time intervals with positive test pulses being injected at 2N₃time intervals. Similarly, negative test pulses are injected at 2N₃time intervals. Also, in the preferred embodiment, each of the test pulses has a relatively short duration, such as, for example, one millisecond; however, the invention also may be practiced using test pulses having other durations. The test signal is illustrated in FIG. 9 where the positive and negative voltage pulses are labeled 104 and 106, respectively. The resulting analog to digital converter output signal 108, as modified by the test pulse, but before filtering by the second digital filter 30, is shown in FIG. 10. This signal, having a sampling rate of N₁, is applied directly to the angular rate sensor test signal input port 29 of the controller 12.
A typical voltage response 108 of the circuit to a positive test pulse 104 is illustrated in FIG. 11, where ST1 is the magnitude of the positive test pulse. Similarly, a typical voltage response 110 of the circuit to a negative test pulse 106 also is illustrated in FIG. 11, where ST2 is the magnitude of the negative test pulse. As described above for the acceleration sensor self-test, the invention contemplates measuring the magnitude of the sensor output signal after a predetermined time period passes following the application of the test pulse 44. The resulting response voltages are labeled ΔSTI and ΔST2 and are less than ST1 and ST2, respectively. For clarity in FIG. 11, only the test voltage pulses ST1 and ST2 and their response voltages ΔST1 and ΔST2 are shown. While the preferred embodiment measures each response voltage one millisecond after the associated test pulse has been applied, it will be appreciated that the measurement may be taken after any selected time period has passed. For clarity in FIG. 11, ΔST1 and ΔST2 have been shown as excursions from the zero voltage axis; however, the invention contemplates that ΔST1 and ΔST2 would actually be measured relative to the digitized sensor signal 108 shown in FIG. 10. Accordingly, the voltage response threshold values also would be adjusted relative to the sensor signal.
As described above, the digitized signal 108, including the periodic test pulses 104 and 106 is fed to the second digital filter 30. By selecting the second digital filter sampling rate N₂to be large enough relative to the analog to digital converter rate N₁. the transient effects of the test pulses 104 and 106 are ended by time that the second digital filter 30 samples the signal 108. Thus, the second digital filter 30 also effectively “steps over” the signals generated by the testing of the angular rate sensor and produces the output signal 109 shown in FIG. 11 A that is supplied to the angular rate sensor input port 31 of the microprocessor portion 12A and then subsequently to the individual vehicle systems. In the preferred embodiment, the digital filter sampling rate N₂is selected to be sufficiently large that the digital filter output signal 109 is very similar to, or exactly the same as, the signal 102 shown in FIG. 8 that does not include test pulses 104 and 106. Again, as stated above, the selected sampling rates N₁, N₂and N₃are sufficiently faster than the controlled vehicle system response times that the loss of the sampled angular rate sensor signals following insertion of the sensor test pulses does not adversely affect the system responses.
As illustrated in FIGS. 10 and 11A, the alternate embodiment of the invention effectively discards a predetermined number of analog to digital converter output data samples during the sensor test. In the preferred embodiment, four data points following the initial application of the test pulse are discarded; however, the application also may be practiced with the discarding of more or less than four data points. Thus, in the preferred embodiment, a positive test pulse ST1 is injected at N₃milliseconds in FIG. 11 and the data points that are taken at (N₃+N₁), (N₃+2N₁), (N₃+3N₁) and (N₃+4N₁) milliseconds are discarded. Similarly, a negative test pulse ST2 is injected at 2N₃milliseconds in FIG. 11 and the data points that are taken at (2N₃+N₁), (2N₃+2N₁), (2N₃+3N₁) and (2N₃+4N₁) milliseconds are discarded. In place of the discarded data points, the last filter output signals, which would be at (N₃−N₁) and at (2N₃−N₁) milliseconds in FIG. 11, are used as input to the microprocessor 12.
The alternate embodiment of the method for angular rate sensors is implemented by an algorithm that is stored in a memory unit accessible by the controller 12. The algorithm is illustrated by the flow chart shown in FIGS. 12A and 12B, which is similar to the flow chart shown in FIG. 6, and is entered through block 120. As in the algorithm described above, the first three functional blocks shown in FIG. 12A initialize the program. Thus, in functional block 122, the error flag is reset while the an error flag count EC and fault counts FC1 and FC2 are set to zero in functional blocks 124 and 126, respectively. The algorithm continues to block 128 which represents the same error flag count/clear subroutine that is shown in FIG. 7. As described above, after the error flag has been set, the error flag count/clear subroutine is operative to track the time that the flag has been set without a reoccurrence of a response voltage error; and, upon reaching the predetermined time period without an additional error, to reset the error flag.
The algorithm then proceeds to functional block 130 where the operation is delayed for a first time period DELAY1 corresponding to the test voltage rate N₃. As described above, during this period, sensor output signals are being supplied to the microprocessor portion 12A by the second digital filter 30 at a rate of N₂. Upon reaching the end of the first time delay, the algorithm advances to functional block 132 where a positive test voltage pulse ST1 is inserted into the angular rate sensor test signal input port. Then, after a time delay that. in the preferred embodiment, corresponds to the digital converter sampling rate of N₁, the response voltage, ΔST1 is measured in functional block 134 and the result is applied to the test signal input port 29 of the microprocessor portion 12A. As described above, the second digital filter 30 continues to supply angular rate sensor signals to the input port 31 of the microprocessor portion 12A at a rate of N₂.
Following measurement of the sensor response voltage, the algorithm reaches decision block 138 where the response voltage ΔST1 to the positive test signal pulse ST1 is compared to allowed maximum and minimum values in accordance with the following relationship:
Is T _MAX ≧ΔST 1≧T _MIN?, where,
T_MAXis the upper limit for the allowable output voltage range and
T_MINis the lower limit for the allowable output voltage range.
If, in decision block 138 it is determined that the response voltage ΔST1 is outside of the allowable voltage response range, the algorithm transfers to functional block 140 where the first fault count FC1 is indexed. The algorithm then continues to functional block 142 where the delay DELAY1 preceding the injection of the next test pulse is implemented. However, if it is determined in decision block 138 that the response voltage ΔST1 is within the allowable voltage response range, the algorithm transfers to functional block 144 where the first fault count FC1 is zeroed. The algorithm then continues to functional block 142 where the operation is delayed for a second time period DELAY1 corresponding to the test voltage rate N₃.
After completion of the delay in functional block 142, the algorithm then continues to functional block 145 where the negative test pulse voltage ST2 is injected into the angular rate sensor test signal input port. Then, again following a time delay, the response voltage, ΔST2 is measured in functional block 146 and the result applied to the test signal input port 29 of the microprocessor portion 12A. As before, the second digital filter 30 continues to supply angular rate sensor signals to the input port 31 of the microprocessor portion 12A at a rate of N₂.
Following measurement of the sensor response voltage, the algorithm reaches decision block 150 where the response voltage ΔST2 to the negative test signal pulse ST2 is compared to allowed maximum and minimum values in accordance with the following relationship:
Is −T _MAX ≧ΔST 1≧−T _MIN?, where,
−T_MAXis the lower limit for the allowable output voltage range and
−T_MINis the upper limit for the allowable output voltage range.
If, in decision block 150, it is determined that the response voltage ΔST2 is outside of the allowable voltage response range, the algorithm transfers to functional block 152 where the second fault count FC2 is indexed. The algorithm then continues to functional block 154, which is shown in FIG. 12B where a total fault count FCT is computed as the sum of the first and second fault counts, FC1 and FC2, respectively. However, if it is detennined in decision block 150, that the response voltage ΔST2 is within the allowable voltage response range, the algorithm transfers to functional block 156 where the second fault count FC2 is zeroed. The algorithm then continues to functional block 154.
After the total fault count FCT is determined in functional block 154, the algorithm advances to a series of three decision blocks labeled 156, 158 and 160 where the fault counts and total fault counts are compared to predetermined fault count thresholds. Thus, in decision block 156, the first fault count FC1 is compared to a maximum allowable fault count threshold FC1 _MAX. If FC1 is less than or equal to FC1 _MAX, the algorithm transfers to decision block 158 where second fault count FC2 is compared to a maximum allowable fault count threshold FC2 _MAX. If FC2 is less than or equal to FC2 _MAX, the algorithm transfers to decision block 160 where the total fault count FCT is compared to a maximum allowable fault count threshold FCT_MAX. If FCT is less than or equal to FCT_MAX, the algorithm transfers to decision block 162 where the algorithm where it is determined whether or not the algorithm should continue.
However, if in any of the decision blocks 156, 158 or 160, the count exceeds the corresponding allowable maximum count threshold, a fault is declared and the algorithm transfers to functional block 164 where the total fault count FCT is set to zero. The algorithm continues to functional block 166 where the error flag is set and then to functional block 168 where the error flag count EC is set to zero. After setting EC to zero, the algorithm advances to decision block 162. In the preferred embodiment, a failure is declared when any of the fault counts, FC1, FC2, or FCT exceeds a maximum of eight counts; however, other values may be utilized for the maximum fault counts. Additionally, the fault count thresholds also may have different values from one another. Because the test signals alternate between positive and negative pulses, in the preferred embodiment, the algorithm will take twice as long to declare a fault for FC1 or FCT2 than to declare a fault for FCT.
Similar to the decision block 82 in FIG. 6, in decision block 162, a specific test regarding the vehicle is used to determine whether the algorithm should continue, such as for example, checking to determine if the vehicle ignition is still on. If the continuation is needed, the algorithm transfers back to functional block 128 in FIG. 12A where the error flag count/clear subroutine is entered and the algorithm continues as described above. If the continuation is not needed, the algorithm transfers to exit block 170 and terminates.
The present invention also contemplates that the angular rate sensor test fault thresholds are temperature and noise compensated. Thus, a nominal value for each of the self test response voltages ΔST_xas a function of temperature T is given by the following formula:
ΔST _{x nominal deg/s}(T)=ΔST _{x nominal volt}(T)/K(T); where, ΔST_{x nominal volt}(T)=ΔST _x+a_— ΔST _x* [0.0084*(25−T)]+b_ΔST_x* [0.0084*(25−T)]²and
K(T)=Sens+a_Sens *[0.0084*(25−T)]+b_Sens *[0.0084*(25−T) ]², with x=1 or 2 and ΔST1, a_— ΔST1, b_— ΔST1, ΔST2, a_— ΔST2, b_— ΔST2,
Sens, a_Sens and b_Sens being values that are stored in a Non-Volatile Random Access Memory (NVRAM).
The self test error fault thresholds then be based upon gain and offset sensitivity for ΔST_{x nominal deg/s}(T) in accordance with the following formulas:
Upper bound=HW_FILTER_COEFFICIENT_HIGH *ΔST _{x nominal deg/s}(T) +threshold value calculated above, and Lower bound=HW_FILTER_COEFFICIENT_LOW *ΔST _{x nominal deg/s}(T) −threshold value calculated above.
The above threshold bound calculations would be carried out before comparing the test response voltage ΔST_xto the thresholds in decision blocks 138 and 150 in FIG. 12A. Thus, the calculation for the ΔST1 bounds may be completed during the measurement of the first response voltage in functional block 134 (not shown). Similarly, the calculation for the ΔST2 bounds may be completed during the measurement of the second response voltage in functional block 146 (not shown).
Four additional embodiments of the invention are illustrated in FIGS. 13 through 16. These additional embodiments provide the capability to ignore response voltages caused by external actions, such as, for example, power supply spikes and external noise, without resetting the fault counters. Such extraneous signals are identified by monitoring the rise time and/or frequency of the signal.
The alternate embodiment of the algorithm shown in FIG. 13 is a modification of the basic flow chart shown in FIG. 6 and blocks shown in FIG. 13 that are the same as blocks shown in FIG. 6 have the same numerical identifiers. The change shown in FIG. 13 involves measuring the rate of rise of the response voltage in functional block 66 and the inclusion of decision block 180 where the rate of rise of the response voltage is compared to a rate of rise threshold. The rate of rise decision block 180 is only reached upon the determination in decision block 72 that the response is not within the bounds. If, in decision block 180, the response voltage rate of rise is less than or equal to a rate of rise threshold SR_MAX, the fault counter FC is indexed in functional block 74. If, in decision block 180, the rate of rise is greater than the rate of rise threshold SR_MAX, the algorithm transfers directly to decision block 76, skipping the indexing of the fault counter FC 74. The use of the algorithm shown in FIG. 13 allows an extraneous signal having too fast of a rise time to be ignored without resetting the fault counter.
The alternate embodiment of the algorithm shown in FIG. 14 involves measuring the frequency of the response voltage in functional block 66 and the inclusion of decision block 182 where the frequency of the response voltage is compared to a signal frequency threshold. The response voltage frequency decision block 182 is only reached upon the determination in decision block 72 that the response is not within the bounds. If, in decision block 182, the response voltage frequency is less than or equal to a frequency threshold SF_MAX, the fault counter FC is indexed in functional block 74. If, in decision block 182, the rate of rise is greater than the frequency threshold SF_MAX, the algorithm transfers directly to decision block 76, skipping the indexing of the fault counter FC 74. The use of the algorithm shown in FIG. 14 allows an extraneous signal having too fast of a frequency to be ignored without resetting the fault counter.
The alternate embodiments illustrated in FIGS. 15 and 16 include consideration of both the rate of rise and the frequency of the response voltage with both of the parameters being measured in functional block 66. Thus, both decision blocks 180 and 182 are shown in FIGS. 15 and 16. In FIG. 15, if either the rate of rise threshold SF_MAX+or the frequency threshold SF_MAXis exceeded, the algorithm transfers directly to decision block 76, skipping the indexing of the fault counter FC 74. In FIG. 16, only if both the rate of rise threshold SF_MAX+and the frequency threshold SF_MAXare exceeded, the algorithm transfers directly to decision block 76, skipping the indexing of the fault counter FC 74.
While the alternate embodiments discussed above and illustrated in FIGS. 13 through 15 have described with regard to modification of the algorithm shown in FIG. 6, it will be appreciated that the invention also contemplates modifying the algorithm shown in FIG. 12 in a similar manner (not shown).
While the preferred embodiment of the invention has been described and illustrated above, it will be appreciated that the flow charts shown are intended to be exemplary of the methods, and that specific details and the sequence of the steps shown may vary. Also, while the preferred embodiment for testing the angular rate sensor was illustrated and described as utilizing alternating positive and negative test pulses, it will be appreciated that the invention also may be practiced with selected combinations of positive and negative pulses, such as, for example, two positive pulses followed by one negative pulse. Furthermore, the invention contemplates utilizing random sequences of positive and negative pluses for test signals. The invention also contemplates applying sequenced or randomly selected positive and negative test signals to the test port of accelerometers. Additionally, while the preferred embodiment of the invention has been illustrated and described for accelerometers and yaw rate sensors, it will be appreciated that the invention also may be practiced for other sensors such as, for example, pressure sensors, rotational sensors, optical based sensors, Hall effect based sensors and Linear Variable Displacement Transducers.
In accordance with the provisions of the patent statutes, the principle and mode of operation of this invention have been explained and illustrated in its preferred embodiment. However, it must be understood that this invention may be practiced otherwise than as specifically explained and illustrated without departing from its spirit or scope.

Claims

1. A method for verifying proper operation of a motion sensor comprising the steps of:

(a) providing a motion sensor;

(b) injecting a test pulse into the motion sensor;

(c) measuring the output of the motion sensor after a predetermined delay period;

(d) comparing the motion sensor output to an acceptable output range; and

(e) declaring a fault upon determining that the sensor output measured in step (a) is outside of the acceptable output range.

2. The method of claim 1 wherein the test signal is periodically applied to the motion sensor.

3. The method of claim 2 wherein an error signal is generated subsequent to step (e) after a predetermined number of faults caused by consecutive test signals have been detected.

4. The method of claim 3 wherein the motion sensor provided in step (a) is an accelerometer.

5. The method of claim 3 wherein the periodic test signal is alternately positive and negative.

6. The method of claim 4 wherein an error signal is generated subsequent to step (e) after a predetermined number of faults caused by consecutive positive test signals have been detected.

7. The method of claim 6 wherein the motion sensor provided in step (a) is an angular rate sensor.

8. The method of claim 4 wherein an error signal is generated subsequent to step (e) after a predetermined number of faults caused by consecutive negative test signals have been detected.

10. The method of claim 4 wherein an error signal is generated subsequent to step (e) after a predetermined number of total faults caused by consecutive positive and negative test signals have been detected.

11. The method of claim 2 wherein the upper and lower limits of the acceptable output range utilized in step (d) are based upon at least one variable parameter.

12. The method of claim 11 wherein the upper and lower limits of acceptable output range utilized in step (d) are based upon at least the ambient temperature.

13. The method of claim 11 wherein the upper and lower limits of acceptable output range utilized in step (d) are based upon at least the variation of parts parameters.

14. The method of claim 11 wherein the upper and lower limits of acceptable output range utilized in step (d) are based upon at least vehicle dynamics.

15. The method of claim 3 wherein the output of the motion sensor is sampled at a rate of N₁and, during step (b), the test signal is injected into the motion sensor at a rate of N₃, with N₃being greater than N₁.

16. The method of clam 15 wherein the injected test signal from step (b) is passed through a digital filter prior and further wherein the digital filter generates an output signal at a rate of N₂with N₁<N₂<N₃.

17. The method of claim 16 further including, subsequent to finding that the motion sensor output is within an acceptable output range in step (d), supplying the output of the digital filter to at least one vehicle control system.

18. The method of claim 17 wherein the at least one vehicle control system includes an electronically controlled vehicle brake system.

19. The method of claim 3 wherein the periodic test signal includes sequenced positive and negative signals.

20. The method of claim 3 wherein the periodic test signal includes random positive and negative signals.