CN102507009B - Debugging device used for simulating thermal imager operation - Google Patents
Debugging device used for simulating thermal imager operation Download PDFInfo
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Abstract
The invention discloses a debugging device used for simulating thermal imager operation. The debugging device comprises a FPGA (field programmable gate array) controller, a PC (poly carbonate) machine, a monitor, a first SD (secure digital memory) card and a second SD card, wherein a network chip and a network interface are arranged between the FPGA controller and the PC machine; a video coding chip and a video interface are connected between the FPGA controller and the monitor, and a first SD card slot is connected between the FPGA controller and the first SD card; a second SD card slot is connected between the FPGA controller and a second SD card, and a thermal imager interface is connected between the FPGA controller and a thermal infrared imager; and an infrared identification module interface is connected between the FPGA controller and a target recognition module. The debugging device can collect and store a sample image in real time according to a time sequence of a digital interface of the thermal infrared imager, and the stored sample image can be output according to the time sequence of the digital interface of a thermal imager.
Description
Technical field
The present invention relates to a kind of image that is applicable to the infrared identification system processes, more particularly, refer to that a kind of FPDA of employing chip is the debugging apparatus for generation of the infrared digital signal on basis, this debugging apparatus has substituted the work of thermal imaging system in the existing infrared identification system.
Background technology
Infrared imagery technique is the poor scene image that forms of infrared radiation that utilizes between background and the target, is Now Domestic and the focus of high-tech area research in the world.Infrared imaging system belongs to imaging and passive imaging, therefore has good disguise.It has broken through illumination and spectral response range to the visual constraints of human eye, and is therefore farther than visible light systemic effect distance, has stronger smog and sees through ability and antijamming capability, almost can accurate all weather operations.Based on these good characteristics of infrared imaging system, it has been widely used in various military and civilians field.
Based on the target detection of infrared image, it is a core technology of the application systems such as Infra-Red Search ﹠ Track System, precise guidance system, infraed early warning system, large visual field targeted surveillance system, satellite remote sensing system, boats and ships active safety early warning system.That delivers in " infrared " in February, 2007 is divided into three modules about disclosing a kind of infrared identification system in " Embedded Infrared Target Recognition and Tracking systematic research " by its function: infrared signal acquisition processing module (abbreviation infrared module), target recognition and tracking module (abbreviation identification module) and embedded main control module (abbreviation main control module).Collection and the A/D conversion of infrared signal acquisition processing module in order to finish infrared image; Target recognition and tracking module receives digital infrared image, and dynamic object is carried out automatic search, identification, tracking, and the image that will process and matching result are sent to embedded main control module; Embedded main control module is responsible for the control of whole system, and friendly human-computer interaction interface is provided.
Identification module in the infrared identification system, the normal embedded processing plate that adopts carries out image recognition and tracking processing, and because the thermal imaging system sensor in the system mostly is digital interface, the embedded processing plate often adopts FPGA and DSP structure or independent FPGA structure.There is following problem in debugging for identification module disposable plates hardware and software algorithm:
(1) first step of identification module disposable plates debugging is the sequential according to thermal imaging system, as frame synchronization, row synchronously, data useful signal and clock signal obtain gathering correct infrared image.This step is usually more consuming time, particularly for the thermal imaging system of high frame frequency, wiring or the physically unequal delay that causes of line length tend to cause collecting error image on the disposable plates hardware, debugging needs thermal imaging system to work for a long time frequently, for the refrigeration mode thermal imaging system of costliness, working long hours affects detector serviceable life.
(2) the infrared identification algorithm needs continuous debugging just can reach best effect, particularly for maneuvering target recognition and tracking under the complex environment, requires algorithm to have good real-time and robustness, needs for a long time debugging.Often take at present to read sequence image software debugging algorithm on the PC, transplant again algorithm after debugging successfully to flush bonding processor, to move.But PC is different with the software runtime environment of embedded processing plate, so that this adjustment method does not reach desirable effect.
(3) for high pixel resolution thermal imaging system, every pixel is usually all greater than 8, and commonly used has 14,16, and the image of preserving with the picture form all is 8 on PC.If carry out the precision that the algorithm debugs has just lost image with 8 images, also can affect the debug results of algorithm.
(4) when carrying out the outfield experiments chamber, experiment sample is very precious, and because the complicated singularity of environment and the limitation of existing apparatus, so that it is very difficult to preserve these samples.
Therefore, for above problem, the present invention proposes a kind of debugging apparatus of simulation thermal infrared imager sequential simple in structure, easy to use, in order to substitute the infrared signal acquisition module, carries out the debugging to infrared identification module.
Summary of the invention
The purpose of this invention is to provide a kind of debugging apparatus for simulating thermal imager operation, this debugging apparatus is according to thermal infrared imager digital interface sequential Real-time Collection and storing sample image, and the sample image of storage can be exported according to thermal imaging system digital interface sequential.This debugging apparatus adopts the monolithic fpga chip to realize, application HDL hardware description language realization FPGA communicates by letter with each interface; Show that by image acquisition, image storage, image reproducing and image several steps realize the function of " off-line " thermal imaging system, and can realize by changing the hardware description language restructural simulation of various thermal imaging systems, internal field and the outfield experiments of infrared identification system had positive effect.
A kind of debugging apparatus for simulating thermal imager operation of the present invention, this debugging apparatus include FPGA controller (50), PC (10), monitor (20), a SD card (30), the connection of the 2nd SD card (40); Be connected with network chip (10A) and network interface (10B) between FPGA controller (50) and the PC (10); Be connected with video coding chip (20A) and video interface (20B) between FPGA controller (50) and the monitor (20); Be connected with the first SD card slot (30A) between FPGA controller (50) and the SD card (30); Be connected with the second SD card slot (40A) between FPGA controller (50) and the 2nd SD card (40); Be connected with thermal imaging system interface (100A) between FPGA controller (50) and the thermal infrared imager; Be connected with infrared identification module interface (200A) between FPGA controller (50) and the target identification module.
Described FPGA controller (50) is divided by the function that realizes and is included sequential receiving interface module (50A), state machine acquisition control module (50B), the first cache module (50C), height modular converter (50D), the second cache module (50E), coding module (50F), the 3rd cache module (50G), ethernet controller (50H), the 4th cache module (50J), thermal imaging system sequential output module (50K), SD card read-write control module (50L);
Sequential receiving interface module (50A) is used for the digital infrared time sequence information (100) of thermal imaging system output is carried out the clutter filtering, removes burr, eliminates wiring delay, is adjusted rear time sequence information (512);
State machine acquisition control module (50B) is used for gathering adjusting rear time sequence information (512), obtains effective video image information (511);
The first cache module (50C) is used for preserving effective video image information (511), calls to make things convenient for SD card read-write control module (50L); The input end of this first cache module (50C) buffer memory is the 14bit data bus, and the output terminal of buffer memory is the data bus of 4bit;
SD card read-write control module (50L) first aspect reads the effective video image information (511) in the first cache module (50C); Second aspect is carried out the CRC check position to effective video image information (511) and is loaded, and obtains CRC check image information (51), and this CRC check image information (51) is kept in the SD card (30) or in the 2nd SD card (40); The third aspect is called CRC check image information (51) with the sequential of reading the SD card, obtains sample image information (52) output;
The second cache module (50E) is used for the sample image information (52) of buffer memory SD card read-write control module (50L) output, and exports second and call sample cache information (521) to coding module (50F);
It is the processing of encoding of the data layout of 4:2:2 according to CCIR-656YUV that coding module (50F) calls sample cache information (521) to second, obtains analog video image information (523);
Height modular converter (50D) carries out high pixel resolution to the sample image information (52) of SD card read-write control module (50L) output and converts low pixel resolution to, obtains low pixel resolution image information (531);
The 3rd cache module (50G) is used for the low pixel resolution image information (531) of buffer memory, and exports the 3rd and call sample cache information (532) to net controller (50H) too;
Ethernet controller (50H) calls sample cache information (532) with the 3rd and is transferred to PC (10);
The 4th cache module (50J) is used for the sample image information (52) of buffer memory SD card read-write control module (50L) output, and exports the 4th and call sample cache information (541) to thermal imaging system sequential output module (50K);
Thermal imaging system sequential output module (50K) first aspect is called sample cache information (541) to the 4th and is carried out clock frequency extraction T
K, frame synchronization extracts F
K, row extracts synchronously H
K, data enable signal extracts D
KSecond aspect adopts sequential-Image Matching Strategy to call sample cache information (541) to the 4th to carry out sequential and judge and process, and obtains the thermal imaging system digital interface time sequence information (200) identical with the sequential of the digital Infrared Image Information (100) of thermal imaging system output.
The advantage of the debugging apparatus of simulating thermal imager operation of the present invention is:
1. debugging apparatus of the present invention has solved when the infrared identification module of debugging, and the frequent switch of thermal imaging system is affected the thermal imaging system life-span, and particularly the refrigeration mode thermal imaging system impact on costliness is larger.This debugging apparatus can replace thermal imaging system to export digital infrared signal, simulates the duty of complete thermal imaging system and does not affect debug results.
2. debugging apparatus of the present invention can be preserved raw data when substituting the thermal imaging system of high pixel resolution, and can not affect image resolution ratio and precision according to the output of thermal imaging system interface sequence off-line, and crucial effect has been played in the debugging of infrared identification module.
3. debugging apparatus of the present invention adopts the monolithic fpga chip to realize, its volume is little, lightweight, be easy to carry, plug and play, to different thermal imaging systems, only just slightly make an amendment by the HDL language in the debugging apparatus and can simulate different thermal imaging systems, especially for outfield experiments, because circumstance complication, sample is precious, and this debugging apparatus is particularly suitable for collecting sample and carries out the sample reproduction.
4. debugging apparatus product of the present invention adopts two high speed SD cards, and memory capacity is large, can work under big bang, hot conditions, and the storage data have broad application prospects when being adapted at the field and carrying out outfield experiments.
5. debugging apparatus of the present invention can not affect infrared identification module work when capturing sample image, can obtain simultaneously recognition result.
Description of drawings
Fig. 1 is connected to synoptic diagram in the Infrared Target Recognition and Tracking system with debugging apparatus of the present invention.
Fig. 2 is the hardware connection diagram of debugging apparatus of the present invention.
Fig. 3 is the structured flowchart of FPGA controller in the debugging apparatus of the present invention.
Fig. 4 is the sequential control figure of FPGA controller in the debugging apparatus of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing.
Referring to shown in Figure 1, the debugging apparatus of the present invention's design is to be connected between existing target recognition and tracking module (abbreviation identification module) and the infrared signal acquisition processing module (abbreviation infrared module)." infrared signal acquisition processing module " is also referred to as thermal infrared imager hereinafter.Thermal infrared imager is used for exporting digital Infrared Image Information 100 to debugging apparatus of the present invention; Target recognition and tracking module is used for receiving the thermal imaging system digital interface time sequence information 200 of debugging apparatus output of the present invention.When target recognition and tracking module was debugged, thermal infrared imager was only opened once, and debugging apparatus of the present invention then keeps digital Infrared Image Information 100, to make things convenient for again calling of target recognition and tracking module.Be conducive to like this protect the use of thermal infrared imager, improved simultaneously the serviceable life of thermal infrared imager.Infrared Targets recognition and tracking module is the application of debugging apparatus of the present invention.
Referring to shown in Figure 2, the present invention is a kind of debugging apparatus for simulating thermal imager operation, and this debugging apparatus includes FPGA controller 50, PC 10, monitor 20, a SD card 30,40 connections of the 2nd SD card.
Be connected with network chip 10A and network interface 10B between FPGA controller 50 and the PC 10.
Be connected with video coding chip 20A and video interface 20B between FPGA controller 50 and the monitor 20.
Be connected with the first SD card slot 30A between FPGA controller 50 and the SD card 30.
Be connected with the second SD card slot 40A between FPGA controller 50 and the 2nd SD card 40.
Be connected with thermal imaging system interface 100A between FPGA controller 50 and the thermal infrared imager.
Be connected with infrared identification module interface 200A between FPGA controller 50 and the target identification module.
PC 10 is a kind ofly can according to the program of prior storage, carry out automatically, at high speed the modernized intelligent electronic device of massive values computation and various information processings.Minimalist configuration is CPU 2GHz, internal memory 2GB, hard disk 20GB; Operating system is windows 2000/2003/XP.In the present invention, PC 10 is used for showing and observes sample image.
Monitor 20 is used for observing the infrared sample image of high pixel resolution.In the present invention, the coding module 50F of high pixel resolution image in FPGA controller 50 of the thermal imaging system that collects is converted into analog video image information 523, and this analog video image information 523 is shown by monitor 20.In the present invention, the analog video image information 523 of demonstration is different at the image effect that shows in the sample image that shows in the PC 10 and the monitor 20, the analog video image information 523 that shows has abundanter image detail, and with analog video image information 523 as observation caliber.
The one SD card 30 links to each other with FPGA controller 50 by SD card slot as the video memory of FPGA controller 50, and a SD card is supported 2.0 version technique standards, supports hot plug.The one SD the core of the card sheet adopts SDHC10, and capacity is 32G.
The 2nd SD card 40 links to each other with FPGA controller 50 by SD card slot as the video memory of FPGA controller 50, and the 2nd SD card is supported 2.0 version technique standards, supports hot plug.The 2nd SD the core of the card sheet adopts SDHC10, and capacity is 32G.In the present invention, in order to enlarge memory capacity, adopting two SD cards, is 50Hz for frame frequency, and the image size is 640 * 512, and pixel resolution is the thermal infrared imager of 14bit, energy Coutinuous store 2 hours.The SD card is controlled by SD card read-write control module 50L, adopts the 4-bitSD mode bus to realize that SD card read-write control module 50L is to operations such as the initialization of SD card, read-writes.
In the present invention, network chip 10A links to each other with PC 10 by RJ45 socket (network interface 10B), ethernet interface module 50H controls on the one hand network chip 10A and finishes image transmitting, ethernet interface module 50H finishes the initialization setting to network chip 10A on the other hand, read video data among the 3rd cache module 50G according to the order of FPGA controller 50, carry out network and send.Video coding chip 20A adopts chip Q9 connector (20B) to link to each other with monitor 2, and the coding module 50F control video coding chip 20A in the FPGA controller 50 finishes analog video output.
Thermal imaging system interface 100A is 9 pin plugs.
Infrared identification module interface 200A is 25 pin plugs.
The first SD card slot 30A and the 2nd SD card are inserted the MINISD deck of Hong Kong Si Masi company, rated voltage 50VAC, and rated current 1A, insulation resistance 1000M Europe, withstand voltage 500V, contact element are aldary, gold-plated tin, plastic body are thermoplastic LCP plastics.
Referring to shown in Figure 3, FPGA controller 50 in the debugging apparatus of the present invention is to realize with fpga chip in the embedded processing plate, employing Verilog HDL (HDL:Hardware Discription Language, software version ISE10.1) hardware description language realization fpga chip is communicated by letter with each interface.
Referring to shown in Figure 3, FPGA controller 50 of the present invention is divided by the function that realizes and is included: sequential receiving interface module 50A, state machine acquisition control module 50B, the first cache module 50C, height modular converter 50D, the second cache module 50E, coding module 50F, the 3rd cache module 50G, ethernet controller 50H, the 4th cache module 50J, thermal imaging system sequential output module 50K, SD card read-write control module 50L.
(1) sequential receiving interface module 50A
Sequential receiving interface module 50A is used for the digital infrared time sequence information 100 of thermal imaging system output is carried out the clutter filtering, removes burr, eliminates wiring delay, is adjusted rear time sequence information 512.
In order to obtain undelayed clock information, need clock signal is connected on the global clock on the pin, eliminate clock jitter and delay with digital dock administration module (DCM:Digital Clock Management).
Reach synchronously the data useful signal for frame synchronization, row, need to eliminate the burr signal of introducing in the transmission course with latch.
(2) state machine acquisition control module 50B
State machine acquisition control module 50B is used for gathering adjusting rear time sequence information 512, obtains effective video image information 511.
In the gatherer process of a frame image data, most importantly be exactly a frame image data is begun judgement with the finish time, the present invention realizes accurate control to the gatherer process terminal with state machine.
The rising edge of frame synchronization represents the beginning of a two field picture, and in line synchronizing signal effectively and data enable signal when effective, the view data on the data bus of rising edge clock collection thermal imaging system interface is effective video image information 511.The state control flow of gatherer process terminal of determining a two field picture based on these three signals (frame synchronizing signal, line synchronizing signal, data enable signal) is as follows:
(A) if it is low detecting the frame synchronizing signal level, change step (B) over to;
(B) if detect the frame synchronizing signal level for high, change step (C) over to, begin simultaneously the collection of a frame new images;
(C) if detect the line synchronizing signal level for high, change step (D) over to;
(D) if it is low detecting the line synchronizing signal level, show that then an image frame grabber process finishes, and changes step (A) over to, otherwise carry out effective image data acquiring during data useful signal level is height.
In the present invention, the effective video image information 511 of state machine acquisition control module 50B output is 14bit pixel bit wide image, and the data bus bit wide of thermal imaging system is 14bit, collects a grey scale pixel value at every turn.
(3) first cache module 50C
The first cache module 50C is used for preserving effective video image information 511, calls to make things convenient for SD card read-write control module 50L.
The first cache module 50C is an asynchronous memory, is used for storing, cushioning two data transmission between the asynchronous clock.Input end at buffer memory is the 14bit data bus, and the output terminal of buffer memory is the data bus of 4bit.
(4) SD card read-write control module 50L
SD card read-write control module 50L first aspect reads the effective video image information 511 among the first cache module 50C; Second aspect is carried out the CRC check position to effective video image information 511 and is loaded, obtain containing the image information 51 (referred to as the CRC check image information) of CRC check position, this CRC check image information 51 is kept in the SD card 30 or in the 2nd SD card 40; The third aspect is called CRC check image information 51 with the sequential of reading the SD card, obtains 52 outputs of sample image information.
SD card read-write control module 50L adopts no write de-lay, playback mode, clock is 50MHz, each read-write operation sends first 1bit start bit 0, then send the effective video image information 511 of 512bit on 4 bit data bus, and then send the 16bitCRC check code that is obtained by the effective video image information, send at last 1 position of rest 1.
(5) second cache module 50E
The second cache module 50E is used for the sample image information 52 of buffer memory SD card read-write control module 50L output, and exports second and call sample cache information 521 to coding module 50F.
The second cache module 50E is an asynchronous memory, is used for storing, cushioning two data transmission between the asynchronous clock.Input end at buffer memory is the 4bit data bus, and the output terminal of buffer memory is the data bus of 14bit.
(6) coding module 50F
It is the processing of encoding of the data layout of 4:2:2 according to CCIR-656YUV that coding module 50F calls sample cache information 521 to second, obtain analog video image information 523, this analog video image information 523 is the high definition video of YPrPb progressive-scan format.
Video encoding module at first is configured by the register of I2C bus to video coding chip, adopts master slave mode to carry out register configuration here.After register configuration was finished, externally under the control of level, vertical and blanking signal or EAV/SAV sequence code, it was among the input signal that suitable synchronizing signal is inserted into digit data stream.
(7) height modular converter 50D
Height modular converter 50D carries out high pixel resolution to the sample image information 52 of SD card read-write control module 50L output and converts low pixel resolution to, obtains low pixel resolution image information 531.
Height modular converter 50D carries out gray-scale statistical to the former frame image, with the gray-scale statistical result of former frame image a rear two field picture is processed.Obtain the poor of the maximal value of a two field picture pixel and minimum value and maximal value and minimum value during gray-scale statistical.Minimum value obtained intermediate pixel when current frame pixel deducted gray-scale statistical, and the most-significant byte of then getting intermediate pixel according to the difference of minimum and maximum value obtains conversion output.
(8) the 3rd cache module 50G
The 3rd cache module 50G is used for the low pixel resolution image information 531 of buffer memory, and exports the 3rd and call sample cache information 532 to net controller 50H too.
The 3rd cache module 50G is an asynchronous memory, is used for storing, cushioning two data transmission between the asynchronous clock.Input end at buffer memory is the 8bit data bus, and the output terminal of buffer memory is the data bus of 8bit.
(9) ethernet controller 50H
In the present invention, too net controller 50H adopts the DM9000 chip.
(A) ethernet controller 50H utilizes write operation register MWCMD to write the transmission Frame in the transmission buffer zone of DM9000A, comprises the pixel data of 6 byte destination-mac address, 6 byte source MACs, 2 byte data length or protocol type, delegation's image.
(B) Frame length is write transmission packet length register TPLR.Frame length is the total length that comprises the packet informations such as destination address, source address, and the high byte of length is write FDH, and low byte writes FCH.
(C) bit[0 of transmit control register TCR is set]=1, sending to DM9000A and to send the packet instruction, DM9000A can insert header and the initial separator of frame etc. automatically, begins to send Frame after being disposed again.
In the present invention, too net controller control network chip and PC 10 are realized data interaction.
(10) the 4th cache module 50J
The 4th cache module 50J is used for the sample image information 52 of buffer memory SD card read-write control module 50L output, and exports the 4th and call sample cache information 541 to thermal imaging system sequential output module 50K.
The 4th cache module 50J is an asynchronous memory, is used for storing, cushioning two data transmission between the asynchronous clock.Input end at buffer memory is the 4bit data bus, and the output terminal of buffer memory is the data bus of 14bit.
(11) thermal imaging system sequential output module 50K
Thermal imaging system sequential output module 50K first aspect is called sample cache information 541 to the 4th and is carried out clock frequency extraction T
K, frame synchronization extracts F
K, row extracts synchronously H
K, data enable signal extracts D
KSecond aspect adopts sequential-Image Matching Strategy to call sample cache information 541 to the 4th to carry out sequential and judge and process, and obtains the image information 200 (referred to as thermal imaging system digital interface time sequence information 200) identical with the sequential of the digital Infrared Image Information 100 of thermal imaging system output.
Referring to shown in Figure 4, in the present invention, thermal imaging system sequential output module 50K to image sequential control adopted sequential-Image Matching Strategy, this sequential-Image Matching Strategy includes the following step:
(A) at first make frame synchronizing signal T
K, line synchronizing signal H
K, data enable signal D
KInvalid, pixel clock is 29.5MHz; Start the column counter counting, counting clock is pixel clock; Whether when counting down to 334425, it is effective to detect among the 4th cache module 50J the half-full signal of FIFO, if true, enables that FIFO reads enable signal among the 4th cache module 50J, forwards step (B) to, simultaneously zero clearing column counter; If false, the zero clearing counter restarts counting, and when counting down to 334425, whether effective, repeat this step, until forward step (B) to if detecting again among the 4th cache module 50J the half-full signal of FIFO;
(B) column counter makes frame synchronizing signal T since 0 counting
K, line synchronizing signal H
KEffectively, column counter is that even number makes, and makes data enable signal D
KEffectively, when column counter is odd number, make data enable signal D
KInvalid; Simultaneously, sample that data fifo bus epigraph data are sent to data bus among the thermal imaging system sequential output module 50K among the 4th cache module 50J; After column count reaches 319, make row extract synchronously H
K, data enable signal extracts D
KInvalid, the column counter zero clearing, it is invalid to make among the 4th cache module 50J FIFO read enable signal, stops to gather data fifo bus epigraph data among the 4th cache module 50J, forwards simultaneously step (C) to;
(C) column counter restarts counting, and each rising edge clock column counter adds 1, after counting reaches 187, linage-counter is added 1, and with the column counter zero clearing, forwards simultaneously step (D) to
(D) whether judge linage-counter greater than 239, if true, make frame synchronizing signal T
KInvalid, forward simultaneously step (A) to; If false, forward step (B) to.
In FPGA, these four steps are controlled by state machine, and 4 steps are respectively idle, high_H, low_H, tran_on, and the function of sequential output module 50K is finished in loop jump between this one of four states, obtains the digital interface sequential of thermal imaging system.
In the present invention, FPGA controller 50 includes the first cache module 50C, the second cache module 50E, the 3rd cache module 50G and the 4th cache module 50J.
What the first cache module 50C stored is image information 511 after the sequential adjustment, and the data bus of image information 511 is 14bit after this sequential adjustment, and clock is 14.75MHz; And the first cache module 50C to export to the data bus of the image information of SD card read-write control module 50L be 4bit, clock is 50MHz;
The second cache module 50E storage be second to call sample cache information 521; This second data bus that calls sample cache information 521 is 14bit, and clock is 14.75MHz; And the data bus of the sample image information 52 of SD card read-write control module 50L output is 4bit, and clock is 50MHz;
The 3rd cache module 50G storage be the 3rd to call sample cache information 532; The 3rd data bus that calls sample cache information 532 is 8bit, and clock is 50MHz; And the data bus of the low pixel resolution image information 531 of height modular converter 50D output is 8bit, and clock is 50MHz;
The 4th cache module 50J storage be that the 4th to call the data bus that sample cache information 541, the four calls sample cache information 541 be 14bit, clock is 14.75MHz; And the data bus of the sample image information 52 of SD card read-write control module 50L output is 4bit, and clock is 50MHz.
The first cache module 50C adopts the ping-pong structure of two FIFO (being first FIFO, second FIFO) to carry out data transmission, and each FIFO arranges half-full sign.When the half-full signal of first FIFO is effective, SD card read-write control module 50L begin to read among first FIFO data and write a SD card or the 2nd SD card in, until first FIFO be sky.When second half-full signal of FIFO was effective, SD card read-write control module 50L read that data write in a SD card or the 2nd SD card among second FIFO.
The second cache module 50E adopts the ping-pong structure of two FIFO (i.e. the 3rd FIFO, the 4th FIFO) to carry out data transmission, and each FIFO arranges half-full sign.When the 3rd the half-full signal of FIFO was effective, coding module 50F began to read data and the processing of encoding among the 3rd FIFO, until the 3rd FIFO is empty.When the 4th the half-full signal of FIFO was effective, coding module 50F began to read among the 4th FIFO data processing of encoding, until the 4th FIFO is empty.
The 3rd cache module 50G adopts the ping-pong structure of a FIFO (i.e. the 5th FIFO) to carry out data transmission, and FIFO arranges half-full sign.Too net controller 50H reads among the 5th FIFO data and transfers to PC and carries out image and show.
The 4th cache module 50J adopts the ping-pong structure of two FIFO (i.e. the 6th FIFO, the 7th FIFO) to carry out data transmission, and each FIFO arranges half-full sign.When the 6th the half-full signal of FIFO was effective, thermal imaging system sequential output module 50K began to read among the 6th FIFO data and transfers to target recognition and tracking module, until the 6th FIFO is empty.When the 7th the half-full signal of FIFO was effective, thermal imaging system sequential output module 50K began to read among the 7th FIFO data and transfers to target recognition and tracking module, until the 7th FIFO is empty.
Claims (5)
1. debugging apparatus that is used for simulating thermal imager operation, it is characterized in that: this debugging apparatus includes FPGA controller (50), PC (10), monitor (20), a SD card (30), the 2nd SD card (40);
Be connected with network chip (10A) and network interface (10B) between FPGA controller (50) and the PC (10);
Be connected with video coding chip (20A) and video interface (20B) between FPGA controller (50) and the monitor (20);
Be connected with the first SD card slot (30A) between FPGA controller (50) and the SD card (30);
Be connected with the second SD card slot (40A) between FPGA controller (50) and the 2nd SD card (40);
Be connected with thermal imaging system interface (100A) between FPGA controller (50) and the thermal infrared imager;
Be connected with infrared identification module interface (200A) between FPGA controller (50) and the target identification module;
Described FPGA controller (50) is divided by the function that realizes and is included sequential receiving interface module (50A), state machine acquisition control module (50B), the first cache module (50C), height modular converter (50D), the second cache module (50E), coding module (50F), the 3rd cache module (50G), ethernet controller (50H), the 4th cache module (50J), thermal imaging system sequential output module (50K), SD card read-write control module (50L);
Sequential receiving interface module (50A) is used for the digital infrared time sequence information (100) of thermal imaging system output is carried out the clutter filtering, removes burr, eliminates wiring delay, is adjusted rear time sequence information (512);
State machine acquisition control module (50B) is used for gathering adjusting rear time sequence information (512), obtains effective video image information (511);
The first cache module (50C) is used for preserving effective video image information (511), calls to make things convenient for SD card read-write control module (50L); The input end of this first cache module (50C) buffer memory is the 14bit data bus, and the output terminal of buffer memory is the data bus of 4bit;
SD card read-write control module (50L) first aspect reads the effective video image information (511) in the first cache module (50C); Second aspect is carried out the CRC check position to effective video image information (511) and is loaded, and obtains CRC check image information (51), and this CRC check image information (51) is kept in the SD card (30) or in the 2nd SD card (40); The third aspect is called CRC check image information (51) with the sequential of reading the SD card, obtains sample image information (52) output;
The second cache module (50E) is used for the sample image information (52) of buffer memory SD card read-write control module (50L) output, and exports second and call sample cache information (521) to coding module (50F);
It is the processing of encoding of the data layout of 4:2:2 according to CCIR-656YUV that coding module (50F) calls sample cache information (521) to second, obtains analog video image information (523);
Height modular converter (50D) carries out high pixel resolution to the sample image information (52) of SD card read-write control module (50L) output and converts low pixel resolution to, obtains low pixel resolution image information (531);
The 3rd cache module (50G) is used for the low pixel resolution image information (531) of buffer memory, and exports the 3rd and call sample cache information (532) to ether net controller (50H);
Ethernet controller (50H) calls sample cache information (532) with the 3rd and is transferred to PC (10);
The 4th cache module (50J) is used for the sample image information (52) of buffer memory SD card read-write control module (50L) output, and exports the 4th and call sample cache information (541) to thermal imaging system sequential output module (50K);
Thermal imaging system sequential output module (50K) first aspect is called sample cache information (541) to the 4th and is carried out clock frequency T
KExtraction, frame synchronization F
KExtract, go synchronous H
KExtraction, data enable signal D
KExtract; Second aspect adopts sequential-Image Matching Strategy to call sample cache information (541) to the 4th to carry out sequential and judge and process, and obtains the thermal imaging system digital interface time sequence information (200) identical with the sequential of the digital Infrared Image Information (100) of thermal imaging system output.
2. the debugging apparatus for simulating thermal imager operation according to claim 1, it is characterized in that: in the thermal imaging system sequential output module (50K) sequential-Image Matching Strategy has been adopted in the control of sequential, this sequential-Image Matching Strategy includes following treatment step:
(A) at first make frame synchronization F
K, the row synchronous H
K, data enable signal D
KInvalid, pixel clock is 29.5MHz; Start the column counter counting, counting clock is pixel clock; Whether when counting down to 334425, it is effective to detect the middle half-full signal of FIFO of the 4th cache module (50J), if true, FIFO reads enable signal in the 4th cache module (50J), forwards step (B) to, simultaneously zero clearing column counter; If false, the zero clearing counter restarts counting, and when counting down to 334425, whether effective, repeat this step, until forward step (B) to if detecting again the middle half-full signal of FIFO of the 4th cache module (50J);
(B) column counter makes frame synchronization F since 0 counting
K, the row synchronous H
KEffectively, when column counter is even number, make data enable signal D
KEffectively, when column counter is odd number, make data enable signal D
KInvalid; Simultaneously, sample that data fifo bus epigraph data are sent to data bus in the thermal imaging system sequential output module (50K) in the 4th cache module (50J); After column count reaches 319, make the synchronous H of row
K, data enable signal D
KInvalid, the column counter zero clearing, it is invalid that the middle FIFO of the 4th cache module (50J) reads enable signal, stops to gather data fifo bus epigraph data in the 4th cache module (50J), forwards simultaneously step (C) to;
(C) column counter restarts counting, and each rising edge clock column counter adds 1, after counting reaches 187, linage-counter is added 1, and with the column counter zero clearing, forwards simultaneously step (D) to;
(D) whether judge linage-counter greater than 239, if true, make frame synchronization F
KInvalid, forward simultaneously step (A) to; If false, forward step (B) to.
3. the debugging apparatus for simulating thermal imager operation according to claim 1, it is characterized in that: the first cache module (50C) is an asynchronous memory, is used for storing, cushioning two data transmission between the asynchronous clock.
4. the debugging apparatus for simulating thermal imager operation according to claim 1 is characterized in that: height modular converter (50D) carries out gray-scale statistical to the former frame image, with the gray-scale statistical result of former frame image a rear two field picture is processed.
5. the debugging apparatus for simulating thermal imager operation according to claim 1, it is characterized in that: FPGA controller (50) is to realize with an embedded processing plate fpga chip, and employing HDL hardware description language realization fpga chip is communicated by letter with each interface.
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