CM OS MEMORY CELL WITH TUNNELING
DURING PROGRAM AND ERASE THROUGH
THE NMOS AND PMOS TRANSISTORS AND
A PASS GATE SEPARATING THE NMOS
AND PMOS TRANSISTORS
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to CMOS memory cells having PMOS and NMOS transistors with a common floating gate configured so that program and erase occurs through the gate oxide of the NMOS and PMOS transistors. More particularly, the present invention relates to circuitry, and a method for utilizing the circuitry, to enable such a CMOS memory cell to be used in a programmable logic device (PLD) and to prevent current flow in unselected cells during erase which may disturb programming conditions in the unselected cells.
2. Description of the Related Art
FIG. 1 shows a circuit configuration of a CMOS memory cell having a PMOS transistor 102 and an NMOS transistor 104 enabling utilization of tunneling through the NMOS and PMOS transistors during program and erase. The PMOS transistor 102 and NMOS transistor 104 have a common floating gate. The drains of transistors 102 and 104 connect together to form an output of the CMOS cell. A capacitor 106 is connected to couple bias voltage from an array control gate (ACG) node to the common floating gate. Bias voltage is provided to the source of the NMOS transistor 104 through a chip ground or Vss pin. A PMOS pass gate transistor 108 supplies a word control (WC) voltage to the source of PMOS transistor 102 as controlled by a word line (WL) voltage supplied to its gate. Transistor 108 is a PMOS device to avoid having to increase the WC voltage above the threshold of an NMOS device during programming. The CMOS memory cell of FIG. 1 is described in detail, along with methods for its program and erase, in U.S. patent application Ser. No. 08/427,117 entitled "A CMOS Memory Cell With Gate Oxide Of Both NMOS and PMOS Transistors As Tunneling Window For Program and Erase," by Lin, et al., filed Apr. 21, 1986, and incorporated herein by reference (hereinafter, the Lin reference).
FIG. 2 shows a layout for the cell of FIG. 1. The layout for the CMOS cell is formed in a p type substrate. Capacitor 106 is formed using an n+ type implant region 110, including a programming junction region, formed in the p type substrate. Capacitor 106 also includes a gate oxide layer and a common floating gate (F.G.) 112 overlying the n+ implant region 110. Transistor 104 is formed using n+ implant regions 114 and 116 in the p type substrate with the gate oxide region and common floating gate 112 bridging the n+ implant regions 114 and 116. Transistor 102 is formed using p type regions 118 and 120 included in an n+ type well 122, which is included in the p type substrate. Transistor 102 also includes the gate oxide region and common floating gate 112 bridging the two p type regions 118 and 120. Transistor 108 is formed using a polysilicon (POLY) word line (WL) region 124 on the substrate bridging the p type implant region 120 of transistor 102 with an additional p type implant region 126.
To program the CMOS memory cell of FIG. 1, a voltage is applied between the array control gate (ACG) node of capacitor 106 and the source of the PMOS transistor 102 so that electrons transfer from the common floating gate to the source of the PMOS transistor 102. A high impedance is applied to the source of the NMOS transistor 104 during
programming to prevent depletion of its channel which would occur if an NMOS transistor 104 were biased to remove electrons from the common floating gate. To prevent programming of unselected cells in an array of
5 cells similar to FIG. 1 connected to receive the same WC program voltage, a voltage higher than the program voltage applied to the WC line is applied to WL lines of the unselected cells. By applying such a voltage in unselected cells, transistor 108 in those cells will be off to disconnect
io the WC voltage.
To erase the CMOS memory cell of FIG. 1, a voltage is applied between the array control gate (ACG) node of capacitor 106 and the source of the NMOS transistor 104 so that electrons transfer from the source of the NMOS tran
15 sistor 104 to the common floating gate. A high impedance is further applied to the source of the PMOS transistor 102 during erase to prevent depletion of its channel, which would occur if a PMOS transistor 102 were biased to add electrons to the floating gate.
Because in an array of CMOS cells, configured as shown in FIG. 1, erase is done in bulk, different voltages are not required for unselected cells as in programming.
Voltages applied to the CMOS memory cell of FIG. 1 25 during program, erase, read, and not program are indicated in Table I below.
The typical prograimning voltage Vpp is 12 V. The Vcc voltage indicates the chip power supply input pin voltage which is typically 5 V, or 3 V for low power devices. Because the CMOS cell of FIG. 1 does not include a
40 means to enable or disable a path through the NMOS transistor 104, apart from programming its floating gate, the circuitry of FIG. 1 is not practical for use as an array cell for a PLD. To illustrate, FIG. 3 shows the connections of two array cells 301 and 302 in a PLD. As shown, each array cell
45 301 and 302 receives an input signal COL1 and COL2 as an enable signal EN. Each of cells 301 and 302 further has one connection to a product term (PT) line and an additional connection to a product term ground (PTG) line. The PT line forms an input to a buffer 312 included in a sense amplifier
50 310. The PTG line provides a connection to Vss in the sense amplifier 310. The sense amplifier 310 also includes a current source 314 connected to the input of the buffer 312. Array cells 301 and 302 are programmed to provide a connection from the PT to the PTG line, the connection
55 being provided when the array cell receives an appropriate EN signal.
Although the circuit of FIG. 1 can be programmed to provide a path between its output and Vss, no separate enable (EN) is provided, making the cell of FIG. 1 inad
60 equate for use as one of array cells 301 or 302 in a PLD. Additionally, with the source of the NMOS transistor of a cell of FIG. 1 which is not selected for programming floating during programming of another array cell, current leakage can occur which can cause a disturb condition
65 wherein electrons are injected onto the common floating gate in the unselected cell. As shown in Table I, for programming a particular cell, a WL voltage of Vcc is applied,