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US006629312B1
(12) United States Patent ao) Patent No.: us 6,629,312 Bi
Gupta (45) Date of Patent: Sep. 30,2003
(54) PROGRAMMATIC SYNTHESIS OF A MACHINE DESCRIPTION FOR RETARGETING A COMPILER
(75) Inventor: Shail Aditya Gupta, Sunnyvale, CA (US)
(73) Assignee: Hewlett-Packard Development
Company, L.P., Houston, TX (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 09/378,601
(22) Filed: Aug. 20, 1999
(51) Int. C I. G06F 9/45
(52) U.S. CI 717/136; 717/147; 703/20
(58) Field of Search 717/140, 147,
717/148, 136; 703/20
(56) References Cited
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5,854,929 A * 12/1998 Van Praet et al 717/156
5,918,035 A * 6/1999 Van Praet 395/500
6,226,776 Bl 5/2001 Panchul et al 716/3
6,292,938 Bl * 9/2001 Sarkar et al 717/138
6,463,582 Bl * 10/2002 Lethin et al 717/158
OTHER PUBLICATIONS
Peter Grun et al., Expression: An ADL for System Level Design Expoloration, Sep. 1998 [retrieved on Apr. 25, 2002]. Retrieved from the Internet: <URL:http://citeseer.nj.nec.com/grun98expression.html>.*
Halambi et al., Expression: a language for architecture exploration through compiler/simula retargetability, Mar. 1999 [retrieved on Apr. 25, 2002]. Retrieved from the Internet: http ://ieeexplore ieee .org/ie14/6133/16399/
00761170.pdf?is Number=16399&prod=CNE*
Parcerisa et al., The Latency Hiding Effectiveness of Decoupled Access/Execute Processors, 1998, Universitat Poloitecnica de Catalunya, Barcelona, Spain.* Rainer Leupers, Peter Marwedel, "Retargetable Generation of Code Selectors from HDL Processor Models," IEEE, 1997, pp. 140-144.
George Hadjiyiannis, Silvina Hanono, Srinivas Devadas, "ISDL: An Instruction Set Description Language for Retargetability," ACM, 1997, pp. 299-302. Gyllenhaal et al., "HMDES Version 2.0 Specification," Hewlett Packard Laboratories Technical Report IMPACT-96-3, (Published before Aug. 20, 1999). Hadjiyiannis et al., "A Methodology for Accurate Performance Evaluation in Architecture Exploration." (Published before Aug. 20, 1999).
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(List continued on next page.)
Primary Examiner—Kakali Chaki Assistant Examiner—-Todd Ingberg
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An MDES extractor automatically extracts a machine description (MDES) for re-targeting a compiler from a structural representation of a datapath of an explicitly parallel instruction computing (EPIC) processor. The datapath is a machine readable data structure that specifies the functional unit instances and an interconnect of the functional unit instances to registers. The MDES extractor structurally traverses the interconnect, identifying resource conflicts among the operations in the processor's opcode repertoire. Latencies and internal resources of the opcodes associated with the functional unit instances are obtained from a macrocell library. The MDES extractor then identifies external resource conflicts by preparing reservation tables for the functional units.
18 Claims, 9 Drawing Sheets
OTHER PUBLICATIONS
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Aditya et al., "Elcor's Machine Description System: Version 3.0," HPL-98-128, Oct. 1998, pp. 1-75.
Rau et al., "Machine-Description Driven Compilers for EPIC Processors," HP Laboratories Technical Report, HPL-98^10, Sep. 1998, pp. 1-82.
Kathail et al., "HPL PlayDoh Architecture Specification: Version 1.0," HP Laboratories Technical Report, HPL-93-80, Feb. 1994, pp. 1-48.
* cited by examiner
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