An internal clock generator is provided in which a clock having the smaller difference between the cycle of the clock and the delay time of a combinational circuit is generated. The combinational circuit included in a circuit to which the clock is supplied includes five signal processing portions which...http://www.google.co.uk/patents/US5907256?utm_source=gb-gplus-sharePatent US5907256 - Internal clock generator for self-timed circuit with reduced difference between a cycle of a clock and delay time of a combinational circuit
