An apparatus and method, the apparatus including an NMOS pass gate separating NMOS and PMOS transistors of a CMOS memory cell configured for tunneling during program and erase through the NMOS and PMOS transistors. The additional NMOS pass gate enables the CMOS memory cell to be utilized as a memory...http://www.google.co.uk/patents/US5646901?utm_source=gb-gplus-sharePatent US5646901 - CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separating the NMOS and PMOS transistors
