A system and method for reducing transfer latencies in fencepost buffering requires that a cache is provided between a host and a network controller having shared memory. The cache is divided into a dual cache having a top cache and a bottom cache. A first and second descriptor address location are fetched...http://www.google.co.uk/patents/US6941391?utm_source=gb-gplus-sharePatent US6941391 - Fencepost descriptor caching mechanism and method therefor
