WO2017089856A1

WO2017089856A1 - Frequency meter

Info

Publication number: WO2017089856A1
Application number: PCT/IB2015/002513
Authority: WO
Inventors: Wilmar Hernandez Perdomo; Carlos Alberto CALDERON CORDOVA; Carlos Israel CAMPOVERDE ROJAS; John Paul LANCHI OCHOA
Original assignee: Universidad Tecnica Particular De Loja
Priority date: 2015-11-25
Filing date: 2015-11-25
Publication date: 2017-06-01

Abstract

In one embodiment, a device for estimating frequency of the periodic signal includes a processor that receives a periodic signal and a periodic estimator module that is executable by the processor to estimate a length of a predefined number of cycles of the periodic signal with respect to a comparator signal to generate a length estimate for each of the predefined number of cycles, and store the length estimates. The periodic estimator module is further executable by the processor to sample the stored length estimates with replacement to generate resampled estimated vectors, and to calculate resample means for each of the resampled estimated length vectors, wherein each resample mean is the average of the length estimates in a respective resampled estimated length vector. The periodic estimator module is then executable by the processor to calculate a final periodic estimate of the periodic signal based on the resample means.

Description

FREQUENCY METER

FIELD

The present disclosure relates to the electronic technology field. More particularly, the present disclosure relates to circuit design and frequency meter devices.

BACKGROUND

Various electronic circuits and frequency estimation algorithms have been developed to calculate the frequency of an unknown input signal. Some such existing electronic circuits and algorithms for frequency detection include counters for counting pulses of a variable input signal using another input signal of a different fixed frequency as a reference. For example, such frequency counters are commonly used to estimate the frequency of signals, and in some cases the noise characteristics of RF (radio frequency) sources. A conventional frequency counter consists of a signal gate followed by a counter. In one type of conventional frequency counter, the signal gate opens for a known period of time, which is usually a predetermined number of cycles of a stable reference frequency. The counter then counts the number of input cycles that occur during this gate time. The frequency of the variable input signal can then be determined as the count number divided by the length of time that the gate was opened. In an alternative embodiment of a frequency counter, the signal gate is caused to open for one cycle of the variable input signal, such as being triggered by each consecutive positive edge or negative edge of the input cycle. The counter counts the number of pulses of the known reference frequency during the period that the gate is open, which is presumably one cycle period of the variable input signal.

SUMMARY

This Summary is provided to introduce a selection of concepts that are further described below in the Detailed Description. This Summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in limiting the scope of the claimed subject matter.

In one embodiment, a non-transitory computer readable medium having computer executable instructions stored thereon for estimating frequency of a periodic signal is provided, wherein the instructions include the steps of detecting a first ascending or descending edge of a rectangular periodic signal and a second ascending or descending edge of the rectangular periodic signal, counting a number of ascending or descending pulse edges of a comparator signal to generate a length estimate of a cycle or the rectangular periodic signal, and storing the length estimate. The detecting counting and storing steps are then repeated until a predefined number of length estimates are stored. A predefined number of resampled estimated length vectors are then generated by sampling the stored length estimates with replacement. A resample mean is calculated for each of the resampled estimated length vectors, wherein the resample mean is the average of the length estimates in the respective resampled estimated length vectors. A final periodic estimate of the periodic signal is then calculated based on the resample means, and the final periodic estimate is outputted.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 provides a block diagram of one embodiment of a device for estimating frequency of a periodic signal.

Figure 2A illustrates an exemplary periodic input signal.

Figure 2B illustrates an exemplary rectangular periodic signal generated based on the periodic input signal of Figure 2A. Figure 2C illustrates an exemplary comparator signal having a frequency that is higher than the frequency of the rectangular input signal.

Figure 3 provides a flowchart depicting one embodiment of a method and instruction steps for estimating a frequency of a periodic signal. Figures 4A-4F provide flowcharts illustrating various embodiments of methods and instruction steps for estimating a frequency of a periodic signal.

Figure 5 is a block diagram illustrating another embodiment of a device for estimating frequency of a periodic signal

DETAILED DESCRIPTION Through their experimentation and research in the relevant field, the inventors have recognized that presently available electronic circuit devices, systems and methods for frequency estimation, including the existing frequency counter circuits described herein, present problems and challenges, such as susceptibility to noise, requiring significant filtering processes, requiring optimization for specific signal power strength and/or frequency ranges, requiring expensive specialized process configurations, and/or requiring too much processing power and/or computing time. For instance, methods, systems and devices implementing Newton-type algorithms for frequency estimation require significant computational input, and thus necessitate significant processing power. Other methods, systems, and devices implement frequency estimation algorithms based on based on the Fourier Fast Transform (FFT), Discrete Fourier Transform (DFT), or Discrete Cosine Transform (DCT) for frequency estimation, which are susceptible to influence by noise and harmonics and thus require significant filtering of the input signal in order to provide a robust and effective frequency estimator. Other implementations that use a least squares (LS) estimation algorithm to estimate signal frequency fail because matrix inversion provides inaccurate results if the matrix is not singular. To provide further exemplary issues with prior art recognized by the present inventors, frequency estimation algorithms that use a Kalman Filter (KF) are susceptible to instability and failure because they require an accurate system model and tuning of filter parameters. Therefore, if the model presents uncertainties or modeling errors, the estimation made by the KF is not robust, and results will deviate from the correct value, and may even be diverted to infinity. Implementations that use a Zero Crossing Detector (ZCD) are highly susceptible to noise, since noise may introduce multiple zero crossings that do not exist in the input signal being measured, and thus ZCDs are inaccurate in many practical applications where noise is present in the input signal. Frequency estimation techniques based on phase lock loops (PLL) and adaptive stop-band filters (ANF), need pre- and post- filtering processes, which are cumbersome and require significant processing power. Frequency estimation techniques based on the minimization of expected value of error mean square (LMS) depend on parameter pass size (μ), which is dependent on the input signal energy. However, when the input signal energy is not known, as happens frequently in practical applications, the LMS loses strength and said filter must be strengthened by other means, such as by amplifiers. Frequency estimation systems and methods implementing artificial intelligence techniques, such as neural networks and genetic algorithms, among others, require training and optimization processes that consume significant computational power, input, and time.

The electronic circuit device, method, and software disclosed herein was developed by the inventors after their recognition of and to overcome the above-mentioned problems and challenges. The periodic value— i.e., the period and/or frequency— of an unknown periodic input signal is estimated by comparing multiple periods of the periodic input signal with a fixed comparator signal of a known frequency, and conducting statistical analysis on the multiple period estimates made according to the statistical principal of bootstrapping to calculate a final periodic estimate. Specifically, a counter, such as a known electronic frequency counter, estimates the length of multiple periods of the periodic input signal in terms of a period of a known periodic comparator signal, and stores the length estimates of each period in a length estimate vector. The length estimates in the vector are then sampled with replacement to create many more vectors of length estimates which, in accordance with known bootstrapping principals, are relied upon to provide an estimation of the original sampling distribution and to estimate the period and/or frequency of the periodic input signal. Specifically, a resample mean is generated for each vector of resampled length estimates by averaging the length estimate samples therein. A new vector is then created containing the resample means. A final period estimate is calculated therefrom based on an average of the resample means.

Accordingly, the inventors have developed and disclosed herein, a simple and economic computational device, system, method, and software for estimating frequency of a periodic signal, which is not recursive or adaptive and, thus, there are no convergence problems. The frequency estimator works satisfactorily in environments where the signal-to-noise ratio is low. For example, the disclosed frequency estimator is not greatly affected by noise-induced zero crossings of a periodic input signal contaminated by noise. Accordingly, in most environments and applications, there is no need for pre- or post- filtering stages or investing in a matrix, and thus there are no bad conditioning problems. Furthermore, the device utilizes simple electronic circuitry, can be implemented on general purpose microprocessors, is easy to manufacture, and is easily integrated into current technology of frequency meter devices.

The frequency estimator device and method described and disclosed herein can be used in a wide range of industrial applications. For example, frequency is an essential parameter in the analysis, operation and control of power systems. Frequency estimation is important to evaluate the quality of power in these systems. Additionally, the frequency estimator device and methods disclosed herein may be useful in any application involving sinusoidal signals, including electronics, communications, medicine, and mechanics, among others. For example, this device can be used as laboratory instrument to measure the frequency of a function generator and/or circuit oscillator. To provide further examples, it can also be used to measure frequency both in signal transmitters and receivers, to indirectly measure the speed of vehicle wheels and/or engine revolutions, to measure the frequency of the electrical grid, etc.

Figure 1 depicts one embodiment of a frequency estimator, or detector, device 10 that receives a periodic input signal 30 and provides a final periodic estimate 40 of the period and/or frequency of the periodic input signal 30. In the embodiment of Figure 1, the device 10 includes signal conditioning circuitry including voltage comparator circuit 12a to condition the periodic input signal 30 for receipt and processing by the processor 14. The processor 14 executes a periodic estimator module 8 (see Figs. 3, 4A-4F, and 5), which estimates the length of multiple cycles of the periodic input signal with respect to a comparator signal, and then calculates a final periodic estimate of the periodic signal using bootstrapping. More specifically, and with reference also to Figure 5, the voltage comparator circuit 12a transforms the periodic input signal 30 to a rectangular periodic signal 30a having a frequency equal to the frequency, or cycle length, of the periodic input signal 30. The cycle, or signal period, of the rectangular periodic signal 30a can be defined, for example, as the distance between two consecutive ascending edges or two consecutive descending edges of the rectangular wave. The rectangular periodic input signal 30a may or may not have approximately the same peak-to-peak amplitude of the periodic input signal 30, depending on the conditioning circuitry 12 utilized.

The voltage comparator circuit 12a may be, for example, a Schmitt trigger, which is a comparator circuit with hysteresis implemented by applying positive feedback to the

noninverting input of a comparator or differential amplifier. Likewise, other active circuits that convert the analog periodic input signal 30 to a digital output signal, such as rectangular periodic signal 30a, may be used with equal effectiveness, which will be evident to a person having ordinary skill in the art upon reviewing the present disclosure. In one configuration of a Schmitt trigger comparator circuit, when the periodic input signal 30 is higher than a chosen threshold, the output of the circuit is high. When the input is below a different, lower chosen threshold, the output is low. When the input is between the two threshold levels, the output retains its value, thus providing hysteresis. Accordingly, a Schmitt trigger voltage comparator circuit 12a reduces the influence of noise in the periodic input signal 30 by removing much of the noise from the rectangular periodic signal 30a provided at the output. In other embodiments, additional conditioning circuitry 12, which may or may not include the voltage comparator circuit 12a, may be utilized. (See Figure 5.) Exemplary additional conditioning circuitry 12 could include an amplifier, one or more filters, and/or other shaping circuitry at the input. As an additional example, the conditioning circuitry 12 may include a voltage level shifter to condition the input periodic signal 30 to be received by the voltage comparator circuit 12a and/or the processor 14. For example, the voltage level shifter may shift the voltage range of the periodic input signal 30 to a range varying from 0 to 5 volts, 0 to 1 volt, -10 to 10 volts, or any other voltage range required for optimal operation of an aspect of the frequency estimator device 10.

The conditioned signal 30a is provided to the processor 14, which then invokes and executes the periodic estimator module 8 in order to generate a final periodic estimate 40. The processor may be, for example, a microprocessor, microcontroller, or peripheral interface controller (PIC), as is discussed in further detail hereinbelow. The processor 14 may further receive or rely on a comparator signal 20. The comparator signal 20 is a uniform periodic signal of a known frequency, such as a square wave with a 50% duty cycle. However, in other embodiments the comparator signal 20 may be any other shaped waveform, such as a rectangular wave with a different duty cycle, a sawtooth wave, or a triangle wave.

Figures 2A-2C provide exemplary signals that can be used to illustrate the function of the frequency estimator device 10, and to describe the experimental procedure and results illustrating the operation of the device 10. The exemplary periodic input signal 30 provided in Figure 2A has a frequency of 10 kHz and a peak-to-peak amplitude of 5 volts. Figure 2B depicts an exemplary rectangular periodic signal 30a generated based on the periodic input signal 30 of Figure 2A, such as by processing the periodic input signal 30 with a voltage comparator circuit 12a. The rectangular periodic signal 30a has a frequency of 10 kHz and a peak-to-peak amplitude of 5 volts. Figure 2C demonstrates an exemplary comparator signal 20, which is a square wave with 50% duty cycle having a frequency of 100 kHz. While a 100 kHz comparator signal may be too low for many applications of the disclosed frequency estimator device 10, 100 kHz is used here to exemplify the operation of the method, device, and instructions executed by the periodic estimator module 8 in order to estimate the length of a cycle of the periodic input signal 30, and in this case the rectangular periodic signal 30a. In a preferred embodiment, the frequency of the comparator signal 20 complies with the Nyquist Theorem, and in certain embodiments in applications over sampling will be preferable. For example, in applications where estimation accuracy is critical, it may be advisable that the sampling frequency is twenty times or more greater than the maximum frequency to be measured. As described above, the periodic estimator module 8 may be configured to detect a cycle period based on consecutive ascending edges 34 of the rectangular periodic signal 30a, or consecutive descending edges 35. In the embodiment depicted in Figures 2B and 2C, the periodic estimator module 8 is configured to detect ascending edges 34 of the rectangular periodic signal 30a, and upon such detection to employ a counter to begin counting pulses of the comparator signal frequency of 100 kHz. In the depicted embodiment, the counter is configured as an ascending pulse edge counter to count the ascending edges of each cycle of the comparator signal 20 falling between the ascending pulse edges 34 of the rectangular periodic signal 30a. Upon detection of the next ascending pulse edge, the counter outputs the number of ascending pulse edges 21 of the comparator signal 20 as the length estimate 24, and meanwhile the counter restarts its ascending pulse edge 21 count or the next cycle of the rectangular periodic signal 30a. Accordingly, the length estimate 24 of each cycle of the periodic input signal 30 is estimated based on an assumption that each ascending edge 21 represents an entire period of the comparator signal 20, such as a clock cycle, that falls within the cycle period of the periodic input signal 30. Of course, this assumption will not always be correct, and thus this method of length estimation by pulse counting introduces a small amount of error into the periodic estimate, and that error grows relatively larger with a lower frequency comparator signal 20. Thus, the length estimate 24 of any given cycle of the periodic input signal 30, when multiplied by the period of the comparator signal 20, may be slightly larger or slightly smaller than the actual period of the periodic input signal 30. The device, system, method, and software disclosed herein provides that multiple length estimates 24 are made over multiple cycles of the periodic input signal 30. The multiple length estimate data is then analyzed using bootstrapping statistical analysis to assess the accuracy and generate sample estimates, as is described further herein.

Figure 3 provides one exemplary method 50 and instruction set executed by the device 10. At step 52, a periodic input signal 30 is received at the device 10. The periodic input signal 30 is conditioned at step 53, such as by the voltage comparator circuit 12a generating a rectangular periodic signal 30a. The periodic estimator module 8 is then invoked at step 55, such as by the processor 14. The periodic estimator module 8 is then executed, such as on the processor 14, to execute a series of steps and instructions resulting in the output of a final periodic estimate 40. In the embodiment depicted in Figure 3, n number of length estimates of cycles of the periodic input signal 30 are generated at step 60. At step 67, outliers are removed from the n number of length estimates. At step 73, the remaining length estimates are sampled with replacement to generate m number of resampled length estimate vectors. The resample mean of each resampled length estimate vector is calculated at step 74. Then, at step 80, the final periodic estimate 40 is calculated based on the resample means calculated at step 74. Figures 4A through 4F further describe various embodiments and aspects of the disclosed method 50 of estimating frequency, and corresponding exemplary instructions carried out when executing the periodic estimator module 8. At step 51, a counter for the value n is reset to 0 (n=0) at the start of a new frequency estimation cycle. A period input signal 30 is received at step 52. The periodic input signal may be any type of real, periodic signal complying with the Dirichlet conditions. Namely, the periodic input signal 30 must be absolutely integrable over a period, and the input signal must be finite and bounded. At step 53, the periodic input signal 30 is conditioned, including processing the input signal 30 with a voltage comparator circuit 12a to generate a rectangular periodic signal 30a. The rectangular periodic signal is then received at the processor 14 in step 54. At step 55, the processor invokes the periodic estimator module 8. At step 56, an ascending edge 34 of the rectangular periodic signal 30a is detected at step 56. As described above, other embodiments may rely on detection of a descending edge. In still other embodiments, other threshold detection methods may be used to detect the initiation and/or completion of a cycle of the periodic input signal 30.

The rectangular periodic signal 30a is then compared to a comparator signal 20 at step 57, such as by sampling the rectangular periodic input signal 30a at a clock frequency, and then using a counter to tally the number of samples until the next ascending edge of the rectangular periodic signal 30a is detected. In an exemplary embodiment, the comparator signal 20 may be the clock signal associated with the processor 14, which typically has pulses in the MHz or GHz range. However, in other embodiments a separate comparator frequency 20 other than the clock signal may be used. At step 59, the length estimate 24 is stored as a value X in the length estimate vector, which can be defined as X = (X_1; X₂,..., X_n). At step 60, it is determined whether the predefined number of length estimates have been generated of cycles of the periodic input signal 30. Specifically, at step 60 in the embodiment of Figure 4A, n is increased by 1 (n=n+l), and the periodic estimator module 8 determines whether the new value of n is equivalent to the predefined number of length estimates 24 that the periodic estimator module 8 has been configured to require. In various embodiments, the predefined number for the number n of length estimates 24 may be at least 30, and in certain embodiments superior accuracy may be obtained working with a higher predefined number for n, such as 100 length estimates of 100 cycles of the periodic input signal 30, or more. In various embodiments, the periodic estimator module 8 may continue after step 60 to execute various steps to remove outliers from the length estimate vector, as is exemplified in Figure 4B. In other embodiments, the periodic estimator module 8 may continue to the method steps illustrated in Figure 4C, which include resampling and calculating resample mean values. In an embodiment of the method 50 including the removal of outliers, the periodic estimator module 8 may execute instructions that include the steps depicted in Figure 4B. At step 62, a lower quartile value Ql is determined, which a person having ordinary skill in the art will understand is the median of the lower half of the length values 24 in the length estimate vector. At step 63, the upper quartile value Q3 of the data in the length estimate vector is determined, which will be understood by a person having ordinary skill in the art as the median value of the upper half of the length estimate values 24 in the length estimate vector generated at step 59. At step 64, the interquartile range (IQR) is calculated as the upper quartile value minus the lower quartile value (IQR = Q₃ - Qi). A lower barrier for the outlier removal is then calculated at step 65 based on the interquartile range IQR. For example, the lower barrier may be calculated as a multiple of the IQR value. To provide one exemplary embodiment, the lower barrier may be calculated as LB = Qi - (1.5 IQR). Similarly, at step 66, an upper barrier may be calculated based on the interquartile range, which in the provided example is calculated as UB = Q₃ + (1.5 IQR). Then, at step 67, outliers are removed by removing length values 24 in the estimated length vector that are either below the lower barrier LB or above the upper barrier UB. Then, in the embodiment of Figure 4B, n is reassigned as the number of remaining length estimates 24 left in the length estimate vector after the outliers have been removed.

The remaining steps exemplified in Figures 4C through 4F rely on the statistical principle and technique of bootstrapping, which rely on random sampling methods and statistical analyses as described herein. Figure 4C depicts further steps of the method 50 executed in an exemplary embodiment of the periodic estimator module 8. At step 70, the counter variable m is assigned a zero value (m=0). As described above, X = (X_1; X₂,..., X_n) denotes the length estimate vector, which may or may not have undergone the outlier removal steps depicted in 4B depending on the embodiment of the periodic estimator module 8. It is assumed that the length estimate vector X = (Xi, X₂,..., X_n) represents a sample of size n observed from the periodic input signal 30, which has an unspecified probability distribution. At step 71, the estimated length values 24 in the length estimate vector X = (X_1; X₂,..., X_n) are sampled with replacement to create a resampled estimated length vector X*, which may have a different predefined length in various

embodiments of the periodic estimator module 8. In the embodiment of Figure 4C, the length estimate vector X = (Xi, X₂,..., X_n) is sampled n number of times, and thus the resampled estimated length vector X* generated at step 72 has length n and is the same length as the length estimate vector X. Thus, X* = (Xi*, X₂*,..., X_n*)- Steps 71 and 72 are repeated to generate a predefined number m of resampled estimated length vectors X*. Accordingly, at step 73, the counter variable m is increased until it reaches the predefined value. In various embodiments, the predefined number for the m counter value may be 10, 100, 1,000, 10,000, or more resampled estimated length vectors. Once m reaches the predefined number of resampled estimated length vectors generated, the values in each of the m number of resampled estimated length vector are averaged to create a resample mean value X for each resampled estimated length vector X*. The resample mean calculation may be represented as: m

X = ∑ X* /m

i = 1

Accordingly, at step 74, m number of resample means X are generated. The resample means are stored in a resample mean vector having length m at step 75, such that the resample mean vector is represented by X = (X\, X₂,. . . , X_m)- In certain embodiments, the periodic estimator module 8 may then execute steps to test the variability in the data in the resample mean vector X = (X\, X₂,. . . , X_m), such ^as the exemplary steps depicted in Figure 4D. In other embodiments, accuracy may be assumed and the periodic estimator module 8 may continue on to generate the final periodic estimate 40 based on the resample means X without the steps exemplified in part D. In Figure 4D, the standard deviation of the sample means in the vector X = (X\, X₂,. . . , X_m) is calculated at step 77. At step 78, it is determined whether the standard deviation exceeds a maximum value. In various embodiments, the maximum value may be established at various levels in order to require a desired amount of accuracy. To provide one example, where a high degree of accuracy is required, the maximum value for the standard deviation may be set to 0.5% of the mean value of the resample means vector X = (X\, X₂,. . . , X_m)- In other embodiments, such as embodiments where a very high degree of noise or other signal variability is expected and/or fast processing time is more highly valued than accuracy, the maximum standard deviation may be set higher. If the maximum standard deviation is exceeded at step 78, then the estimation process may be restarted at point A (see Figure 4A). If the standard deviation is less than or equal to the maximum standard deviation, then the periodic estimator module 8 continues on to calculate a final periodic estimate 40 based on the values in the resample mean vector X = (X\, X₂,. . . , X_m). Figures 4E and 4F depict various embodiments of calculating the final periodic estimate 40, which is represented in Figure 3 as step 80. In Figure 4E, the average of the resample means X is calculated at step 82. At step 84, the average value is then multiplied by the period of the comparator signal 20. Accordingly, this method is applicable in embodiments where the estimated length values 24, and the resample means X, represent the original pulse count values, such as those generated at the execution of steps 56 through 59, which have not yet been multiplied by the period of the comparator signal 20. Accordingly, in some embodiments, the calculation carried out at step 84 may be executed at other points in the method 50. At step 85, a frequency estimate is determined as the final periodic estimate 40 by inverting the period value generated at step 84. At step 86, the periodic estimator module 8 outputs the frequency estimate.

Figure 4F depicts another embodiment of the method 50 where the final periodic estimate 40 is calculated as an estimate of the period of the periodic input signal 30. At step 83, each resample mean value X in the resample mean vector is multiplied by the period of the comparator signal 20. Accordingly, at step 83, a resample period is calculated for each value in the resample mean vector X = (X\, ¾,· · · Xm)- At step 86, the resample period values are averaged to generate the final periodic estimate 40 in the form of an estimate of the period length, or time length, of each cycle of the periodic input signal 30. At step 87, the periodic estimator module 8 outputs the period estimate as the final periodic estimate 40.

In order to achieve maximum estimation accuracy, in some embodiments the frequency estimation method 50 and instructions may be executed multiple times on multiple sets of cycles of the periodic input signal 30, with each frequency estimate calculated therefrom stored in a vector of the frequency estimates. The average, or mean value, of this vector may then calculated, and that average may then used as the final periodic estimate 40 output.

Figure 5 provides another block diagram of an exemplary embodiment of the device 10 for estimating the frequency of the periodic signal implementing a periodic estimator module 8 as described herein. The device 10 includes a computing system 200 and conditioning circuitry 12. The computing system 200 includes a processor 14, storage system 204, software 202, and communication interface 208. The processor 14 loads and executes software 202 from the storage system 204, including the periodic estimator module 8, which is one or more applications within the software 202. The periodic estimator module 8 includes computer-readable instructions that, when executed by the computing device 10 (including the processor 14), direct the processor 14 to operate as described in herein in further detail, including to execute the steps to calculate the final periodic estimate 40. The communication interface 208 communicates with devices external to the computer system 200, such as the conditioning circuit 12, a clock circuit or other device providing the comparator signal 20, and/or devices configured to receive the final periodic estimate 40, such as a user interface device that could output the value to a user.

Although the computing device 10 depicted in Figure 5 includes one software 202 encapsulating one periodic estimator module 8, it should be understood that one or more software elements having one or more instruction modules may provide the same operation.

Similarly, while description as provided herein refers to a computing system 200 and a processor 14, it is to be recognized that implementations of such systems can be performed using one or more processors, which may be communicatively connected, and such implementations are considered to be within the scope of the description. The processor 14 may comprise a microprocessor, a microcontroller, or a PIC, and other circuitry that retrieves and executes software 202 from storage system 204. Other examples of processor 14 include general purpose central processing units, applications specific processors, and logic devices, as well as any other type of processing device, combinations of processing devices, or variations thereof. Processor 14 can be implemented within a single processing device but can also be distributed across multiple processing devices or sub-systems that cooperate in executing program instructions.

The storage system 204 can comprise any storage media, or group of storage media, readable by processor 14, and capable of storing software 202. The storage system 204 can include volatile and non- volatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer-readable instructions, data structures, program modules, or other data. Storage system 204 can be implemented as a single storage device but may also be implemented across multiple storage devices or sub-systems. For example, the periodic estimator module 8 can be stored, distributed, and/or implemented across one or more storage media or group of storage medias. Examples of storage media include random access memory, read only memory, magnetic discs, optical discs, flash memory, virtual memory, and non-virtual memory, magnetic sets, magnetic tape, magnetic disc storage or other magnetic storage devices, or any other medium which can be used to storage the desired information and that may be accessed by an instruction execution system, as well as any combination or variation thereof, or any other type of storage medium. Likewise, the storage media may be housed locally with the processor 14, or may be distributed in one or more servers, which may be at multiple locations and networked, such as in cloud computing applications and systems. In some implementations, the store media can be a non-transitory storage media. In some implementations, at least a portion of the storage media may be transitory.

The inventors developed a prototype in accordance with one embodiment of the description herein to exemplify and illustrate the performance of the device, system, method, and software. The 10kHz periodic input signal depicted in Figure 2A was generated using a signal generator, specifically a Tektronix AFG2021 Arbitrary Function Generator. In order to test and exemplify the behavior of the device 10 in the presence of noise, the periodic input signal 30 was contaminated with Gaussian noise at a signal-to-noise ratio of approximately 3.6dB. Input signals of a range of frequency values were generated, each having that signal-to-noise ratio of approximately 3.6dB, such that the list of frequencies generated for the test included: 1 kHz, 10kHz, 20 kHz, 30 kHz, 40 kHz, 50 kHz, 60 kHz, 70 kHz, 80 kHz, 90 kHz, and 100 kHz. The periodic input signals 30, including that illustrated in Figure 2A, were provided to a

LM339 voltage comparator circuit device by Texas Instruments Inc., of Dallas, Texas. The LM339 voltage comparator circuit 12a was set up as a Schmitt trigger, supplied by 0 to 5 volts, with a lower threshold voltage of 2 volts and a higher threshold voltage of 3 volts. The rectangular periodic signal 30a was output from the voltage comparator circuit 12a in response to the periodic input signal 30 of Figure 2A, and thus the rectangular periodic signal 30a has a frequency of 10 kHz and a peak-to-peak amplitude of 5 volts. Similar rectangular periodic waves 30a were generated in each test for each of the other input frequencies. The rectangular periodic signal 30a was then supplied to a National Instruments NIsbRIO-9636 embedded control device by National Instruments Corporation of Austin, Texas, which is an exemplary computing system 200 having a processor 14. The NIsbRIO-9636 includes a 400 MHz processor, 512 megabytes of nonvolatile storage, and 256 megabytes of DRAM. The clock frequency was used as the comparator signal 20, and thus the rectangular periodic signal 30a was sampled at 40 MHz.

The NIsbRIO-9636 device was configured to execute an exemplary embodiment of the periodic estimator module 8, which was configured to detect a cycle of the rectangular periodic signal 30a based on detection of consecutive positive, or ascending, edges of the rectangular wave. Specifically, an embodiment of the periodic estimator module 8 was programmed using Lab VIEW (also from National Instruments) on the NIsbRIO-9636 platform to execute instructions and carry out the following steps. A counter was used to count the number of clock pulses that occurred between each set of consecutive ascending edges. The clock frequency was the sampling frequency. In the test configuration, the duty cycle of the clock signal was equal to 50%, and the counter was rising edge triggered. Accordingly, the length of each cycle was estimated as the number of clock pulses in one cycle of the periodic input signal 30, which was recorded as a length estimate.

For each of 100 number of cycles (predefined number for n was 100) of the rectangular periodic signal 30a, and thus also of the periodic input signal 30, the length estimates were stored in a vector, creating a vector of 100 of length estimates. Next, outliers in the length estimate vector were removed according to methods described above. Each remaining length estimate in the length estimate vector, which then had a size less than or equal to 100, was multiplied by the period of the clock comparator signal 20, which was 25 nanoseconds, in order to create a length estimate vector containing estimates of the period of the periodic input signal 30. In this particular embodiment, the inverse of each element in the length estimate vector was then determined such that the length estimate values in the length estimate vector were then frequency values. However, in other embodiments, the length estimate values may remain.

Next, 1,000 resampled length estimate vectors were created by sampling with

replacement from the length estimate vector. Each resampled length estimate vector contained n number of samples, where n was less than or equal to 100 and was the length of the length estimate vector once the outliers were removed. Then, for each of the 1000 resampled length estimate vectors, a resample mean was calculating as the average of the values in the respective resampled length estimate vector. Accordingly, 1,000 resample mean values were calculated, and were stored in a resample mean vector. Next, the standard deviation of the 1,000 sample means was calculated. If the standard deviation was greater than a maximum standard deviation value of 0.5%, then the data was scrapped and the entire frequency estimation process was repeated based on new cycles of the periodic input signal 30. If the standard deviation was less than the 0.5% maximum, then the final periodic estimate 40 was calculated based on the resample means. As described above, in this embodiment the length estimate values stored in the length estimate vector and the 1000 resampled length estimate vectors was a frequency value. Accordingly, a final periodic estimate 40 of the periodic input signal 30 was calculated as the average value of the 1,000 resample means.

In order to achieve maximum estimation accuracy, the frequency estimation method 50 and instructions were executed 100 more times, with each frequency estimate stored in a vector. The average of this vector was then calculated, and that average, or mean value, was then used as the final periodic estimate 40 output. The table below represents the frequency estimates obtained in this manner from the aforementioned input frequencies, which were corrupted by Gaussian noise at a signal-to-noise ratio of 3.6dB. The estimations were calculated with 6 ½ digits of resolution.

The above described embodiment of the device 10 was also tested using a square wave periodic input signal 30 having a 50% duty cycle and a peak-to-peak voltage ranging between 0 and 5 volts. The square wave periodic input signal was generated with the Tektronix AFG2021 function generator described above. The embodiment of the periodic estimator module 8 described above was also programmed using Lab VIEW on the NIsbRIO-9636 platform. In embodiments such as this where the periodic input signal 30 is already in digital form, the voltage comparator circuit 12a could potentially be eliminated. The square wave periodic input signals, which were not contaminated with noise, were generated at the following frequencies: 1 Hz, 5 Hz, 10 Hz, 50 Hz, 100 Hz, 500 Hz, 1 kHz, 5 kHz, 10 kHz, 50 kHz, 100 kHz, 500 kHz, and 1 MHz. The exemplary periodic estimator module 8 outputs a final periodic estimate 40 in the form of a frequency estimate represented with 6 ½ digits of resolution for each of these test frequencies, and the results are shown in the chart below:

This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to make and use the invention. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.

Claims

CLAIMS We claim:

1. A device for estimating frequency of a periodic signal comprising:

a processor that receives a periodic signal; and

a periodic estimator module executable by the processor to:

estimate a length of a predefined number of cycles of the periodic signal with respect to a comparator signal to generate a length estimate for each of the predefined number of cycles;

store the length estimates;

sample the stored length estimates with replacement to generate resampled estimated length vectors;

calculate resample means for each of the resampled estimated length vectors, wherein each resample mean is the average of the length estimates in a respective resampled estimated length vector; and

calculate a final periodic estimate of the periodic signal based on the resample means.

2. The device of claim 1, wherein the periodic estimator module is executable by the processor to multiply each resample mean by a period of the comparator signal to get a resample period for each resample mean, and to calculate the final periodic estimate by averaging of the resample periods.

3. The device of claim 1, wherein the periodic estimator module is executable by the processor to calculate an average of the resample means, and multiply the average of the resample means by a period of the comparator signal.

4. The device of any of claims 1-3, wherein the periodic estimator module is executable by the processor to further calculate the final periodic estimate as a frequency estimate.

5. The device of any of claims 1-4, wherein the periodic estimator module is further executable by the processor to output the final periodic estimate.

6. The device of any of claims 1-5, further comprising a voltage comparator circuit that generates a rectangular periodic signal having a frequency equal to a frequency of a periodic input signal, and providing the rectangular periodic signal as input to the periodic estimator module.

7. The device of claim 6, wherein the voltage comparator circuit is a Schmitt trigger.

8. The device of claim 6, wherein the periodic estimator module is further executable by the processor to detect a first ascending edge of the rectangular periodic signal and a second ascending edge of the rectangular periodic signal, and wherein the comparator signal is a square wave of a predefined frequency and periodic estimator module estimates the length of the cycle of the rectangular periodic signal by counting a number of ascending or descending pulse edges of the comparator signal between the first ascending edge and the second ascending edge.

9. The device of claim 6, wherein the periodic estimator module is further executable by the processor to detect a first descending edge of the rectangular periodic signal and a second descending edge of the rectangular periodic signal, and wherein the comparator signal is a square wave of a predefined frequency and periodic estimator module estimates the length of the cycle of the rectangular periodic signal by counting a number of ascending or descending pulse edges of the comparator signal between the first descending edge and the second descending edge.

10. The device of any of claims 1-9, wherein the periodic estimator module is executable by the processor to generate length estimates for at least 10 cycles of the periodic signal.

11. The device of claim 10, wherein the periodic estimator module is executable by the processor to generate length estimates for at least 100 cycles of the periodic signal.

12. The device of any of claims 1-11, wherein the periodic estimator module is executable by the processor to generate at least 100 resampled estimated length vectors.

13. The device of claim 12, wherein the periodic estimator module is executable by the processor to generate at least 10,000 resampled estimated length vectors.

14. The device of any of claims 10-13, wherein each resampled estimated length vector has a vector length equal to the number of length estimates.

15. The device of any of claims 1-14, wherein the periodic estimator module is further executable by the processor to remove outliers from the stored length estimates.

16. The device of claim 15, wherein the periodic estimator module is further executable by the processor to remove the outliers from the stored length estimates prior to generating the resampled estimated length vectors.

17. The device of any of claims 1-16, wherein the periodic estimator module is further executable by the processor to calculate a standard deviation of the resample means.

18. The device of claim 17, wherein the periodic estimator module is further executable by the processor to determine whether the standard deviation is greater than a maximum standard deviation, and to restart the estimation if the standard deviation is greater than the maximum.

19. The device of claim 18, wherein the maximum standard deviation is a standard deviation of the stored length estimates after the outliers are removed.

20. The device of any of claims 1-19, wherein the periodic estimator module is further executable by the processor to estimate the length of multiple sets of cycles of the periodic signal and to generate multiple sets of length estimates, calculate the final periodic estimate for each set of length estimates, and to calculate a frequency estimate based on an average of the final periodic estimates of the multiple sets.

21. A non-transitory computer readable medium having computer executable instructions stored thereon for estimating frequency of a periodic signal, wherein the instructions include the steps comprising:

detecting a first ascending or descending edge of a rectangular periodic signal and a second ascending or descending edge of the rectangular periodic signal;

counting a number of ascending or descending edges of a comparator signal to generate a length estimate of a cycle of the rectangular periodic signal;

storing the length estimate;

repeating the detecting, counting, and storing steps to until a predefined number of length estimates are stored;

generating a predefined number of resampled estimated length vectors by sampling the stored the length estimates with replacement;

calculating a resample mean for each of the resampled estimated length vectors, wherein the resample mean is the average of the length estimates in the respective resampled estimated length vector;

calculating a final periodic estimate of the periodic signal based on the resample means; and

outputting the final periodic estimate.

22. The non-transitory computer readable medium having computer executable instructions of claim 18, further including the step of removing outliers from the stored length estimates prior to generating the resampled estimated length vectors.

23. The non-transitory computer readable medium having computer executable instructions of claims 18 and 19, further including the steps of calculating a standard deviation of the resample means, determining that the standard deviation is greater than a maximum standard deviation, and restarting the instructions if the standard deviation is greater than the maximum.

24. A method of estimating a frequency of a periodic signal, the method comprising the steps of:

receiving a periodic input signal;

processing the periodic input signal with a comparator circuit to generate a rectangular periodic signal having a frequency equal to a frequency of the periodic input signal;

counting a number of ascending or descending pulse edges of the comparator signal to generate a length estimate of a cycle of the rectangular periodic signal;

storing the length estimate;

repeating the receiving, processing, detecting, counting, and storing steps to until a predefined number of length estimates are stored;

calculating a final periodic estimate of the periodic signal based on the resample means; and outputting the final periodic estimate.

25. The method of claim 24, further including the step of removing outliers from the stored length estimates prior to generating the resampled estimated length vectors.

26. The method of claims 24 and 25, further including the steps of calculating a standard deviation of the resample means, determining that the standard deviation is greater than a maximum standard deviation, and restarting the method of estimating a frequency of a periodic signal if the standard deviation is greater than the maximum.

27. The method of any of claims 24-26, wherein the periodic estimator module is executable by the processor to generate length estimates for at least 10 cycles of the periodic signal.

28. The method of claim 27, wherein the periodic estimator module is executable by the processor to generate length estimates for at least 100 cycles of the periodic signal.

29. The method of any of claims 24-28, wherein the periodic estimator module is executable by the processor to generate at least 100 resampled estimated length vectors.

30. The method of claim 29, wherein the periodic estimator module is executable by the processor to generate at least 10,000 resampled estimated length vectors.

31. The method of any of claims 24-30, wherein each resampled estimated length vector has a vector length equal to the number of length estimates.

32. A device that executes the method of any of claims 24-30.