WO2017052125A1

WO2017052125A1 - Method and system for operating sram-based tcam with increased number of bits

Info

Publication number: WO2017052125A1
Application number: PCT/KR2016/010215
Authority: WO
Inventors: 알리아메드; 백상현
Original assignee: 한양대학교 에리카산학협력단
Priority date: 2015-09-23
Filing date: 2016-09-09
Publication date: 2017-03-30

Abstract

A method for operating a static random access memory (SRAM)-based ternary content addressable memory (TCAM) with increased number of bits comprises: a step of receiving input data; a step of dividing the input data into a plurality of sub-keys on the basis of the number of virtual blocks divided from an SRAM; a step of sequentially applying the plurality of sub-keys to the virtual blocks; and a step of outputting a specific address value corresponding to the input data on the basis of the application result.

Description

Operation method and system of SRAM-based TCAM with increased number of bits

The following embodiments are technologies related to a static random access memory (SRAM) -based TCAM (Ternary Content Addressable Memory) operating system and a method thereof, and a technique for an SRAM-based TCAM that operates by increasing the number of bits emulated in the SRAM.

Typically, a conventional SRAM-based TCAM such as a CAM (Content Addressable Memory) is an apparatus that receives input data and outputs an address value corresponding to the input data. For example, referring to FIG. 1 illustrating an SRAM-based TCAM, the SRAM-based TCAM 100 receives input data 110 and outputs an address value 120 corresponding to the input data 110.

Since such conventional SRAM-based TCAM uses SRAM resources while TCAM data is mapped to SRAM, there is a problem that the number of TCAM bits emulated in SRAM is limited (reduced) by the limited capacity of the physical addresses of the SRAM.

Accordingly, the following embodiments propose a technique for increasing the number of TCAM bits emulated in SRAM in an SRAM-based TCAM.

One embodiment provides a method and system for operating an SRAM-based TCAM that increases the number of TCAM bits emulated in the SRAM.

Specifically, one embodiment provides a method and system for operating an SRAM-based TCAM that divides the SRAM into virtual blocks, thereby increasing the number of TCAM bits emulated in the virtual blocks.

According to an embodiment, a method of operating a static random access memory (SRAM) -based ternary content addressable memory (TCAM) having an increased number of bits may include receiving input data; Dividing the input data into a plurality of subkeys based on the number of divided virtual blocks by the SRAM; Sequentially applying the plurality of subkeys to the virtual blocks; And outputting a specific address value corresponding to the input data based on the application result.

The outputting of an address value corresponding to the input data based on the application result may include obtaining the address bits corresponding to each of the plurality of sub keys as a result of the application; Comparing the address bits corresponding to each of the plurality of sub keys with each other and extracting a matching bit; And outputting the specific address value corresponding to the matched bit.

Comparing the address bits corresponding to each of the plurality of sub keys with each other and extracting a matching bit may include performing a bitwise operation on address bits corresponding to each of the plurality of sub keys; And extracting the matched bit based on the execution result.

Performing a bitwise operation on address bits corresponding to each of the plurality of subkeys is performing a bitwise AND operation on address bits corresponding to each of the plurality of subkeys. Can be.

Acquiring address bits corresponding to each of the plurality of sub keys may include outputting address bits corresponding to each of the plurality of sub keys through a demultiplexer (DEMUX) connected to a rear end of the SRAM. have.

Comparing the address bits corresponding to each of the plurality of sub keys with each other and extracting a matching bit, comparing the address bits corresponding to each of the plurality of sub keys with each other using a logic circuit connected to an output of the demultiplexer It may include the step.

The outputting of the specific address value corresponding to the matching bit may include outputting the specific address value through a priority encoder connected to an output terminal of the logic circuit when there are a plurality of matching bits. It may include.

The sequentially applying the plurality of subkeys to the virtual blocks may be performed on a block corresponding to each of the plurality of subkeys of the virtual blocks through a multiplexer (MUX) connected to a front end of the SRAM. And applying each of the plurality of sub keys.

The method of operating the SRAM-based TCAM may further include storing the input data in association with the specific address value on the SRAM.

The method of operating the SRAM-based TCAM may further include dividing the address space of the SRAM into the virtual blocks.

Each of the virtual blocks in which the SRAM is divided may store address bits of the SRAM-based TCAM.

The SRAM-based TCAM may be mapped to the SRAM based on a relationship between address bits of the SRAM-based TCAM and data to be stored in the SRAM.

According to an embodiment, an SRAM-based TCAM system having an increased number of bits includes a receiver configured to receive input data; A dividing unit dividing the input data into a plurality of sub keys based on the number of virtual blocks in which an SRAM is divided; An application unit for sequentially applying the plurality of sub keys to the virtual blocks; And an output unit for outputting a specific address value corresponding to the input data based on the application result.

The output unit obtains address bits corresponding to each of the plurality of sub keys as a result of the application, compares the address bits corresponding to each of the plurality of sub keys with each other, extracts a matched bit, and corresponds to the matched bit. The specific address value may be output.

The output unit may store the input data in association with the specific address value on the SRAM.

One embodiment can provide a method and system for operating an SRAM-based TCAM that increases the number of TCAM bits emulated in the SRAM.

Specifically, one embodiment may provide a method and system for operating an SRAM-based TCAM that divides the SRAM into virtual blocks, thereby increasing the number of TCAM bits emulated in the virtual blocks.

Thus, one embodiment may increase the number of TCAM bits emulated in SRAM at low cost.

1 is a diagram illustrating an SRAM-based TCAM.

2 is a diagram illustrating an SRAM divided into virtual blocks according to an exemplary embodiment.

3 is a diagram illustrating a mapping process of an SRAM-based TCAM.

FIG. 4 is a diagram illustrating an SRAM-based TCAM that increases the number of TCAM bits emulated in an SRAM divided into two virtual blocks according to an embodiment.

5 is a diagram illustrating a relationship between the number of virtual blocks in which an SRAM is divided and the number of TCAM bits emulated in the SRAM, according to an exemplary embodiment.

6 is a diagram illustrating an SRAM-based TCAM system according to an embodiment.

7 is a flowchart illustrating a method of operating an SRAM-based TCAM according to an embodiment.

8 is a block diagram illustrating an SRAM-based TCAM system according to an embodiment.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the embodiments. Also, like reference numerals in the drawings denote like elements.

Also, the terminology used herein is a term used to properly express a preferred embodiment of the present invention, which may vary depending on a user, an operator's intention, or customs in the field to which the present invention belongs. Therefore, the definitions of the terms should be made based on the contents throughout the specification.

2, an exemplary SRAM (210) according to the example may be a 2 ⁿ pieces of address of (n-bit addresses) and the address a single port (single port) SRAM having a 2 ⁿ x K D of the K bits per .

Here, the SRAM 210 may be divided into m virtual blocks, which is a preset number. In this case, the number m of dividing the SRAM 210 may be adaptively adjusted according to the size of each of the virtual blocks to be divided.

Each of the virtual blocks in which the SRAM 210 is divided into m may have log ₂ (2 ⁿ / m) bit addresses. Accordingly, log ₂ (2 ⁿ / m) bit addresses are sequentially input according to m cycles through the multiplexer (MUX) 220 connected to the front end of the SRAM 210 and connected to the rear end of the SRAM 210. The SRAM 210 is divided into a TCAM (SRAM 210 based TCAM) using an SRAM 210 resource in which K address bits position data are sequentially outputted every clock cycle through the demultiplexer (DEMUX) 230. Receive input data using each of the virtual blocks that have been created. An address value corresponding to the input data can be output. Detailed description thereof will be described below.

3 is a diagram illustrating a mapping process of an SRAM-based TCAM.

Referring to FIG. 3, the TCAM 310 may be mapped to the SRAM 320 as shown in Equation 1 below.

SRAM unit (2 ⁿ x K) ↔ TCAM (K xn)

mapping

For example, 2 ⁿ pieces of address of (n-bit addresses) and SRAM (320) having 2 ⁿ x K D of the K bits per address is TCAM (310 having a kxn dimensions of n bits per K of address values and the address ) Can be mapped. That is, the TCAM 310 may be mapped to the SRAM 320 based on a relationship between address bits stored in the SRAM 320 and data (eg, input data) to be stored in the SRAM 320.

Accordingly, the SRAM 320 based TCAM 310 may receive n bit input data and output K address bits corresponding to the n bit input data. In this case, K address bits may mean potential match addresses. Each bit of such K address bits may represent an address value.

According to one embodiment, the SRAM-based TCAM divides the SRAM 320 into virtual blocks, thereby providing an SRAM 320 (virtual blocks) without changing the physical structure of the limited capacity of the physical addresses of the SRAM 320. It is possible to increase the number of TCAM bits that are emulated. Detailed description thereof will be made with reference to FIG. 4.

Referring to FIG. 4, the SRAM 410 according to an embodiment may increase the number of bits of the TCAM 420 emulated by dividing into two virtual blocks.

In the SRAM it is divided into m number of virtual blocks, as described above, each of the blocks may have a virtual 2-dimensional ^A xk of the K bits per s log _{2 (2} ⁿ / m) bits of address and the address. Where A is log ₂ (2 ⁿ / m).

Thus, each of the virtual blocks of the two divided SRAMs 410 may have a 2 ^n-1 xk order dimension, and each of the virtual blocks may be mapped to a TCAM having a kx (n-1) dimension. . That is, the SRAM 410 is mapped to the

TCAMs

421 and 422 having two kx (n−1) dimensions, thereby increasing the number of bits of the TCAM 420 emulated in the SRAM 410.

Although not shown in the drawing, when the SRAM 410 is divided into four virtual blocks, the SRAM 410 may be mapped to a TCAM having four k x (n-2) dimensions.

As such, since the SRAM 410 is divided into a plurality of virtual blocks, address bits by the SRAM-based TCAM 420 may be stored in each of the divided virtual blocks. Accordingly, the SRAM-based TCAM 420 increases the number of bits of the TCAM 420 emulated in the SRAM 410 by using the SRAM 410 divided into virtual blocks, or the SRAM-based TCAM 420. May increase the area where the address bits are stored.

In this case, the data throughput of each of the virtual blocks in which the SRAM 410 is divided may be reduced in proportion to the number of virtual blocks in which the SRAM 410 is divided. Therefore, by adjusting the number of virtual blocks in which the SRAM 410 is divided, the data throughput of each of the virtual blocks in which the SRAM 410 is divided may be adjusted. That is, in order to change the data throughput of each of the virtual blocks in which the SRAM 410 is divided, the number of virtual blocks in which the SRAM 410 is divided may be adjusted.

The number of bits of the TCAM 420 according to the number of virtual blocks in which the SRAM 410 is divided will be described with reference to FIG. 5.

5 is a diagram illustrating a relationship between the number of virtual blocks 510 in which an SRAM is divided and the number of TCAM bits 520 emulated in the SRAM, according to an exemplary embodiment.

Referring to FIG. 5, the number of TCAM bits 520 emulated in the SRAM according to an embodiment may increase rapidly in proportion to the number 510 of virtual blocks in which the SRAM is divided. Thus, the SRAM can be divided into virtual blocks by repeating the process of dividing to the resource allowable limit, thereby increasing the number of emulated TCAM bits 520.

Referring to FIG. 6, an SRAM-based TCAM system according to an embodiment includes an SRAM 610, a multiplexer 620 connected to a front end of an SRAM 610, and a demultiplexer 630 connected to a rear end of an SRAM 610. And a logic circuit 640 connected to the output terminal of the demultiplexer 630.

In detail, the SRAM-based TCAM system receives input data of D bits, and divides the received input data into a plurality of sub keys (sub input data bits) based on the number of virtual blocks in which the SRAM 610 is divided. can do. For example, an SRAM-based TCAM system can split the D bit input data into m b bit subkeys.

Each of the m b-bit subkeys split as described above may be sequentially applied to a block corresponding to each of the m b-bit subkeys of the virtual blocks through the multiplexer 620.

According to the application result, K address bits corresponding to each of the m b-bit subkeys may be output through the demultiplexer 630. The K address bits corresponding to each of the m b-bit subkeys to be output are compared with each other by the logic circuit 640, so that a matching bit may be extracted.

Therefore, when one or more matching bits are present and extracted, a specific address value corresponding to the matching bits may be output through the priority encoder 650. In this case, when there is one matching bit, the priority encoder may not be used.

More specific embodiments will be described below to describe an SRAM based TCAM system.

According to an embodiment, the SRAM-based TCAM system may use a SRAM having a 16x8 dimension as a resource to implement a table of a TCAM having 8 address values and 8x8 dimensions of 8 bits per address, as shown in Table 1.

When the SRAM used by the TCAM of Table 1 is divided into four virtual blocks SW1, SW2, SW3, and SW4 (each of the virtual blocks includes 2 bits), Table 1 is shown in Table 2. Can be expressed.

Therefore, the TCAM having the table of Table 2 may be mapped to the SRAM having the 16 × 8 dimension having the table of Table 3.

As shown in Table 3, an SRAM having a 16x8 dimension may be composed of four virtual blocks having a 4x8 dimension. Thus, each of the virtual blocks having the 4x8 dimension of Table 3 may store a potential match address with the 8x2 dimension shown in Table 2.

Thus, an SRAM having a 16x8 dimension may be mapped to a TCAM having an 8x8 dimension by being divided into four virtual blocks according to an embodiment.

To verify that the TCAM with 8x8 dimension is properly mapped to the SRAM with 16x8 dimension, looking at the output address value when the input data is 10XXXXXX, the matching address values are determined as 3, 5 and 6 with reference to Table 1 And, it can be seen that the matching address value is determined as 3, 5 and 6 with reference to Table 3. It can be seen that SRAM with 16x8 dimension can be mapped to TCAM with 8x8 dimension.

Referring to FIG. 7, in operation 710, an SRAM-based TCAM system receives input data.

Subsequently, the SRAM-based TCAM system divides the input data into a plurality of sub keys based on the number of virtual blocks in which the SRAM is divided (720).

Next, the SRAM-based TCAM system sequentially applies a plurality of sub keys to the virtual blocks (730).

In this case, the SRAM-based TCAM system may apply each of the plurality of subkeys to a block corresponding to each of the plurality of subkeys of the virtual blocks through a multiplexer (MUX) connected to the front end of the SRAM.

The SRAM-based TCAM system then outputs a particular address value corresponding to the input data based on the application result (740).

In operation 740, the SRAM-based TCAM system obtains address bits corresponding to each of the plurality of sub keys, and compares the address bits corresponding to each of the plurality of sub keys with each other, thereby extracting a matching bit. A specific address value corresponding to may be output.

Here, the SRAM-based TCAM system can obtain address bits corresponding to each of the plurality of sub keys by outputting address bits corresponding to each of the plurality of sub keys through a demultiplexer (DEMUX) connected to a rear end of the SRAM. .

In addition, the SRAM-based TCAM system may compare address bits corresponding to each of the plurality of sub keys using a logic circuit connected to an output terminal of the demultiplexer.

That is, the SRAM-based TCAM system corresponds to each of the plurality of subkeys by performing a bitwise operation on address bits corresponding to each of the plurality of subkeys and extracting a matching bit based on a result of the execution. The matching bits may be extracted by comparing the address bits. A bitwise AND operation may be used as the bitwise operation, but is not limited thereto. Various bitwise operations may be used.

If there are a plurality of matching bits extracted by comparing address bits corresponding to each of the plurality of subkeys with each other, the SRAM-based TCAM system uses a plurality of matching bits through a priority encoder connected to an output of a logic circuit. By setting the priority of the bits, a specific address value corresponding to each of the plurality of matching bits may be sequentially output according to the priority.

According to an embodiment, the SRAM-based TCAM system stores the input data on the SRAM in correspondence with a specific address value thus output, so that the number of TCAM bits emulated in the SRAM without changing the physical structure of the limited capacity of the physical addresses of the SRAM. It can support increased memory function.

Hereinafter, specific examples will be described with reference to Table 3.

For example, if 10001011 is given as the input data D for retrieval, and the number of virtual blocks in which the SRAM is divided is four, the SRAM-based TCAM system receives the input data of 10001011, and then receives four subkeys (SW1). , SW2, SW3, and SW4). Accordingly, SW1 may represent 10, SW2 may represent 00, SW3 may represent 10, and SW4 may represent 11.

Next, the SRAM-based TCAM system sequentially applies SW1 of 10, SW2 of 10, SW3 of 10, and SW4 of 11 by sequentially applying the address bits 00010110 and SW2 corresponding to SW2 with reference to the table in Table 3. The address bits 11100111 corresponding to SW3 and the address bits 10100110 corresponding to SW4 may be obtained.

Accordingly, the SRAM-based TCAM system compares the address bits 00010110 corresponding to SW1, the address bits 10101100 corresponding to SW2, the address bits 11100111 corresponding to SW3, and the address bits 10100110 corresponding to SW4 (for example, perform a bitwise AND operation). Compare) to extract a matching bit 00000100.

In this case, since there is one specific address value corresponding to the matching bit 00000100 as address 5, the SRAM-based TCAM system may output address 5 as a specific address value and associate the input data with the address 5 on the SRAM. .

As such, the algorithms for the above-described series of operating methods are shown in Table 4 below.

Referring to FIG. 8, an SRAM-based TCAM system operates by using a SRAM, a multiplexer connected to the front end of the SRAM, a demultiplexer connected to the rear end of the SRAM, and a logic circuit connected to an output terminal of the demultiplexer. May be integrated into a module to

The SRAM-based TCAM system includes a receiver 810, a divider 820, an applier 830, and an output 840.

The receiver 810 receives input data.

The divider 820 divides the input data into a plurality of subkeys based on the number of virtual blocks in which the SRAM is divided.

The applier 830 sequentially applies the plurality of sub keys to the virtual blocks.

In this case, the application unit 830 may apply each of the plurality of subkeys to a block corresponding to each of the plurality of subkeys among the virtual blocks through the multiplexer MUX connected to the front end of the SRAM.

The output unit 840 outputs a specific address value corresponding to the input data based on the application result.

In detail, as a result of the application, the output unit 840 obtains address bits corresponding to each of the plurality of sub keys, compares the address bits corresponding to each of the plurality of sub keys with each other, and extracts a matching bit, thereby matching a bit. A specific address value corresponding to may be output.

At this time, the output unit 840 outputs address bits corresponding to each of the plurality of subkeys through a demultiplexer (DEMUX) connected to a rear end of the SRAM, thereby obtaining address bits corresponding to each of the plurality of subkeys. Can be.

Also, the output unit 840 may compare address bits corresponding to each of the plurality of sub keys using a logic circuit connected to an output terminal of the demultiplexer.

That is, the output unit 840 performs a bitwise operation on address bits corresponding to each of the plurality of sub keys, and extracts a matching bit based on a result of the execution. Corresponding address bits may be compared with each other to extract matching bits. A bitwise AND operation may be used as the bitwise operation, but is not limited thereto. Various bitwise operations may be used.

If there are a plurality of matching bits extracted by comparing address bits corresponding to each of the plurality of sub keys with each other, the output unit 840 matches the plurality of matching bits through a priority encoder connected to an output terminal of the logic circuit. By setting the priority of the bits to be made, it is possible to sequentially output a specific address value corresponding to each of the plurality of matching bits according to the priority.

In addition, the output unit 840 may store the input data on the SRAM in correspondence with a specific address value to be output, thereby supporting a memory function of increasing the number of TCAM bits emulated in the SRAM.

The apparatus described above may be implemented as a hardware component, a software component, and / or a combination of hardware components and software components. For example, the devices and components described in the embodiments may be, for example, processors, controllers, arithmetic logic units (ALUs), digital signal processors, microcomputers, field programmable arrays (FPAs), It may be implemented using one or more general purpose or special purpose computers, such as a programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to the execution of the software. For convenience of explanation, one processing device may be described as being used, but one of ordinary skill in the art will appreciate that the processing device includes a plurality of processing elements and / or a plurality of types of processing elements. It can be seen that it may include. For example, the processing device may include a plurality of processors or one processor and one controller. In addition, other processing configurations are possible, such as parallel processors.

The software may include a computer program, code, instructions, or a combination of one or more of the above, and configure the processing device to operate as desired, or process it independently or collectively. You can command the device. Software and / or data may be any type of machine, component, physical device, virtual equipment, computer storage medium or device in order to be interpreted by or to provide instructions or data to the processing device. Or may be permanently or temporarily embodied in a signal wave to be transmitted. The software may be distributed over networked computer systems so that they may be stored or executed in a distributed manner. Software and data may be stored on one or more computer readable recording media.

The method according to the embodiment may be embodied in the form of program instructions that can be executed by various computer means and recorded in a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the media may be those specially designed and constructed for the purposes of the embodiments, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks, such as floppy disks. Magneto-optical media, and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

Although the embodiments have been described by the limited embodiments and the drawings as described above, various modifications and variations are possible to those skilled in the art from the above description. For example, the described techniques may be performed in a different order than the described method, and / or components of the described systems, structures, devices, circuits, etc. may be combined or combined in a different form than the described method, or other components. Or even if replaced or substituted by equivalents, an appropriate result can be achieved.

Therefore, other implementations, other embodiments, and equivalents to the claims are within the scope of the claims that follow.

Claims

In the method of operating a Random Random Access Memory (SRAM) based TCAM (Ternary Content Addressable Memory) with an increased number of bits,

Receiving input data;

Dividing the input data into a plurality of subkeys based on the number of divided virtual blocks by the SRAM;

Sequentially applying the plurality of subkeys to the virtual blocks; And

Outputting a specific address value corresponding to the input data based on the application result

SRAM-based TCAM operating method comprising a.
The method of claim 1,

The step of outputting the address value corresponding to the input data based on the application result

Obtaining address bits corresponding to each of the plurality of sub keys as a result of the application;

Comparing the address bits corresponding to each of the plurality of sub keys with each other and extracting a matching bit; And

Outputting the specific address value corresponding to the matched bit

SRAM-based TCAM operating method comprising a.
The method of claim 2,

Comparing the address bits corresponding to each of the plurality of sub keys with each other and extracting a matching bit

Performing a bitwise operation on address bits corresponding to each of the plurality of sub keys; And

Extracting the matched bit based on the execution result

SRAM-based TCAM operating method comprising a.
The method of claim 3,

Performing a bitwise operation on the address bits corresponding to each of the plurality of sub keys

And performing a bitwise AND operation on address bits corresponding to each of the plurality of sub keys.
The method of claim 2,

Acquiring address bits corresponding to each of the plurality of sub keys

Outputting address bits corresponding to each of the plurality of subkeys through a demultiplexer (DEMUX) connected to a rear end of the SRAM;

SRAM-based TCAM operating method comprising a.
The method of claim 5,

Comparing the address bits corresponding to each of the plurality of sub keys with each other and extracting a matching bit

Comparing address bits corresponding to each of the plurality of subkeys with each other using a logic circuit connected to an output terminal of the demultiplexer

SRAM-based TCAM operating method comprising a.
The method of claim 6,

Outputting the specific address value corresponding to the matched bit

Outputting the specific address value through a priority encoder connected to an output terminal of the logic circuit when there are a plurality of matching bits;

SRAM-based TCAM operating method comprising a.
The method of claim 1,

Sequentially applying the plurality of subkeys to the virtual blocks

Applying each of the plurality of subkeys to a block corresponding to each of the plurality of subkeys of the virtual blocks through a multiplexer (MUX) connected to a front end of the SRAM;

SRAM-based TCAM operating method comprising a.
The method of claim 1,

Storing the input data in association with the specific address value on the SRAM

Method of operation of the SRAM-based TCAM further comprising.
The method of claim 1,

Dividing the SRAM into the virtual blocks by dividing the address space of the SRAM

Method of operation of the SRAM-based TCAM further comprising.
The method of claim 10,

Each of the virtual blocks in which the SRAM is divided

Method bits of the SRAM-based TCAM is stored, the address bits by the SRAM-based TCAM.
The method of claim 1,

The SRAM-based TCAM

And mapped to the SRAM based on a relationship between address bits by the SRAM-based TCAM and data to be stored in the SRAM.
A computer-readable recording medium having recorded thereon a program for performing the method of any one of claims 1 to 12.
In the SRAM-based TCAM system with an increased number of bits,

A receiver for receiving input data;

A dividing unit dividing the input data into a plurality of sub keys based on the number of virtual blocks in which an SRAM is divided;

An application unit for sequentially applying the plurality of sub keys to the virtual blocks; And

An output unit for outputting a specific address value corresponding to the input data based on the application result

SRAM-based TCAM system comprising a.
The method of claim 14,

The output unit

As a result of the application, address bits corresponding to each of the plurality of sub keys are obtained, the address bits corresponding to each of the plurality of sub keys are compared with each other, and a matching bit is extracted, and the specific corresponding to the matching bits is obtained. SRAM-based TCAM system for outputting address values.
The method of claim 14,

The output unit

And store the input data on the SRAM in association with the specific address value.