WO2017020328A1 - Manufacturing method for array substrate - Google Patents

Manufacturing method for array substrate Download PDF

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Publication number
WO2017020328A1
WO2017020328A1 PCT/CN2015/086476 CN2015086476W WO2017020328A1 WO 2017020328 A1 WO2017020328 A1 WO 2017020328A1 CN 2015086476 W CN2015086476 W CN 2015086476W WO 2017020328 A1 WO2017020328 A1 WO 2017020328A1
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Prior art keywords
layer
polysilicon
array substrate
fabricating
gate
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PCT/CN2015/086476
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French (fr)
Chinese (zh)
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李金磊
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武汉华星光电技术有限公司
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Publication of WO2017020328A1 publication Critical patent/WO2017020328A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a method for fabricating an array substrate.
  • a display made of a low-temperature polysilicon thin film transistor including a liquid crystal display or an OLED display driven by a low-temperature polysilicon thin film transistor array, and an electron mobility of a low-temperature polysilicon thin film transistor of up to 50 cm 2 /Vs or more than that of an amorphous silicon thin film transistor (about 0.7cm 2 /Vs ) is 2 ⁇ 3 orders of magnitude higher. Due to the excellent device performance described above, the low-temperature polysilicon thin film transistor array substrate can integrate the driver IC into the glass substrate, which can save the cost of IC manufacturing for display manufacturing. And is conducive to making a narrow bezel display.
  • the low-temperature polysilicon thin film transistor array substrate integrates the IC onto the substrate, and is not subject to TAB using conventional amorphous silicon panels.
  • COG chip on glass
  • PPI pixel per inch
  • the thin film transistor can be made smaller, and the aperture ratio of the panel can be correspondingly improved.
  • the fabrication of low temperature polysilicon thin film transistor array substrates can be done on the periphery of the panel using a COMS-like manufacturing process.
  • the polysilicon thin film transistor and the P-type polysilicon thin film transistor are relatively easy to integrate the driving IC to the periphery of the panel by the integrated circuit design method.
  • the threshold voltage of an N-type TFT fabricated by a typical polysilicon film is usually 0.3 volts, while the threshold voltage of a P-type TFT is negative. At about 5 volts, the absolute values of the two differ greatly.
  • N-type polysilicon thin film transistor and P When a polysilicon thin film transistor forms a logic gate circuit in a driving region, it is necessary to adjust the threshold voltages (also called turn-on voltages) of the two types of polysilicon thin film transistors so that the threshold voltages of the two can be matched, that is, the N-type polysilicon thin film transistors and P
  • the threshold voltage of the polysilicon thin film transistor is adjusted to be symmetrical with respect to the zero point, thereby achieving the effect of improving the complementary transistor circuit and facilitating the IC Circuit design.
  • the threshold voltage is adjusted by conventionally implanting boron ions into polysilicon by means of ion implantation. That is, after the polycrystalline silicon is prepared, boron ions are doped by ion implantation, and since the ion implantation apparatus is relatively expensive, the production cost is high. At the same time, due to the lattice damage of the polysilicon at the channel during high energy ion implantation, it is not conducive to improving the mobility of carriers and the reliability of thin film transistors.
  • the object of the present invention is to provide an array substrate and a manufacturing method thereof, which solve the technical problems that the prior art process is complicated, the production cost is high, and the application is not suitable for large size.
  • the present invention constructs a method for fabricating an array substrate, comprising the following steps:
  • amorphous silicon layer on the buffer layer by chemical vapor deposition; wherein a raw material for preparing the amorphous silicon layer and a mixed raw material containing boron elements are added to the deposition chamber; and the boron-containing element is mixed
  • the raw material is a mixed gas of diborane and hydrogen; the thickness of the light shielding layer is 300 ⁇ ⁇ 1000 ⁇ ;
  • first metal layer on the gate insulating layer, and patterning the first metal layer to form at least a first gate and a second gate; the first gate and the first poly Corresponding to the silicon portion, the second gate corresponds to the second polysilicon portion;
  • the first portion is a portion of the first polysilicon portion corresponding to the first gate; and the second portion is the second and second portions The portion corresponding to the gate;
  • a second metal layer is formed on the protective layer, and the second metal layer is patterned to form at least two sources and at least two drains.
  • the molar mixing ratio of the diborane to the hydrogen is 1: 1000 ⁇ 1: 5000.
  • the content of the boron element in the mixed gas is 1 ⁇ 10 11 to 5 ⁇ 10 12 atoms/cm 2 .
  • the step of converting the amorphous silicon layer into a polysilicon layer comprises:
  • the demagnetized amorphous silicon layer is subjected to excimer laser annealing treatment and laser irradiation.
  • the second metal layer is patterned to form two sources and two drains; the method further includes:
  • the method further includes: forming a second via on the protective layer corresponding to each of the drains, wherein the drain passes through the second pass The hole is connected to the first polysilicon portion; the other drain is connected to the second polysilicon portion through the second via.
  • the method further includes:
  • a flat layer is formed on the second metal layer, and a third via is provided on the flat layer corresponding to each of the drains or each of the sources.
  • the method further includes:
  • the transparent conductive layer is connected to the second metal layer through the third via.
  • the present invention constructs a method for fabricating an array substrate, comprising the following steps:
  • first metal layer on the gate insulating layer, and patterning the first metal layer to form at least a first gate and a second gate; the first gate and the first poly Corresponding to the silicon portion, the second gate corresponds to the second polysilicon portion;
  • the first portion is a portion of the first polysilicon portion corresponding to the first gate; and the second portion is the second and second portions The portion corresponding to the gate;
  • a second metal layer is formed on the protective layer, and the second metal layer is patterned to form at least two sources and two drains.
  • the mixed material containing the boron element is a mixed gas of diborane and hydrogen.
  • the molar mixing ratio of the diborane to the hydrogen is 1: 1000 ⁇ 1: 5000.
  • the content of the boron element in the mixed gas is 1 ⁇ 10 11 to 5 ⁇ 10 12 atoms/cm 2 .
  • the step of converting the amorphous silicon layer into a polysilicon layer comprises:
  • the demagnetized amorphous silicon layer is subjected to excimer laser annealing treatment and laser irradiation.
  • the second metal layer is patterned to form two sources and two drains; the method further includes:
  • the method further includes:
  • the method further includes:
  • a flat layer is formed on the second metal layer, and a third via is provided on the flat layer corresponding to each of the drains or each of the sources.
  • the method further includes:
  • the transparent conductive layer is connected to the second metal layer through the third via.
  • the thickness of the light shielding layer is 300 ⁇ to 1000 ⁇ .
  • the fabrication method of the array substrate reduces the use of the ion implantation device, and can avoid the lattice damage of the polysilicon at the channel during the high energy ion implantation, thereby improving the mobility of the carrier and the reliability of the thin film transistor, thereby reducing Cost of production.
  • the liquid crystal display panel and device of the present invention reduces the production cost and the size of the liquid crystal display panel by rearranging the existing chips and electronic components.
  • FIG. 1 is a schematic view showing a first step of a method for fabricating an array substrate of the present invention
  • FIG. 2 is a schematic view showing a second step of the method for fabricating an array substrate of the present invention
  • FIG. 3 is a schematic view showing a third step of the method for fabricating the array substrate of the present invention.
  • FIG. 4 is a schematic view showing a fourth step of the method for fabricating the array substrate of the present invention.
  • FIG. 5 is a schematic view showing a fifth step of the method for fabricating an array substrate of the present invention.
  • FIG. 6 is a schematic view showing a sixth step of the method for fabricating an array substrate of the present invention.
  • FIG. 7 is a schematic view showing a seventh step of the method for fabricating an array substrate of the present invention.
  • FIG. 8 is a schematic view showing an eighth step of the method for fabricating the array substrate of the present invention.
  • FIG. 9 is a schematic view showing the ninth step of the method for fabricating the array substrate of the present invention.
  • FIG. 10 is a schematic view showing a preferred mode of the method for fabricating the array substrate of the present invention.
  • the array substrate of the present invention is as shown in FIG. 9, and its base substrate 111, light shielding layer 112, ion barrier layer 113, buffer layer 114, a polysilicon layer 116, a gate insulating layer 117, a first metal layer 118, a protective layer 121, a second metal layer, may further include a flat layer and a transparent conductive layer (not shown);
  • the light shielding layer 112 is located on the base substrate 111; the ion barrier layer 113 is located on the light shielding layer 112
  • the buffer layer 114 is located on the ion blocking layer 113; the polysilicon layer 116 is located at the buffer layer 114 Formed by converting an amorphous silicon layer, wherein the raw material of the amorphous silicon layer is doped with a mixed raw material containing a boron element;
  • the gate insulating layer 117 is located on the polysilicon layer; a metal layer 118 Located on the gate insulating layer 117, the first metal layer 118 includes gate regions of two thin film transistors; the protective layer 121 is located at the first metal layer 118
  • the second metal layer is disposed on the protective layer 121, and the second metal layer includes a drain region and a source region of the two thin film transistors;
  • the flat layer is located on the second metal layer, and a third via is disposed on the flat layer corresponding to each of the drains or each of the sources; the transparent conductive layer is located at the flat
  • the transparent conductive layer is connected to the second metal layer through the third via, that is, to the source or the drain.
  • the transparent conductive layer may include a pixel electrode.
  • the manufacturing method of the above array substrate includes:
  • the substrate is placed in a deposition chamber, and a light shielding layer 112 is formed on the substrate 111;
  • the base substrate 111 is placed in a deposition chamber, as shown in FIG. 1, the light shielding layer 112. Specifically, it is obtained by a process of coating, photolithography (photoresist coating, exposure, development, etching, photoresist stripping); the material of the light shielding layer 112 may be an opaque metal layer, such as Mo, Al, Ti Alternatively, it may be a material that absorbs light, such as an amorphous silicon layer.
  • the light shielding layer 112 has a thickness of 300 ⁇ to 1000 ⁇ . Therefore, the light leakage current generated by the illumination of the array substrate polysilicon layer by the light emitted from the backlight module is reduced.
  • the material of the ion barrier layer 113 is silicon nitride SiNx, which acts to avoid the substrate 111.
  • the sodium and potassium ions in the diffusion diffuse into the polysilicon layer in a subsequent high temperature process. Since these sodium and potassium ions form deep defects in the electronic energy levels of the polysilicon semiconductor, resulting in TFT The on-current of the device is reduced, and the leakage current is increased, which ultimately affects the display effect and reliability.
  • the material of the buffer layer 114 may be SiO 2 . Since the thermal expansion coefficients of the ion barrier layer 113 and the subsequent amorphous silicon film are relatively close, a relatively concentrated heterojunction stress is easily generated, thereby causing interface defects.
  • the buffer layer can prevent concentration of heterojunction stress to reduce interface defects.
  • a preparation raw material of the amorphous silicon layer and a mixed raw material containing a boron element are added to the deposition chamber;
  • a plasma assisted chemical vapor deposition processes particularly with the addition of a mixed gas of SiH 4 H 2 in a plasma assisted chemical vapor deposition (PECVD) chambers, SiH 4 gas and H 2 in the state in which the plasma chemical
  • PECVD plasma assisted chemical vapor deposition
  • the reaction produces a hydrogenated amorphous silicon film.
  • the present invention also introduces a mixed gas of B 2 H 6 and H 2 in a chamber of plasma-assisted chemical vapor deposition (PECVD).
  • PECVD plasma-assisted chemical vapor deposition
  • the threshold voltage of the N-type polysilicon thin film transistor and the P-type polysilicon thin film transistor can be made symmetrical with respect to the zero point by doping the mixed raw material containing the boron element in the preparation raw material.
  • B 2 H 6 gas Due to the pre-configured mixture of B 2 H 6 and H 2 , the B 2 H 6 gas is diluted on the one hand, so that the flow rate of the gas during the process can be relatively large, so that the flow rate and uniformity can be accurately controlled.
  • B2H6 gas is a dangerous gas that is highly flammable, explosive and highly toxic, it is premixed with H 2 to increase the safety of B 2 H 6 gas transportation.
  • the molar mixing ratio of the B 2 H 6 and H 2 gas is 1:1000 ⁇ 1:5000;
  • the temperature in the process chamber to 200 °C -350 °C, where the flow rate of SiH 4 gas is 5000 ⁇ 17000sccm, the flow rate of H 2 gas is 1000 ⁇ 60000sccm, and the flow rate of mixed gas of B 2 H 6 and H 2 is 10 ⁇ 500sccm. Since the doping amount of boron element is very small, if pure B2H6 gas is used, according to the calculation of the flow rate of B2H6 between 0 sccm and 1 sccm, the gas flow rate of B 2 H 6 is very small, and it is not easy to accurately control the doping amount and doping. Uniformity results in poor process stability and does not meet the requirements for process repeatability and stability in mass production.
  • a premixed mixture of B 2 H 6 and H 2 is used, and the molar mixing ratio of B 2 H 6 and H 2 gas is 1:1000 to 1:5000.
  • the flow rate of the mixed gas of B 2 H 6 and H 2 is increased.
  • the content of the boron element in the mixed gas is 1 ⁇ 10 11 to 5 ⁇ 10 12 atoms/cm 2 .
  • S104 specifically includes:
  • the number of the polycrystalline silicon portions is not limited to the number shown in the drawing, and may be two or more.
  • the gate insulating layer 117 is formed on the polysilicon layer 116.
  • the material of the gate insulating layer 117 is silicon nitride.
  • the first gate corresponds to the first polysilicon portion
  • the second gate corresponds to the second polysilicon portion; as shown in FIG. 6, in the step After S105, a first metal layer is formed on the gate insulating layer 117, and the first metal layer may be Mo, Mo/Al/Mo, Ti, Ti/Mo. a single layer of metal or metal composite layer; and the first metal layer is patterned (ie, photolithography process) to form two gates 118;
  • the first polysilicon portion (the polysilicon layer on the left side) first blocks the first polysilicon portion (the polysilicon layer on the right side) with a photoresist, and only exposes the polysilicon layer on the left side, to the left.
  • the side of the polysilicon layer on both sides of the first portion is doped with boron by ion implantation.
  • the doping concentration of boron is 1 ⁇ 10 15 atoms / cm 2 ⁇ 5 ⁇ 10 15 atoms / Cm 2 , a doped polysilicon region 119 forming boron element, ie an ohmic contact region of the P-MOS TFT;
  • the polysilicon layer on the left side is shielded by the photoresist, and only the polysilicon layer on the right side is exposed, and the polysilicon layer region on the right side of the first portion is doped by the ion implantation method.
  • the concentration is 1 ⁇ 10 15 atoms/cm 2 to 5 ⁇ 10 15 atoms/cm 2 , and a doped polysilicon region 120 of a phosphorus element, that is, an ohmic contact region of the N-MOS TFT is formed.
  • step S108 the fabrication of the protective layer 121 layer is performed, as shown in Fig. 8, using plasma-assisted chemical vapor deposition.
  • a protective layer 121 is formed on the first metal layer.
  • step S108 as shown in FIG. 9, at the protective layer 121 A second metal layer is formed by coating, and after the second metal layer is patterned (ie, a photolithography process), two source electrodes 21 and two drain electrodes 22 are formed.
  • the method further includes:
  • One of the source electrodes 21 is connected to the first polysilicon portion through the first via hole (not shown), and the other source electrode 21 Connecting to the second polysilicon portion through the first via.
  • One of the drains 22 is connected to the first polysilicon portion through the second via (not shown); the other of the drains 22 Connecting to the second polysilicon portion through the second via.
  • the transparent conductive layer includes a pixel electrode.
  • thermoelectron effect of the ohmic contact region is further provided with a lightly doped region 122 in the patterned polysilicon layer, and the lightly doped region 122 can be fabricated by ion implantation.
  • the prior art is to dope the boron ions into the polysilicon layer by ion implantation after the polysilicon layer is formed, the lattice damage of the polysilicon is easily caused, and the present invention performs the film deposition of the amorphous silicon layer.
  • Doping the boron element so that N-type polysilicon thin film transistor and P
  • the threshold voltage of the polysilicon thin film transistor is symmetric at zero point; thereby saving one ion implantation process and reducing the use of the ion implantation apparatus; the invention can also avoid the ion implantation damage to the polycrystalline silicon lattice at the channel, and improve the loading of the polysilicon thin film transistor. Mobility and component reliability.
  • the array substrate and the manufacturing method thereof reduce the use of the ion implantation device, and can avoid the lattice damage of the polysilicon at the channel during the high energy ion implantation, thereby improving the mobility of the carrier and the reliability of the thin film transistor, thereby reduce manufacturing cost.

Abstract

A manufacturing method for an array substrate, comprising forming a light shielding layer (112), an ion barrier layer (113), a buffer layer (114) and a non-crystalline silicon layer (115) on a substrate (111), wherein a raw material for preparing the non-crystalline silicon layer (115) and a mixed raw material containing the element boron are added into a deposition chamber; the non-crystalline silicon layer (115) is converted into a polycrystalline silicon layer (116), the polycrystalline silicon layer (116) is patterned, and a gate insulation layer (117), a first metal layer (118), a protective layer (121) and a second metal layer are formed on the patterned polycrystalline silicon layer (116).

Description

一种阵列基板的制作方法 Array substrate manufacturing method 技术领域Technical field
本发明涉及液晶显示器技术领域，特别是涉及一种阵列基板的制作方法。 The present invention relates to the field of liquid crystal display technologies, and in particular, to a method for fabricating an array substrate.
背景技术Background technique
低温多晶硅薄膜晶体管制作的显示器，包括液晶显示器或以低温多晶硅薄膜晶体管阵列驱动的 OLED 显示器，低温多晶硅薄膜晶体管的电子迁移率高达 50cm2/V.s 以上，比非晶硅薄膜晶体管的电子迁移率（约 0.7cm2/V.s ）高出 2~3 个数量级，由于具有上述优良的器件性能，使低温多晶硅的薄膜晶体管阵列基板可以把驱动 IC 也集成到玻璃基板上，可以节省显示器制造的 IC 采购的成本，并有利于制作窄边框显示器。A display made of a low-temperature polysilicon thin film transistor, including a liquid crystal display or an OLED display driven by a low-temperature polysilicon thin film transistor array, and an electron mobility of a low-temperature polysilicon thin film transistor of up to 50 cm 2 /Vs or more than that of an amorphous silicon thin film transistor (about 0.7cm 2 /Vs ) is 2~3 orders of magnitude higher. Due to the excellent device performance described above, the low-temperature polysilicon thin film transistor array substrate can integrate the driver IC into the glass substrate, which can save the cost of IC manufacturing for display manufacturing. And is conducive to making a narrow bezel display.
另外，低温多晶硅薄膜晶体管阵列基板把 IC 集成到基板上后，就不受传统非晶硅面板采用 TAB 或 COG(chip on glass) 的外引角间距的限制，可以制作出高 PPI(pixel per inch) 的高清晰显示器。另由于低温多晶硅薄膜晶体管的高电子迁移率，薄膜晶体管可以做更小，面板的开口率也可以相应的提高。In addition, the low-temperature polysilicon thin film transistor array substrate integrates the IC onto the substrate, and is not subject to TAB using conventional amorphous silicon panels. COG (chip on glass) limits the external lead pitch to produce a high PPI (pixel per inch) High definition display. In addition, due to the high electron mobility of the low-temperature polysilicon thin film transistor, the thin film transistor can be made smaller, and the aperture ratio of the panel can be correspondingly improved.
低温多晶硅薄膜晶体管阵列基板的制造可以使用类似 COMS 的制造工艺，在面板的外围制作 N 型多晶硅薄膜晶体管和 P 型多晶硅薄膜晶体管，通过集成电路设计的方法，比较容易将驱动 IC 集成到面板的外围。The fabrication of low temperature polysilicon thin film transistor array substrates can be done on the periphery of the panel using a COMS-like manufacturing process. The polysilicon thin film transistor and the P-type polysilicon thin film transistor are relatively easy to integrate the driving IC to the periphery of the panel by the integrated circuit design method.
一般多晶硅薄膜制造出来的 N 型 TFT 的阈值电压通常为 0.3 伏，而 P 型 TFT 的阈值电压为负 5 伏左右，两者的绝对值相差较大。当用 N 型多晶硅薄膜晶体管和 P 型多晶硅薄膜晶体管在驱动区形成逻辑门电路时，需要对两者的阈值电压（也叫开启电压）做调整，以便两者阈值电压能够匹配，也就是将 N 型多晶硅薄膜晶体管与 P 型多晶硅薄膜晶体管的阈值电压调整到对于零点位对称，从而达到提升互补式晶体管电路的效果，便于 IC 电路的设计。阈值电压的调整，传统工艺上通常采用离子注入的方式将硼离子掺杂到多晶硅中来实现。即在制备好多晶硅后，再通过离子注入的方式掺杂硼离子，由于离子注入设备比较昂贵，因此生产成本较高。同时由于高能量离子注入时对沟道处多晶硅的晶格损伤，不利于提高载流子的迁移率和薄膜晶体管的可靠性The threshold voltage of an N-type TFT fabricated by a typical polysilicon film is usually 0.3 volts, while the threshold voltage of a P-type TFT is negative. At about 5 volts, the absolute values of the two differ greatly. When using N-type polysilicon thin film transistor and P When a polysilicon thin film transistor forms a logic gate circuit in a driving region, it is necessary to adjust the threshold voltages (also called turn-on voltages) of the two types of polysilicon thin film transistors so that the threshold voltages of the two can be matched, that is, the N-type polysilicon thin film transistors and P The threshold voltage of the polysilicon thin film transistor is adjusted to be symmetrical with respect to the zero point, thereby achieving the effect of improving the complementary transistor circuit and facilitating the IC Circuit design. The threshold voltage is adjusted by conventionally implanting boron ions into polysilicon by means of ion implantation. That is, after the polycrystalline silicon is prepared, boron ions are doped by ion implantation, and since the ion implantation apparatus is relatively expensive, the production cost is high. At the same time, due to the lattice damage of the polysilicon at the channel during high energy ion implantation, it is not conducive to improving the mobility of carriers and the reliability of thin film transistors.
因此，有必要提供一种阵列基板及其制作方法，以解决现有技术所存在的问题。Therefore, it is necessary to provide an array substrate and a method of fabricating the same to solve the problems of the prior art.
技术问题technical problem
本发明的目的在于提供一种阵列基板及其制作方法，以解决现有技术制程过程比较复杂，生产成本较高，不利于在大尺寸上应用的技术问题。 The object of the present invention is to provide an array substrate and a manufacturing method thereof, which solve the technical problems that the prior art process is complicated, the production cost is high, and the application is not suitable for large size.
技术解决方案Technical solution
为解决上述技术问题，本发明构造了一种阵列基板的制作方法，包括以下步骤： To solve the above technical problem, the present invention constructs a method for fabricating an array substrate, comprising the following steps:
将衬底基板放入沉积腔室中，并在所述衬底基板上形成遮光层； Inserting a substrate into a deposition chamber and forming a light shielding layer on the substrate;
在所述遮光层上依次形成离子阻挡层、缓冲层；Forming an ion barrier layer and a buffer layer on the light shielding layer;
采用化学气相沉积方式在所述缓冲层上沉积非晶硅层；其中在所述沉积腔室中加入所述非晶硅层的制备原料以及含硼元素的混合原料；所述含硼元素的混合原料为乙硼烷和氢气的混合气体；所述遮光层的厚度为 300 Å ~1000 Å ；Depositing an amorphous silicon layer on the buffer layer by chemical vapor deposition; wherein a raw material for preparing the amorphous silicon layer and a mixed raw material containing boron elements are added to the deposition chamber; and the boron-containing element is mixed The raw material is a mixed gas of diborane and hydrogen; the thickness of the light shielding layer is 300 Å ~ 1000 Å ;
将所述非晶硅层转换为多晶硅层，并对所述多晶硅层进行图形化处理，其中所述图形化处理后的多晶硅层包括第一多晶硅部和第二多晶硅部；Converting the amorphous silicon layer into a polysilicon layer, and patterning the polysilicon layer, wherein the patterned polysilicon layer comprises a first polysilicon portion and a second polysilicon portion;
在所述图形化处理后的多晶硅层上形成栅绝缘层；Forming a gate insulating layer on the patterned polysilicon layer;
在所述栅绝缘层上形成第一金属层，并对所述第一金属层进行图形化处理至少形成第一栅极和第二栅极；所述第一栅极与所述第一多晶硅部对应，所述第二栅极与所述第二多晶硅部对应；Forming a first metal layer on the gate insulating layer, and patterning the first metal layer to form at least a first gate and a second gate; the first gate and the first poly Corresponding to the silicon portion, the second gate corresponds to the second polysilicon portion;
对位于第一部分两侧的所述第一多晶硅部进行 P 型离子注入处理和对位于第二部分两侧的所述第二多晶硅部进行 N 型离子注入处理；所述第一部分为所述第一多晶硅部中与所述第一栅极对应的部分；所述第二部分为所述第二多晶硅部中与所述第二栅极对应的部分；Performing the first polysilicon portion on both sides of the first portion Type ion implantation process and N to the second polysilicon portion located on both sides of the second portion a type ion implantation process; the first portion is a portion of the first polysilicon portion corresponding to the first gate; and the second portion is the second and second portions The portion corresponding to the gate;
在所述第一金属层上沉积保护层；Depositing a protective layer on the first metal layer;
在所述保护层上形成第二金属层，对所述第二金属层进行图形化处理形成至少两个源极和至少两个漏极。A second metal layer is formed on the protective layer, and the second metal layer is patterned to form at least two sources and at least two drains.
在本发明的阵列基板的制作方法中，所述乙硼烷和所述氢气的摩尔混合比为 1 ： 1000~1 ： 5000 。In the method for fabricating the array substrate of the present invention, the molar mixing ratio of the diborane to the hydrogen is 1: 1000~1: 5000.
在本发明的阵列基板的制作方法中，所述硼元素在所述混合气体中的含量为 1 × 1011~5 × 1012 atoms/cm2 。In the method of fabricating the array substrate of the present invention, the content of the boron element in the mixed gas is 1 × 10 11 to 5 × 10 12 atoms/cm 2 .
在本发明的阵列基板的制作方法中，所述将所述非晶硅层转换为多晶硅层的步骤包括：In the method for fabricating the array substrate of the present invention, the step of converting the amorphous silicon layer into a polysilicon layer comprises:
对所述非晶硅层进行高温去氢处理；以及Performing high temperature dehydrogenation treatment on the amorphous silicon layer;
对所述去氢处理后的非晶硅层进行 准分子激光退火 处理和激光照射。The demagnetized amorphous silicon layer is subjected to excimer laser annealing treatment and laser irradiation.
在本发明的阵列基板的制作方法中，对所述第二金属层进行图形化处理形成两个源极和两个漏极；所述方法还包括：In the method of fabricating the array substrate of the present invention, the second metal layer is patterned to form two sources and two drains; the method further includes:
通过光刻工艺在与每个所述源极对应的所述保护层上形成第一过孔；其中一所述源极通过所述第一过孔与所述第一多晶硅部连接，另一所述源极通过所述第一过孔与所述第二多晶硅部连接。Forming a first via hole on the protective layer corresponding to each of the source electrodes by a photolithography process; wherein the source is connected to the first polysilicon portion through the first via hole, and One of the sources is connected to the second polysilicon portion through the first via.
在本发明的阵列基板的制作方法中，所述方法还包括：在与每个所述漏极对应的所述保护层上形成第二过孔，其中一所述漏极通过所述第二过孔与所述第一多晶硅部连接；另一所述漏极通过所述第二过孔与所述第二多晶硅部连接。In the method of fabricating the array substrate of the present invention, the method further includes: forming a second via on the protective layer corresponding to each of the drains, wherein the drain passes through the second pass The hole is connected to the first polysilicon portion; the other drain is connected to the second polysilicon portion through the second via.
在本发明的阵列基板的制作方法中，所述方法还包括：In the method for fabricating the array substrate of the present invention, the method further includes:
在所述第二金属层上形成平坦层，在与每个所述漏极或者每个所述源极对应的所述平坦层上设置第三过孔。A flat layer is formed on the second metal layer, and a third via is provided on the flat layer corresponding to each of the drains or each of the sources.
在本发明的阵列基板的制作方法中，所述方法还包括：In the method for fabricating the array substrate of the present invention, the method further includes:
在所述平坦层上形成透明导电层；所述透明导电层通过所述第三过孔与所述第二金属层连接。Forming a transparent conductive layer on the flat layer; the transparent conductive layer is connected to the second metal layer through the third via.
为解决上述技术问题，本发明构造了一种阵列基板的制作方法，包括以下步骤：To solve the above technical problem, the present invention constructs a method for fabricating an array substrate, comprising the following steps:
将衬底基板放入沉积腔室中，在所述衬底基板上形成遮光层；Inserting a substrate into a deposition chamber, forming a light shielding layer on the substrate;
在所述遮光层上依次形成离子阻挡层、缓冲层；Forming an ion barrier layer and a buffer layer on the light shielding layer;
采用化学气相沉积方式在所述缓冲层上沉积非晶硅层；其中在所述沉积腔室中加入所述非晶硅层的制备原料以及含硼元素的混合原料；Depositing an amorphous silicon layer on the buffer layer by chemical vapor deposition; wherein a raw material for preparing the amorphous silicon layer and a mixed raw material containing boron element are added to the deposition chamber;
将所述非晶硅层转换为多晶硅层，并对所述多晶硅层进行图形化处理；其中所述图形化处理后的多晶硅层包括第一多晶硅部和第二多晶硅部；Converting the amorphous silicon layer into a polysilicon layer, and patterning the polysilicon layer; wherein the patterned polysilicon layer comprises a first polysilicon portion and a second polysilicon portion;
在所述图形化处理后的多晶硅层上形成栅绝缘层；Forming a gate insulating layer on the patterned polysilicon layer;
在所述栅绝缘层上形成第一金属层，并对所述第一金属层进行图形化处理至少形成第一栅极和第二栅极；所述第一栅极与所述第一多晶硅部对应，所述第二栅极与所述第二多晶硅部对应；Forming a first metal layer on the gate insulating layer, and patterning the first metal layer to form at least a first gate and a second gate; the first gate and the first poly Corresponding to the silicon portion, the second gate corresponds to the second polysilicon portion;
对位于第一部分两侧的所述第一多晶硅部进行 P 型离子注入处理和对位于第二部分两侧的所述第二多晶硅部进行 N 型离子注入处理；所述第一部分为所述第一多晶硅部中与所述第一栅极对应的部分；所述第二部分为所述第二多晶硅部中与所述第二栅极对应的部分；Performing the first polysilicon portion on both sides of the first portion Type ion implantation process and N to the second polysilicon portion located on both sides of the second portion a type ion implantation process; the first portion is a portion of the first polysilicon portion corresponding to the first gate; and the second portion is the second and second portions The portion corresponding to the gate;
在所述第一金属层上沉积保护层；Depositing a protective layer on the first metal layer;
在所述保护层上形成第二金属层，对所述第二金属层进行图形化处理形成至少两个源极和两个漏极。A second metal layer is formed on the protective layer, and the second metal layer is patterned to form at least two sources and two drains.
在本发明的阵列基板的制作方法中，所述含硼元素的混合原料为乙硼烷和氢气的混合气体。In the method of fabricating the array substrate of the present invention, the mixed material containing the boron element is a mixed gas of diborane and hydrogen.
在本发明的阵列基板的制作方法中，所述乙硼烷和所述氢气的摩尔混合比为 1 ： 1000~1 ： 5000 。In the method for fabricating the array substrate of the present invention, the molar mixing ratio of the diborane to the hydrogen is 1: 1000~1: 5000.
在本发明的阵列基板的制作方法中，所述硼元素在所述混合气体中的含量为 1 × 1011~5 × 1012 atoms/cm2 。In the method of fabricating the array substrate of the present invention, the content of the boron element in the mixed gas is 1 × 10 11 to 5 × 10 12 atoms/cm 2 .
在本发明的阵列基板的制作方法中，所述将所述非晶硅层转换为多晶硅层的步骤包括：In the method for fabricating the array substrate of the present invention, the step of converting the amorphous silicon layer into a polysilicon layer comprises:
对所述非晶硅层进行高温去氢处理；以及Performing high temperature dehydrogenation treatment on the amorphous silicon layer;
对所述去氢处理后的非晶硅层进行 准分子激光退火 处理和激光照射。The demagnetized amorphous silicon layer is subjected to excimer laser annealing treatment and laser irradiation.
在本发明的阵列基板的制作方法中，对所述第二金属层进行图形化处理形成两个源极和两个漏极；所述方法还包括：In the method of fabricating the array substrate of the present invention, the second metal layer is patterned to form two sources and two drains; the method further includes:
通过光刻工艺在与每个所述源极对应的所述保护层上形成第一过孔；其中一所述源极通过所述第一过孔与所述第一多晶硅部连接，另一所述源极通过所述第一过孔与所述第二多晶硅部连接。Forming a first via hole on the protective layer corresponding to each of the source electrodes by a photolithography process; wherein the source is connected to the first polysilicon portion through the first via hole, and One of the sources is connected to the second polysilicon portion through the first via.
在本发明的阵列基板的制作方法中，所述方法还包括：In the method for fabricating the array substrate of the present invention, the method further includes:
在与每个所述漏极对应的所述保护层上形成第二过孔，其中一所述漏极通过所述第二过孔与所述第一多晶硅部连接；另一所述漏极通过所述第二过孔与所述第二多晶硅部连接。Forming a second via hole on the protective layer corresponding to each of the drains, wherein one of the drains is connected to the first polysilicon portion through the second via hole; another one of the drains The pole is connected to the second polysilicon portion through the second via.
在本发明的阵列基板的制作方法中，所述方法还包括：In the method for fabricating the array substrate of the present invention, the method further includes:
在所述第二金属层上形成平坦层，在与每个所述漏极或者每个所述源极对应的所述平坦层上设置第三过孔。A flat layer is formed on the second metal layer, and a third via is provided on the flat layer corresponding to each of the drains or each of the sources.
在本发明的阵列基板的制作方法中，所述方法还包括：In the method for fabricating the array substrate of the present invention, the method further includes:
在所述平坦层上形成透明导电层；所述透明导电层通过所述第三过孔与所述第二金属层连接。Forming a transparent conductive layer on the flat layer; the transparent conductive layer is connected to the second metal layer through the third via.
在本发明的阵列基板的制作方法中，所述遮光层的厚度为 300 Å ~1000 Å 。In the method of fabricating the array substrate of the present invention, the thickness of the light shielding layer is 300 Å to 1000 Å.
本发明的 阵列基板的制作方法，减少了离子注入设备的使用，还可以避免高能量离子注入时对沟道处多晶硅的晶格损伤，有利于提高载流子的迁移率和薄膜晶体管的可靠性、从而降低生产成本。The invention The fabrication method of the array substrate reduces the use of the ion implantation device, and can avoid the lattice damage of the polysilicon at the channel during the high energy ion implantation, thereby improving the mobility of the carrier and the reliability of the thin film transistor, thereby reducing Cost of production.
有益效果 Beneficial effect
相对现有技术，本发明的液晶显示面板及装置，通过对现有的芯片和电子元件重新布局，从而降低生产成本，减小液晶显示面板的尺寸。Compared with the prior art, the liquid crystal display panel and device of the present invention reduces the production cost and the size of the liquid crystal display panel by rearranging the existing chips and electronic components.
附图说明DRAWINGS
图 1 为本发明阵列基板制作方法的第一步的示意图； 1 is a schematic view showing a first step of a method for fabricating an array substrate of the present invention;
图 2 为本发明阵列基板制作方法的第二步的示意图； 2 is a schematic view showing a second step of the method for fabricating an array substrate of the present invention;
图 3 为本发明阵列基板制作方法的第三步的示意图； 3 is a schematic view showing a third step of the method for fabricating the array substrate of the present invention;
图 4 为本发明阵列基板制作方法的第四步的示意图； 4 is a schematic view showing a fourth step of the method for fabricating the array substrate of the present invention;
图 5 为本发明阵列基板制作方法的第五步的示意图； 5 is a schematic view showing a fifth step of the method for fabricating an array substrate of the present invention;
图 6 为本发明阵列基板制作方法的第六步的示意图； 6 is a schematic view showing a sixth step of the method for fabricating an array substrate of the present invention;
图 7 为本发明阵列基板制作方法的第七步的示意图； 7 is a schematic view showing a seventh step of the method for fabricating an array substrate of the present invention;
图 8 为本发明阵列基板制作方法的第八步的示意图； 8 is a schematic view showing an eighth step of the method for fabricating the array substrate of the present invention;
图 9 为本发明阵列基板制作方法的第九步的示意图。 9 is a schematic view showing the ninth step of the method for fabricating the array substrate of the present invention.
图 10 为本发明阵列基板制作方法的优选方式的示意图。 FIG. 10 is a schematic view showing a preferred mode of the method for fabricating the array substrate of the present invention.
本发明的最佳实施方式BEST MODE FOR CARRYING OUT THE INVENTION
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。The following description of the various embodiments is provided to illustrate the specific embodiments of the invention. The directional terms mentioned in the present invention, such as "upper", "lower", "before", "after", "left", "right", "inside", "outside", "side", etc., are merely references. Attach the direction of the drawing. Therefore, the directional terminology used is for the purpose of illustration and understanding of the invention. In the figures, structurally similar elements are denoted by the same reference numerals.
本发明的阵列基板如图 9 所示，其衬底基板 111 、遮光层 112 、离子阻挡层 113 、缓冲层 114 、多晶硅层 116 、栅绝缘层 117 、第一金属层 118 、保护层 121 、第二金属层、还可包括平坦层和透明导电层（图中未示出）；The array substrate of the present invention is as shown in FIG. 9, and its base substrate 111, light shielding layer 112, ion barrier layer 113, buffer layer 114, a polysilicon layer 116, a gate insulating layer 117, a first metal layer 118, a protective layer 121, a second metal layer, may further include a flat layer and a transparent conductive layer (not shown);
所述遮光层 112 位于所述衬底基板 111 上；所述离子阻挡层 113 位于所述遮光层 112 上；所述缓冲层 114 位于所述离子阻挡层 113 上；所述多晶硅层 116 位于所述缓冲层 114 上，是通过对非晶硅层转换形成的，其中所述非晶硅层的制备原料中掺杂有含硼元素的混合原料；所述栅绝缘层 117 位于所述多晶硅层上；所述第一金属层 118 位于所述栅绝缘层 117 上，所述第一金属层 118 包括两个薄膜晶体管的栅极区；所述保护层 121 位于所述第一金属层 118 上；所述第二金属层位于所述保护层 121 上，所述第二金属层包括两个薄膜晶体管的漏极区和源极区；The light shielding layer 112 is located on the base substrate 111; the ion barrier layer 113 is located on the light shielding layer 112 The buffer layer 114 is located on the ion blocking layer 113; the polysilicon layer 116 is located at the buffer layer 114 Formed by converting an amorphous silicon layer, wherein the raw material of the amorphous silicon layer is doped with a mixed raw material containing a boron element; the gate insulating layer 117 is located on the polysilicon layer; a metal layer 118 Located on the gate insulating layer 117, the first metal layer 118 includes gate regions of two thin film transistors; the protective layer 121 is located at the first metal layer 118 The second metal layer is disposed on the protective layer 121, and the second metal layer includes a drain region and a source region of the two thin film transistors;
所述平坦层位于所述第二金属层上，在与每个所述漏极或者每个所述源极对应的所述平坦层上设置第三过孔；所述透明导电层位于所述平坦层上；所述透明导电层通过所述第三过孔与所述第二金属层连接，即与所述源极或者漏极连接。所述透明导电层可包括像素电极。The flat layer is located on the second metal layer, and a third via is disposed on the flat layer corresponding to each of the drains or each of the sources; the transparent conductive layer is located at the flat The transparent conductive layer is connected to the second metal layer through the third via, that is, to the source or the drain. The transparent conductive layer may include a pixel electrode.
结合图 1-10 ，上述阵列基板的制作方法包括： Referring to FIG. 1-10, the manufacturing method of the above array substrate includes:
S101 、将衬底基板放入沉积腔室中，并在所述衬底基板 111 上形成遮光层 112 ； S101, the substrate is placed in a deposition chamber, and a light shielding layer 112 is formed on the substrate 111;
在进行 S101 之前，先将衬底基板 111 放入沉积腔室中，如图 1 所示，所述遮光层 112 具体采用镀膜，光刻（光阻涂布，曝光，显影，蚀刻，光阻剥离）的工艺得到的；所述遮光层 112 层的材料可以为不透光的金属层，譬如 Mo ， Al ， Ti 等，也可以为可吸收光的材料，譬如非晶硅层。Before performing S101, the base substrate 111 is placed in a deposition chamber, as shown in FIG. 1, the light shielding layer 112. Specifically, it is obtained by a process of coating, photolithography (photoresist coating, exposure, development, etching, photoresist stripping); the material of the light shielding layer 112 may be an opaque metal layer, such as Mo, Al, Ti Alternatively, it may be a material that absorbs light, such as an amorphous silicon layer.
优选地，所述遮光层 112 的厚度为 300 Å ~1000 Å ，从而减少从背光模组射来的光线对阵列基板多晶硅层的照射而产生的光漏电流。Preferably, the light shielding layer 112 has a thickness of 300 Å to 1000 Å. Therefore, the light leakage current generated by the illumination of the array substrate polysilicon layer by the light emitted from the backlight module is reduced.
S102 、在所述遮光层 112 上依次形成离子阻挡层 113 、缓冲层 114 ；S102, forming an ion barrier layer 113 and a buffer layer 114 on the light shielding layer 112 in sequence;
如图 2 所示，所述离子阻挡层 113 的材料为氮化硅 SiNx ，其作用避免所述衬底基板 111 中的钠、钾等离子在后续的高温工艺中扩散到多晶硅层中。由于这些钠、钾等离子会在多硅层半导体的电子能级中形成深层缺陷，从而导致 TFT 器件导通电流减少，漏电流增加，最终影响显示的效果和可靠性。As shown in FIG. 2, the material of the ion barrier layer 113 is silicon nitride SiNx, which acts to avoid the substrate 111. The sodium and potassium ions in the diffusion diffuse into the polysilicon layer in a subsequent high temperature process. Since these sodium and potassium ions form deep defects in the electronic energy levels of the polysilicon semiconductor, resulting in TFT The on-current of the device is reduced, and the leakage current is increased, which ultimately affects the display effect and reliability.
所述缓冲层 114 的材料可为 SiO2 ，由于离子阻挡层 113 与后续的非晶硅薄膜的热膨胀系数比较接近，容易产生比较集中的异质结应力，从而会产生界面缺陷。所述缓冲层能够防止异质结应力集中，以减小界面缺陷。The material of the buffer layer 114 may be SiO 2 . Since the thermal expansion coefficients of the ion barrier layer 113 and the subsequent amorphous silicon film are relatively close, a relatively concentrated heterojunction stress is easily generated, thereby causing interface defects. The buffer layer can prevent concentration of heterojunction stress to reduce interface defects.
S103 、采用化学气相沉积方式在所述缓冲层 114 上沉积非晶硅层 115 ；S103, depositing an amorphous silicon layer 115 on the buffer layer 114 by chemical vapor deposition;
如图 3 所示，其中在所述沉积腔室中加入所述非晶硅层的制备原料以及含硼元素的混合原料；As shown in FIG. 3, a preparation raw material of the amorphous silicon layer and a mixed raw material containing a boron element are added to the deposition chamber;
优选为等离子体辅助化学气相沉积方法，具体在等离子体辅助化学气相沉积 (PECVD) 的腔室中加入 SiH4 与 H2 的混合气体，使 SiH4 与 H2 在等离子体的状态下其发生化学反应，生成氢化非晶硅薄膜。本发明在等离子体辅助化学气相沉积 (PECVD) 的腔室中还通入 B2H6 和 H2 的混合气体。通过在制备原料掺杂含硼元素的混合原料，能够使 N 型多晶硅薄膜晶体管与 P 型多晶硅薄膜晶体管的阈值电压以零点位对称。Preferably a plasma assisted chemical vapor deposition processes, particularly with the addition of a mixed gas of SiH 4 H 2 in a plasma assisted chemical vapor deposition (PECVD) chambers, SiH 4 gas and H 2 in the state in which the plasma chemical The reaction produces a hydrogenated amorphous silicon film. The present invention also introduces a mixed gas of B 2 H 6 and H 2 in a chamber of plasma-assisted chemical vapor deposition (PECVD). The threshold voltage of the N-type polysilicon thin film transistor and the P-type polysilicon thin film transistor can be made symmetrical with respect to the zero point by doping the mixed raw material containing the boron element in the preparation raw material.
由于采用预先配置好的 B2H6 和 H2 的混合气体，一方面稀释了 B2H6 气体，使制程时气体的流量可以通入的量比较大，便于精准地控制流量和均匀性，另一方面，由于 B2H6 气体为易燃易爆剧毒的危险气体，让其与 H2 预先混合，可以增加 B2H6 气体运输的安全性。Due to the pre-configured mixture of B 2 H 6 and H 2 , the B 2 H 6 gas is diluted on the one hand, so that the flow rate of the gas during the process can be relatively large, so that the flow rate and uniformity can be accurately controlled. On the other hand, since B2H6 gas is a dangerous gas that is highly flammable, explosive and highly toxic, it is premixed with H 2 to increase the safety of B 2 H 6 gas transportation.
优选地，所述 B2H6 和 H2 气的摩尔混合比为 1 ： 1000~1 ： 5000 ；Preferably, the molar mixing ratio of the B 2 H 6 and H 2 gas is 1:1000~1:5000;
设定制程腔内的温度为 200 ℃ -350 ℃，其中 SiH4 气体的流量为 5000~17000sccm ， H2 气体的流量为 1000~60000sccm 以及 B2H6 和 H2 的混合气体的流量为 10~500sccm 。因硼元素的掺杂量非常少，若采用纯 B2H6 气体，根据计算 B2H6 的流量为 0sccm~1sccm 之间， B2H6 的气体流量非常小，不容易精准地控制掺杂量和掺杂的均匀性，导致制程稳定性差，达不到大规模量产对制程可重复性和稳定性的要求。Set the temperature in the process chamber to 200 °C -350 °C, where the flow rate of SiH 4 gas is 5000~17000sccm, the flow rate of H 2 gas is 1000~60000sccm, and the flow rate of mixed gas of B 2 H 6 and H 2 is 10~ 500sccm. Since the doping amount of boron element is very small, if pure B2H6 gas is used, according to the calculation of the flow rate of B2H6 between 0 sccm and 1 sccm, the gas flow rate of B 2 H 6 is very small, and it is not easy to accurately control the doping amount and doping. Uniformity results in poor process stability and does not meet the requirements for process repeatability and stability in mass production.
因此，在本专利中，采用预先混合好的 B2H6 和 H2 的混合气体， B2H6 和 H2 气的摩尔混合比为 1 ： 1000~1 ： 5000 。通过这样的混合比使得 B2H6 和 H2 的混合气体的流量就会增加。Therefore, in this patent, a premixed mixture of B 2 H 6 and H 2 is used, and the molar mixing ratio of B 2 H 6 and H 2 gas is 1:1000 to 1:5000. By such a mixing ratio, the flow rate of the mixed gas of B 2 H 6 and H 2 is increased.
优选地，所述硼元素在所述混合气体中的含量为 1 × 1011~5 × 1012 atoms/cm2 。Preferably, the content of the boron element in the mixed gas is 1 × 10 11 to 5 × 10 12 atoms/cm 2 .
S104 、将所述非晶硅层 115 转换为多晶硅层 116 ，并对所述多晶硅层进行图形化处理；S104, converting the amorphous silicon layer 115 into a polysilicon layer 116, and patterning the polysilicon layer;
如图 4 所示， S104 具体包括：As shown in Figure 4, S104 specifically includes:
S201 、先对所述非晶硅层 115 进行高温去氢处理；S201, first performing high temperature dehydrogenation treatment on the amorphous silicon layer 115;
S202 、对所述去氢处理后的非晶硅层进行 准分子激光退火 （ ELA ）处理、以及激光照射后，使得所述非晶硅层 115 转变成整层多晶硅层。S202, performing excimer laser annealing on the dehydrogenated amorphous silicon layer (ELA) After the treatment, and after the laser irradiation, the amorphous silicon layer 115 is turned into an entire polysilicon layer.
S203 、然后采用光刻 ( 光阻涂布，曝光，显影，蚀刻，光阻剥离 ) 的工艺对整层多晶硅层进行图案化处理，得到图案化处理后的多晶硅层，其中所述图形化处理后的多晶硅层包括第一多晶硅部和第二多晶硅部，如图 4 中 116 所示的两个梯形区域。所述多晶硅部的个数不限于图中所示的个数，也可以为两个以上。S203, followed by photolithography (photoresist coating, exposure, development, etching, photoresist stripping) The process of patterning the entire polysilicon layer to obtain a patterned polysilicon layer, wherein the patterned polysilicon layer comprises a first polysilicon portion and a second polysilicon portion, as shown in FIG. 116 Two trapezoidal areas as shown. The number of the polycrystalline silicon portions is not limited to the number shown in the drawing, and may be two or more.
S105 、在所述图案化处理后的多晶硅层 116 上形成栅绝缘层 117 ；S105, forming a gate insulating layer 117 on the patterned polysilicon layer 116;
如图 5 所示，在步骤 S104 之后，通过采用等离子体辅助化学气相沉积 (PECVD) 的方式，在所述多晶硅层 116 上制备所述栅绝缘层 117 。所述栅绝缘层 117 的材料为氮化硅。As shown in Figure 5, after step S104, by plasma assisted chemical vapor deposition (PECVD) The gate insulating layer 117 is formed on the polysilicon layer 116. The material of the gate insulating layer 117 is silicon nitride.
S106 、在所述栅绝缘层上形成第一金属层，并对所述第一金属层进行图形化处理至少形成第一栅极和第二栅极；S106 Forming a first metal layer on the gate insulating layer, and patterning the first metal layer to form at least a first gate and a second gate;
所述第一栅极与所述第一多晶硅部对应，所述第二栅极与所述第二多晶硅部对应；如图 6 所示，在步骤 S105 之后，在所述栅绝缘层 117 层上制作第一金属层，第一金属层可采用 Mo 、 Mo/Al/Mo 、 Ti 、 Ti/Mo 等单层金属或者金属复合层；并对所述第一金属层进行图形化处理（即光刻工艺）形成两个栅极 118 ；The first gate corresponds to the first polysilicon portion, and the second gate corresponds to the second polysilicon portion; as shown in FIG. 6, in the step After S105, a first metal layer is formed on the gate insulating layer 117, and the first metal layer may be Mo, Mo/Al/Mo, Ti, Ti/Mo. a single layer of metal or metal composite layer; and the first metal layer is patterned (ie, photolithography process) to form two gates 118;
S107 、对位于第一部分两侧的所述第一多晶硅部进行 P 型离子注入处理和对位于第二部分两侧的所述第二多晶硅部进行 N 型离子注入处理；所述第一部分为所述第一多晶硅部中与所述第一栅极对应的部分；所述第二部分为所述第二多晶硅部中与所述第二栅极对应的部分；S107, performing the first polysilicon portion on both sides of the first portion Type ion implantation process and N to the second polysilicon portion located on both sides of the second portion a type ion implantation process; the first portion is a portion of the first polysilicon portion corresponding to the first gate; and the second portion is the second and second portions The portion corresponding to the gate;
如图 7 所示，第一多晶硅部（左侧的多晶硅层），先将第一多晶硅部（右侧的多晶硅层）用光阻遮挡，只露出左侧的多晶硅层，对左侧的位于所述第一部分两侧的多晶硅层区域，采用离子注入的方法对该部分区域掺杂硼元素，硼元素的掺杂浓度为 1 × 1015 atoms/cm2~5 × 1015 atoms/cm2 ，形成硼元素的掺杂的多晶硅区 119 ，即 P-MOS TFT 的欧姆接触区；As shown in FIG. 7, the first polysilicon portion (the polysilicon layer on the left side) first blocks the first polysilicon portion (the polysilicon layer on the right side) with a photoresist, and only exposes the polysilicon layer on the left side, to the left. The side of the polysilicon layer on both sides of the first portion is doped with boron by ion implantation. The doping concentration of boron is 1 × 10 15 atoms / cm 2 ~ 5 × 10 15 atoms / Cm 2 , a doped polysilicon region 119 forming boron element, ie an ohmic contact region of the P-MOS TFT;
再将左侧的多晶硅层用光阻遮挡，只露出右侧的多晶硅层，采用离子注入的方法，对右侧的位于所述第一部分两侧的多晶硅层区域进行磷元素的掺杂，掺杂浓度为 1 × 1015 atoms/cm2~5 × 1015 atoms/cm2 ，形成磷元素的掺杂的多晶硅区 120 ，即 N-MOS TFT 的欧姆接触区。Then, the polysilicon layer on the left side is shielded by the photoresist, and only the polysilicon layer on the right side is exposed, and the polysilicon layer region on the right side of the first portion is doped by the ion implantation method. The concentration is 1 × 10 15 atoms/cm 2 to 5 × 10 15 atoms/cm 2 , and a doped polysilicon region 120 of a phosphorus element, that is, an ohmic contact region of the N-MOS TFT is formed.
S109 、在所述第一金属层上沉积保护层；S109, depositing a protective layer on the first metal layer;
在步骤 S108 之后，进行保护层 121 层的制作，如图 8 所示，采用等离子体辅助化学气相沉积 (PECVD) 的方式，在所述第一金属层上制作保护层 121 。After step S108, the fabrication of the protective layer 121 layer is performed, as shown in Fig. 8, using plasma-assisted chemical vapor deposition. In a manner of (PECVD), a protective layer 121 is formed on the first metal layer.
S110 、在所述保护层上形成第二金属层，对所述第二金属层进行图形化处理形成至少两个源极和至少两个漏极；S110 Forming a second metal layer on the protective layer, and patterning the second metal layer to form at least two sources and at least two drains;
在步骤 S108 之后，如图 9 所示，在所述保护层 121 上采用镀膜的方式形成第二金属层，并对所述第二金属层进行图形化处理（即光刻工艺）后，形成两个源极 21 和两个漏极 22 。After step S108, as shown in FIG. 9, at the protective layer 121 A second metal layer is formed by coating, and after the second metal layer is patterned (ie, a photolithography process), two source electrodes 21 and two drain electrodes 22 are formed.
优选地，所述方法还包括：Preferably, the method further includes:
S111 、通过光刻工艺在与每个所述源极对应的所述保护层上形成第一过孔；S111, forming a first via hole on the protective layer corresponding to each of the source electrodes by a photolithography process;
其中一所述源极 21 通过所述第一过孔（图中未示出）与所述第一多晶硅部连接，另一所述源极 21 通过所述第一过孔与所述第二多晶硅部连接。One of the source electrodes 21 is connected to the first polysilicon portion through the first via hole (not shown), and the other source electrode 21 Connecting to the second polysilicon portion through the first via.
S112 、在与每个所述漏极对应的所述保护层上形成第二过孔，S112, forming a second via hole on the protective layer corresponding to each of the drains,
其中一所述漏极 22 通过所述第二过孔（图中未示出）与所述第一多晶硅部连接；另一所述漏极 22 通过所述第二过孔与所述第二多晶硅部连接。One of the drains 22 is connected to the first polysilicon portion through the second via (not shown); the other of the drains 22 Connecting to the second polysilicon portion through the second via.
S113 、在所述第二金属层上制作平坦层，在与每个所述漏极或者每个所述源极对应的所述平坦层上设置第三过孔；S113 Forming a flat layer on the second metal layer, and providing a third via hole on the flat layer corresponding to each of the drains or each of the source electrodes;
S114 、在所述平坦层上形成透明导电层；所述透明导电层通过所述第三过孔与所述第二金属层连接。所述透明导电层包括像素电极。S114 Forming a transparent conductive layer on the flat layer; the transparent conductive layer is connected to the second metal layer through the third via. The transparent conductive layer includes a pixel electrode.
优选地，如图 10 所示，为了改善 N-MOS TFT 欧姆接触区的热电子效应，在所述图形化处理后的多晶硅层中，还设置有轻掺杂区域 122 ，所述轻掺杂区域 122 可采用离子注入的方法制作。Preferably, as shown in FIG. 10, in order to improve the N-MOS TFT The thermoelectron effect of the ohmic contact region is further provided with a lightly doped region 122 in the patterned polysilicon layer, and the lightly doped region 122 can be fabricated by ion implantation.
由于现有技术是在形成多晶硅层后，采用离子注入到的方式将硼离子掺杂到多晶硅层中的，容易对多晶硅的晶格损伤，而本发明在进行非晶硅层的薄膜沉积时，就进行硼元素的掺杂，以使 N 型多晶硅薄膜晶体管与 P 型多晶硅薄膜晶体管的阈值电压以零点位对称；从而节省了一次离子注入制程，可以减少离子注入设备的使用；本发明还可以避免离子注入对沟道处多晶硅晶格损伤，提高多晶硅薄膜晶体管的载流子迁移率和元件可靠性。Since the prior art is to dope the boron ions into the polysilicon layer by ion implantation after the polysilicon layer is formed, the lattice damage of the polysilicon is easily caused, and the present invention performs the film deposition of the amorphous silicon layer. Doping the boron element so that N-type polysilicon thin film transistor and P The threshold voltage of the polysilicon thin film transistor is symmetric at zero point; thereby saving one ion implantation process and reducing the use of the ion implantation apparatus; the invention can also avoid the ion implantation damage to the polycrystalline silicon lattice at the channel, and improve the loading of the polysilicon thin film transistor. Mobility and component reliability.
本发明的 阵列基板及其制作方法，减少了离子注入设备的使用，还可以避免高能量离子注入时对沟道处多晶硅的晶格损伤，有利于提高载流子的迁移率和薄膜晶体管的可靠性、从而降低生产成本。The invention The array substrate and the manufacturing method thereof reduce the use of the ion implantation device, and can avoid the lattice damage of the polysilicon at the channel during the high energy ion implantation, thereby improving the mobility of the carrier and the reliability of the thin film transistor, thereby reduce manufacturing cost.
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。In the above, the present invention has been disclosed in the above preferred embodiments, but the preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various modifications without departing from the spirit and scope of the invention. The invention is modified and retouched, and the scope of the invention is defined by the scope defined by the claims.

Claims (18)

  1. 一种阵列基板的制作方法，其包括：A method for fabricating an array substrate, comprising:
    将衬底基板放入沉积腔室中，并在所述衬底基板上形成遮光层；Inserting a substrate into a deposition chamber and forming a light shielding layer on the substrate;
    在所述遮光层上依次形成离子阻挡层、缓冲层；Forming an ion barrier layer and a buffer layer on the light shielding layer;
    采用化学气相沉积方式在所述缓冲层上沉积非晶硅层；其中在所述沉积腔室中加入所述非晶硅层的制备原料以及含硼元素的混合原料；所述含硼元素的混合原料为乙硼烷和氢气的混合气体；所述遮光层的厚度为 300 Å ~1000 Å ；Depositing an amorphous silicon layer on the buffer layer by chemical vapor deposition; wherein a raw material for preparing the amorphous silicon layer and a mixed raw material containing boron elements are added to the deposition chamber; and the boron-containing element is mixed The raw material is a mixed gas of diborane and hydrogen; the thickness of the light shielding layer is 300 Å ~ 1000 Å ;
    将所述非晶硅层转换为多晶硅层，并对所述多晶硅层进行图形化处理，其中所述图形化处理后的多晶硅层包括第一多晶硅部和第二多晶硅部；Converting the amorphous silicon layer into a polysilicon layer, and patterning the polysilicon layer, wherein the patterned polysilicon layer comprises a first polysilicon portion and a second polysilicon portion;
    在所述图形化处理后的多晶硅层上形成栅绝缘层；Forming a gate insulating layer on the patterned polysilicon layer;
    在所述栅绝缘层上形成第一金属层，并对所述第一金属层进行图形化处理至少形成第一栅极和第二栅极；所述第一栅极与所述第一多晶硅部对应，所述第二栅极与所述第二多晶硅部对应；Forming a first metal layer on the gate insulating layer, and patterning the first metal layer to form at least a first gate and a second gate; the first gate and the first poly Corresponding to the silicon portion, the second gate corresponds to the second polysilicon portion;
    对位于第一部分两侧的所述第一多晶硅部进行 P 型离子注入处理和对位于第二部分两侧的所述第二多晶硅部进行 N 型离子注入处理；所述第一部分为所述第一多晶硅部中与所述第一栅极对应的部分；所述第二部分为所述第二多晶硅部中与所述第二栅极对应的部分；Performing a P-type ion implantation process on the first polysilicon portion on both sides of the first portion and performing a N-type polysilicon portion on both sides of the second portion a type ion implantation process; the first portion is a portion of the first polysilicon portion corresponding to the first gate; and the second portion is the second and second portions The portion corresponding to the gate;
    在所述第一金属层上沉积保护层； 以及Depositing a protective layer on the first metal layer;
    在所述保护层上形成第二金属层，对所述第二金属层进行图形化处理形成至少两个源极和至少两个漏极。A second metal layer is formed on the protective layer, and the second metal layer is patterned to form at least two sources and at least two drains.
  2. 根据权利要求 1 所述的阵列基板的制作方法，其中The method of fabricating an array substrate according to claim 1, wherein
    所述乙硼烷和所述氢气的摩尔混合比为 1 ： 1000~1 ： 5000 。The molar mixing ratio of the diborane to the hydrogen is 1:1000~1:5000.
  3. 根据权利要求 1 所述的阵列基板的制作方法，其中所述硼元素在所述混合气体中的含量为 1 × 1011~5 × 1012 atoms/cm2 。The method of fabricating an array substrate according to claim 1, wherein a content of the boron element in the mixed gas is 1 × 10 11 to 5 × 10 12 atoms/cm 2 .
  4. 根据权利要求 1 所述的阵列基板的制作方法，其中所述将所述非晶硅层转换为多晶硅层的步骤包括：The method of fabricating an array substrate according to claim 1, wherein the converting the amorphous silicon layer into a polysilicon layer comprises:
    对所述非晶硅层进行高温去氢处理；以及Performing high temperature dehydrogenation treatment on the amorphous silicon layer;
    对所述去氢处理后的非晶硅层进行 准分子激光退火 处理和激光照射。The demagnetized amorphous silicon layer is subjected to excimer laser annealing treatment and laser irradiation.
  5. 根据权利要求 1 所述的阵列基板的制作方法，其中对所述第二金属层进行图形化处理形成两个源极和两个漏极；所述方法还包括：According to claim 1 The method for fabricating an array substrate, wherein the second metal layer is patterned to form two sources and two drains; the method further includes:
    通过光刻工艺在与每个所述源极对应的所述保护层上形成第一过孔；其中一所述源极通过所述第一过孔与所述第一多晶硅部连接，另一所述源极通过所述第一过孔与所述第二多晶硅部连接。Forming a first via hole on the protective layer corresponding to each of the source electrodes by a photolithography process; wherein the source is connected to the first polysilicon portion through the first via hole, and One of the sources is connected to the second polysilicon portion through the first via.
  6. 根据权利要求 5 所述的阵列基板的制作方法，其中所述方法还包括：在与每个所述漏极对应的所述保护层上形成第二过孔，其中一所述漏极通过所述第二过孔与所述第一多晶硅部连接；另一所述漏极通过所述第二过孔与所述第二多晶硅部连接。According to claim 5 The method of fabricating an array substrate, wherein the method further comprises: forming a second via hole on the protective layer corresponding to each of the drains, wherein one of the drains passes through the second via hole Connected to the first polysilicon portion; the other drain is connected to the second polysilicon portion through the second via.
  7. 根据权利要求 1 所述的阵列基板的制作方法，其中所述方法还包括：The method of fabricating an array substrate according to claim 1, wherein the method further comprises:
    在所述第二金属层上形成平坦层，在与每个所述漏极或者每个所述源极对应的所述平坦层上设置第三过孔。A flat layer is formed on the second metal layer, and a third via is provided on the flat layer corresponding to each of the drains or each of the sources.
  8. 根据权利要求 1 所述的阵列基板的制作方法，其中所述方法还包括：The method of fabricating an array substrate according to claim 1, wherein the method further comprises:
    在所述平坦层上形成透明导电层；所述透明导电层通过所述第三过孔与所述第二金属层连接。Forming a transparent conductive layer on the flat layer; the transparent conductive layer is connected to the second metal layer through the third via.
  9. 一种阵列基板的制作方法，其包括： A method for fabricating an array substrate, comprising:
    将衬底基板放入沉积腔室中，并在所述衬底基板上形成遮光层；Inserting a substrate into a deposition chamber and forming a light shielding layer on the substrate;
    在所述遮光层上依次形成离子阻挡层、缓冲层；Forming an ion barrier layer and a buffer layer on the light shielding layer;
    采用化学气相沉积方式在所述缓冲层上沉积非晶硅层；其中在所述沉积腔室中加入所述非晶硅层的制备原料以及含硼元素的混合原料；Depositing an amorphous silicon layer on the buffer layer by chemical vapor deposition; wherein a raw material for preparing the amorphous silicon layer and a mixed raw material containing boron element are added to the deposition chamber;
    将所述非晶硅层转换为多晶硅层，并对所述多晶硅层进行图形化处理，其中所述图形化处理后的多晶硅层包括第一多晶硅部和第二多晶硅部；Converting the amorphous silicon layer into a polysilicon layer, and patterning the polysilicon layer, wherein the patterned polysilicon layer comprises a first polysilicon portion and a second polysilicon portion;
    在所述图形化处理后的多晶硅层上形成栅绝缘层；Forming a gate insulating layer on the patterned polysilicon layer;
    在所述栅绝缘层上形成第一金属层，并对所述第一金属层进行图形化处理至少形成第一栅极和第二栅极；所述第一栅极与所述第一多晶硅部对应，所述第二栅极与所述第二多晶硅部对应；Forming a first metal layer on the gate insulating layer, and patterning the first metal layer to form at least a first gate and a second gate; the first gate and the first poly Corresponding to the silicon portion, the second gate corresponds to the second polysilicon portion;
    对位于第一部分两侧的所述第一多晶硅部进行 P 型离子注入处理和对位于第二部分两侧的所述第二多晶硅部进行 N 型离子注入处理；所述第一部分为所述第一多晶硅部中与所述第一栅极对应的部分；所述第二部分为所述第二多晶硅部中与所述第二栅极对应的部分；Performing a P-type ion implantation process on the first polysilicon portion on both sides of the first portion and performing a N-type polysilicon portion on both sides of the second portion a type ion implantation process; the first portion is a portion of the first polysilicon portion corresponding to the first gate; and the second portion is the second and second portions The portion corresponding to the gate;
    在所述第一金属层上沉积保护层；以及Depositing a protective layer on the first metal layer;
    在所述保护层上形成第二金属层，对所述第二金属层进行图形化处理形成至少两个源极和至少两个漏极。A second metal layer is formed on the protective layer, and the second metal layer is patterned to form at least two sources and at least two drains.
  10. 根据权利要求 9 所述的阵列基板的制作方法，其中The method of fabricating an array substrate according to claim 9, wherein
    所述含硼元素的混合原料为乙硼烷和氢气的混合气体。The mixed raw material of the boron-containing element is a mixed gas of diborane and hydrogen.
  11. 根据权利要求 10 所述的阵列基板的制作方法，其中The method of fabricating an array substrate according to claim 10, wherein
    所述乙硼烷和所述氢气的摩尔混合比为 1 ： 1000~1 ： 5000 。The molar mixing ratio of the diborane to the hydrogen is 1:1000~1:5000.
  12. 根据权利要求 10 所述的阵列基板的制作方法，其中所述硼元素在所述混合气体中的含量为 1 × 1011~5 × 1012 atoms/cm2 。The method of fabricating an array substrate according to claim 10, wherein a content of said boron element in said mixed gas is 1 × 10 11 to 5 × 10 12 atoms/cm 2 .
  13. 根据权利要求 9 所述的阵列基板的制作方法，其中所述将所述非晶硅层转换为多晶硅层的步骤包括：The method of fabricating an array substrate according to claim 9, wherein the converting the amorphous silicon layer into a polysilicon layer comprises:
    对所述非晶硅层进行高温去氢处理；以及Performing high temperature dehydrogenation treatment on the amorphous silicon layer;
    对所述去氢处理后的非晶硅层进行 准分子激光退火 处理和激光照射。The demagnetized amorphous silicon layer is subjected to excimer laser annealing treatment and laser irradiation.
  14. 根据权利要求 9 所述的阵列基板的制作方法，其中对所述第二金属层进行图形化处理形成两个源极和两个漏极；所述方法还包括：According to claim 9 The method for fabricating an array substrate, wherein the second metal layer is patterned to form two sources and two drains; the method further includes:
    通过光刻工艺在与每个所述源极对应的所述保护层上形成第一过孔；其中一所述源极通过所述第一过孔与所述第一多晶硅部连接，另一所述源极通过所述第一过孔与所述第二多晶硅部连接。Forming a first via hole on the protective layer corresponding to each of the source electrodes by a photolithography process; wherein the source is connected to the first polysilicon portion through the first via hole, and One of the sources is connected to the second polysilicon portion through the first via.
  15. 根据权利要求 14 所述的阵列基板的制作方法，其中所述方法还包括：在与每个所述漏极对应的所述保护层上形成第二过孔，其中一所述漏极通过所述第二过孔与所述第一多晶硅部连接；另一所述漏极通过所述第二过孔与所述第二多晶硅部连接。According to claim 14 The method of fabricating an array substrate, wherein the method further comprises: forming a second via hole on the protective layer corresponding to each of the drains, wherein one of the drains passes through the second via hole Connected to the first polysilicon portion; the other drain is connected to the second polysilicon portion through the second via.
  16. 根据权利要求 9 所述的阵列基板的制作方法，其中所述方法还包括：The method of fabricating an array substrate according to claim 9, wherein the method further comprises:
    在所述第二金属层上形成平坦层，在与每个所述漏极或者每个所述源极对应的所述平坦层上设置第三过孔。A flat layer is formed on the second metal layer, and a third via is provided on the flat layer corresponding to each of the drains or each of the sources.
  17. 根据权利要求 9 所述的阵列基板的制作方法，其中所述方法还包括：The method of fabricating an array substrate according to claim 9, wherein the method further comprises:
    在所述平坦层上形成透明导电层；所述透明导电层通过所述第三过孔与所述第二金属层连接。Forming a transparent conductive layer on the flat layer; the transparent conductive layer is connected to the second metal layer through the third via.
  18. 根据权利要求 9 所述的阵列基板的制作方法，其中所述遮光层的厚度为 300 Å ~1000 Å 。The method of fabricating an array substrate according to claim 9, wherein the thickness of the light shielding layer is 300 Å to 1000 Å .
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