WO2017008503A1

WO2017008503A1 - Gan hemt bias circuit

Info

Publication number: WO2017008503A1
Application number: PCT/CN2016/073509
Authority: WO
Inventors: 谢路平; 李娣; 林锡贵; 刘江涛
Original assignee: 京信通信系统（中国）有限公司
Priority date: 2015-07-15
Filing date: 2016-02-04
Publication date: 2017-01-19
Also published as: CN105048969B; CN105048969A

Abstract

A GaN HEMT bias circuit, comprising a first earthed capacitor group (A11), a first transformer (A12), a second transformer (A13), a drain voltage switch (A14) and a gate generation control circuit (A15). The first earthed capacitor group (A11), an input end of the first transformer (A12) and a first input end of the drain voltage switch (A14) are connected to an external voltage input end. An input end of the second transformer (A13) and a first input end of the gate generation control circuit (A15) are connected to an output end of the first transformer (A12). An output end of the second transformer (A13) is connected to a second input end of the gate generation control circuit (A15). An output end of the drain voltage switch (A14) is connected a GaN HEMT drain and a third input end of the gate generation control circuit (A15). A second input end of the drain voltage switch (A14) is connected to a first output end of the gate generation control circuit (A15). A second output end and a fourth input end of the gate generation control circuit (A15) is connected to the GaN HEMT gate. The bias circuit realizes automatic power-up and power-down in a GaN HEMT circuit, preventing the GaN HEMT being burned out by a large current, thereby ensuring normal operation of a wireless communications apparatus using the GaN HEMT.

Description

GaN HEMT bias circuit

Technical field

The present invention relates to the field of electronic technology, and more particularly to a GaN HEMT bias circuit.

Background technique

In recent years, the global wireless communication industry has developed rapidly. According to Cisco's forecast, the annual growth rate of mobile data throughput in 2013-2018 is more than 60%. By 2018, mobile data throughput will reach 16 Exabytes/month. The performance of traditional silicon-based devices is no longer sufficient. Wireless communication devices must use GaN HEMTs (GaN High Electron Tobility Transistors) to support huge data throughput requirements.

Although GaN HEMTs have the advantages of high power density, high operating frequency, low noise, high efficiency, and high linearity. However, the use of GaN HEMTs still meets certain conditions and has some disadvantages.

First, the pinch-off voltage of the GaN HEMT is a negative voltage. The upper and lower power must meet the following timing requirements. Otherwise, the GaN HEMT will be burnt by a large current, which may cause the wireless communication device using the GaN HEMT to fail.

Power-on sequence:

1) The gate voltage is controlled below the pinch-off voltage;

2) Performing a leakage pressure bias;

3) After the leakage voltage is stabilized, adjust the gate voltage to the required gate voltage value.

Power down sequence:

1) Adjust the gate voltage to below the pinch-off voltage;

2) Disconnect the leakage pressure until the leakage pressure is zero;

3) Break the grid voltage.

Secondly, the gate of the GaN HEMT is a Schottky contact. As the input power or temperature changes, the gate current will change in magnitude and positive and negative polarity, which will affect the stability of the gate voltage.

Finally, other powers such as GaN HEMT and LDMOS (laterally diffused metal oxide semiconductor) Like the amplifying tube, the pinch-off voltage changes with temperature, causing the static operating point to drift.

Summary of the invention

Based on this, it is necessary to provide a gallium nitride high electron mobility electron transistor GaN HEMT bias circuit for the problem that the upper and lower power of the GaN HEMT cannot be automatically realized.

The technical solution of the present invention includes:

A GaN high electron mobility GaN HEMT bias circuit includes: a first ground capacitor group, a first transformer, a second transformer, a drain voltage switch, and a gate voltage generation and control circuit, wherein the first a grounding capacitor group, an input end of the first transformer, a first input end of the drain switch, and an external voltage input terminal, an input end of the second transformer, and a first gate voltage generating and control circuit The input end is connected to the output end of the first transformer, and the output end of the second transformer is connected to the second input end of the gate voltage generating and control circuit, and the output end of the leakage pressure switch and the drain of the GaN HEMT The gate voltage is generated and connected to the third input end of the control circuit, and the second input end of the drain switch is connected to the first output end of the gate voltage generating and control circuit, and the gate voltage is generated and controlled A second output of the circuit, the gate input and the fourth input of the control circuit are coupled to the gate of the GaN HEMT.

The GaN HEMT bias circuit receives an external input voltage and passes through the first grounding capacitor group, and is connected to the first input terminal and the second input terminal of the gate voltage generating and controlling circuit via a first transformer and a second transformer. It satisfies the positive and negative voltages required by the gate voltage generation and control circuit, and the other through the drain switch to the drain of the GaN HEMT, the second input of the drain switch and the first of the gate voltage generation and control circuit The output terminal is connected, and the second output end and the fourth input end of the gate voltage generating and control circuit are connected to the gate of the GaN HEMT. According to the technical solution, the first capacitor group provides the voltage when the power is off, the first transformer and the second The transformer provides the operating voltage required for the gate voltage generation and control circuit. The gate voltage generation and control circuit meets the requirements of the GaN HEMT and the power-down timing. The automatic on-and-off function of the GaN HEMT circuit is realized, and the GaN HEMT is avoided. It is burnt by a large current, which in turn ensures the normal operation of the wireless communication device using the GaN HEMT.

DRAWINGS

1 is a schematic structural view of a first embodiment of a GaN HEMT bias circuit according to the present invention;

2 is a schematic structural view of a second embodiment of a GaN HEMT bias circuit according to the present invention;

3 is a timing diagram of actual measured power-on of a third embodiment of a GaN HEMT bias circuit according to the present invention;

4 is a timing diagram of measured power down of a fourth embodiment of a GaN HEMT bias circuit according to the present invention;

5 is a diagram showing a variation of gate voltage with input power according to a fifth embodiment of a GaN HEMT bias circuit of the present invention;

6 is a graph showing temperature changes of a gate voltage and a substrate according to a sixth embodiment of the GaN HEMT bias circuit of the present invention.

detailed description

In order to make the objects, technical solutions and advantages of the present invention more comprehensible, the present invention will be further described in detail with reference to the accompanying drawings.

To simplify the description, in the following description of each embodiment, a gallium nitride high electron mobility electron transistor is referred to as a GaN HEMT, and a gallium nitride high electron mobility electron transistor bias circuit is referred to as a GaN HEMT bias. The circuit is described.

1 is a schematic structural view of a first embodiment of a GaN HEMT bias circuit of the present invention.

As shown in FIG. 1, the GaN HEMT bias circuit of the present embodiment may include: a first ground capacitor group A11, a first transformer A12, a second transformer A13, a drain switch A14, and a gate voltage generation and control circuit A15, wherein The first grounding capacitor group A11, the input end of the first transformer A12, the first input terminal of the leakage pressure switch A14 are connected to the external voltage input terminal, the input end of the second transformer A13, the gate voltage generating and the first of the control circuit A15 The input end is connected to the output end of the first transformer A12, the output end of the second transformer A13 is connected to the second input end of the gate voltage generation and control circuit A15, the output end of the drain pressure switch A14 and the drain and gate voltage of the GaN HEMT The connection is connected to the third input end of the control circuit A15, and the second input end of the drain switch A14 is connected to the first output end of the gate voltage generation and control circuit A15, and the second output end of the gate voltage generation and control circuit A15 is gated. A fourth input of the voltage generation and control circuit A15 is coupled to the gate of the GaN HEMT.

For the first capacitor group A11, one or more large capacitance capacitors (generally 100uF or more) and RF filter capacitors may be included, and connected in parallel to the external input voltage V _EXT , which functions as low frequency filtering on the one hand, and On the one hand, energy storage. By using the principle that the capacitor voltage can not be abrupt, in the event of power failure and V _EXT failure, the gate voltage generation and control circuit A15 and the drain switch A14 can still be maintained, ensuring that the circuit can still provide the correct power-down sequence function.

In one embodiment, the GaN HEMT bias circuit may further include a third transformer A19 coupled between the output of the first transformer A12 and the first input of the gate voltage generation and control circuit A15. The effect can be: since the V _EXT voltage is relatively large, the output voltage of the first transformer A12 can be further transformed according to the easiness of device selection.

In one embodiment, for the first transformer A12, from the functional principle, the first transformer A12 is used to vary the V _{EXT of} the large voltage to the small voltage V1 to supply power to the second transformer A13 and the third transformer A19. A negative voltage is generated by the second transformer A13, and a third transformer A19 generates a positive voltage for use by the gate voltage generation and control circuit A15.

In one embodiment, for the second transformer A13, a switching power supply can be implemented. Since the V _EXT voltage is relatively large, a two-stage voltage variator is used in consideration of the easiness of device selection: the first transformer A12 and the second transformer A13. .

Further, as shown in FIG. 1 , the GaN HEMT bias circuit of the embodiment may further include: a second grounded capacitor group A16, and the second grounded capacitor group A16 is connected to the output end of the first transformer A12. The setting of the second grounding capacitor group A16 can play the following roles: first, as the output filter capacitor of the first transformer A12; secondly, as the input filter capacitor of the second transformer A13; finally, storing the power, in the power down, external input When the voltage V _EXT fails, the second grounded capacitor group A16 discharges the sustain gate voltage generation and the control circuit A15 operates normally.

Further, the GaN HEMT bias circuit may further include: a gate bias filter network A18 connected to the second output end of the gate voltage generation and control circuit A15 and the gate of the GaN HEMT between. Through the setting of the gate bias filter network A18, it is possible to filter and store the voltage generated by the gate voltage generated by the control circuit A15, ensuring that the voltage of the gate of the GaN HEMT is always a stable value.

Further, the GaN HEMT bias circuit may further include: a drain bias filter network A17 connected between the output terminal of the drain switch A14 and the drain of the GaN HEMT. The effect may be that after the gate voltage of the GaN HEMT is pulled below the pinch-off voltage, the drain bias filter network A17 supplies power to the first transformer A12 and discharges. The setting of the drain bias filter network A17, in combination with the first ground capacitor group A11 and the second ground capacitor group A16, can cause the gate voltage generation and the control circuit A15 to operate normally when discharging until V _{EXT is} close to 0V.

Further, the GaN HEMT bias circuit may further include: a first resistor Rg connected between the gate bias filter network A18 and the gate of the GaN HEMT. The first resistor Rg is set such that the gate bias filter network A18 is connected to the gate of the GaN HEMT through a high resistance line to further ensure that the voltage of the gate of the GaN HEMT is always a stable value.

2 is a schematic structural view of a second embodiment of a GaN HEMT bias circuit of the present invention.

As shown in FIG. 2, the GaN HEMT bias circuit of the present embodiment may include: a first ground capacitor group A11, a first transformer A12, a second transformer A13, a drain switch A14, and a gate voltage generation and control circuit A15, wherein The first grounding capacitor group A11, the input end of the first transformer A12, the first input terminal of the leakage pressure switch A14 are connected to the external voltage input terminal, the input end of the second transformer A13, the gate voltage generating and the first of the control circuit A15 The input end is connected to the output end of the first transformer A12, the output end of the second transformer A13 is connected to the second input end of the gate voltage generation and control circuit A15, the output end of the drain pressure switch A14 and the drain and gate voltage of the GaN HEMT The connection is connected to the third input end of the control circuit A15, and the second input end of the drain switch A14 is connected to the first output end of the gate voltage generation and control circuit A15, and the second output end of the gate voltage generation and control circuit A15 is gated. A fourth input of the voltage generation and control circuit A15 is coupled to the gate of the GaN HEMT.

For the first grounded capacitor group A11, it is a grounded capacitor group, and the other end is connected to an external voltage input terminal, and at the same time, since the input end of the first transformer A12 and the first input end of the drain switch are also connected to the external voltage input terminal, Connected to the GaN HEMT bias circuit.

In one embodiment, the first grounded capacitor group A11 may include a capacitor C3-capacitor C8, and the capacitor C3-capacitor C8 may be a large-capacitance capacitor (generally a capacitance of 100 uF or more), a radio frequency filter capacitor. The function of the large capacitor is to perform low frequency filtering and energy storage. By using the principle that the capacitor voltage cannot be abrupt, the GaN HEMT bias circuit can still be maintained normally during power-down and V _EXT failure, ensuring that the circuit can still provide the correct power-down sequence function.

For the first transformer A12, a voltage variator whose output voltage is adjustable is connected between the first grounded capacitor group A11 and the second transformer A13.

In one embodiment, the first transformer A12 may include an integrator U1, a resistor R2, and a resistor R4. And capacitor C10, wherein capacitor C10 is a grounding capacitor, the other end is connected to the input terminal VIN of the integrator U1, and the resistor R2 is connected between the output terminal VOUT of the integrator U1 and the regulating terminal ADJ of the integrator U1, and the resistor R4 is connected at one end. The adjustment terminal ADJ of the integrator U1 is grounded at the other end. The output voltage value can be adjusted by adjusting the values of resistor R2 and resistor R4.

Since the drain operating voltage of the high-power GaN HEMT is generally +28V or +48V, and the positive voltage value of the gate voltage generation and control circuit A15 is lower, generally +3V can work normally, so the first transformer A12 requires Having a wide input voltage range, in another embodiment, the first transformer A12 can also be implemented in series using two +DC/+DC voltage variators. The first transformer A12 with wide input voltage range can make the capacitor discharge through the first ground capacitor group A11 to work normally when the power is turned off and V _EXT fails, and provide stable V1 and V2 sustain gate voltage generation and control circuit normal operation. To ensure that the power-down sequence is correct.

For the second transformer A13, a switching power supply can be implemented, and the second transformer A13 is connected between the first transformer A12 and the gate voltage generating and controlling circuit A15.

In one embodiment, the second transformer A13 may include a switching power supply chip U2, a resistor R1, a resistor R3, a capacitor C1, a capacitor C2, a capacitor C11, an inductor L1, and a diode V1. The VIN terminal of the switching power supply chip U2 is connected to the output end of the first transformer A12, the BOOT terminal is grounded through the capacitor C1 and the inductor L1, the PH terminal is connected between the inductor L1 and the capacitor C1, the VSENSE terminal is connected to the PH terminal, the NC terminal, the ENA terminal and The GND terminal is empty. The capacitor C11 is connected between the VIN terminal of the switching power supply chip U2 and the output terminal of the second transformer A13, the anode of the diode V1 is connected to the output terminal of the second transformer A13, and the cathode of the diode V1 is connected to the PH terminal of the switching power supply chip U2, and the capacitor C2 The positive pole is grounded, the negative pole is connected to the output end of the second transformer A13, the resistor R1 is the grounding resistor, the other end is connected to the VSENSE end of the switching power supply chip U2, and the resistor R3 is connected to the VSENSE end of the switching power supply chip U2 and the output end of the second transformer A13. between.

For the drain switch A14, in one embodiment, the drain switch A14 may include a P-channel field effect transistor K2 and a diode D1, a gate of the P-channel field effect transistor K2 and a first output of the gate voltage generation and control circuit A15. The terminal is connected, the source and the gate voltage are connected to the third input terminal of the control circuit A15, the drain is connected to the input end of the first transformer A12, the anode of the diode D1 is connected to the source of the P-channel field effect transistor K2, and the negative electrode is connected. The drain of the P-channel field effect transistor K2 is connected.

Further, the drain switch A14 may further include a resistor R6 and a resistor R9, wherein the resistor R6 is connected between the gate and the drain of the P-channel field effect transistor K2, and the resistor R9 is connected to the gate voltage generating and controlling circuit A15 and P. Between the gates of the channel field effect transistor K2, a resistor R6 and a resistor R9 function as a protection circuit.

The voltage V _{EXT1 of the} first grounded capacitor group A11 is supplied to the drain of the GaN HEMT through the drain switch A14, and the other circuit generates the operating voltage V1 for the gate voltage generating and control circuit A15 through the first transformer A12. V1 generates a negative voltage through the second transformer A13 to provide a negative operating voltage V2 that the gate voltage generation and control circuit A15 need to use.

Further, the GaN HEMT bias circuit may further include: a second ground capacitor group A16 connected between the first transformer A12 and the second transformer A13.

In one embodiment, the second grounded capacitor group A16 may include a capacitor C9, a capacitor C12, and an inductor L2. The anode of the capacitor C9 is connected to the input end of the second transformer A13, the anode is grounded, and the capacitor C12 is a ground capacitor connected to the integrator U1. Between the output terminal and the regulation terminal, the inductor L2 is connected between the anode of the capacitor C9 and the output terminal of the first transformer A12. The second grounding capacitor group A16 can function as: an output filter capacitor of the first transformer A12; as an input filter capacitor of the second transformer A13; and energy storage, when the power is off, V _EXT fails, the second ground capacitor group A16 is discharged. Maintain gate voltage generation and control circuit operation.

Further, the GaN HEMT bias circuit may further include: a third transformer A19 connected between the output end of the first transformer A12 and the first input end of the gate voltage generating and controlling circuit A15. The voltage of the first transformer A12 is further transformed in consideration of the easiness of device selection.

In one embodiment, the third transformer A19 can include an integrator U3, capacitors C13, C14, and C15. The input terminal Vin of the integrator U3 is connected to the output end of the first transformer A12, the EN terminal is connected to the input terminal Vin, the BP terminal is grounded through the capacitor C15, the GND terminal is grounded, the output terminal Vout is the output end of the third transformer A19, and the capacitor C13 is Grounding capacitor, the other end is connected to the input terminal Vin of the integrator U3, the capacitor C14 is the grounding capacitor, and the other end is connected to the output terminal Vout of the integrator U3.

Further, the GaN HEMT bias circuit may further include a drain bias filter network A17 connected between the output terminal of the drain switch A14 and the drain of the GaN HEMT. The function is as follows: the first grounding capacitor group A11 and the second grounding capacitor group A16 are discharged, and the discharging power supply can make the gate voltage generating and the control circuit A15 work normally until V _{EXT is} close to 0V.

In one embodiment, the drain bias filter network A17 may include capacitors C18, C19, C20, and C21, and the capacitor C18-capacitor C21 is a ground capacitor connected in parallel to the output of the drain switch A14 and the drain of the GaN HEMT. between.

Further, the GaN HEMT bias circuit may further include: a gate bias filter network A18 connected to the second output end of the gate voltage generation and control circuit A15 and the gate of the GaN HEMT between.

Preferably, the gate bias filter network A18 may include capacitors C22, C23, and C24. The capacitor C22-capacitor C24 is a ground capacitor connected in parallel to the second output of the gate voltage generation and control circuit A15 and the gate of the GaN HEMT. between.

Further, the GaN HEMT bias circuit may further include: a first resistor Rg connected between the gate bias filter network A18 and the gate of the GaN HEMT.

In one embodiment, for the gate voltage generation and control circuit A15, the comparator U4A may be included, the negative pole of the power supply of the comparator U4A is connected to the output end of the second transformer A13, the positive pole of the power supply is connected to the output end of the third transformer A19, and the negative input terminal is The gate bias filter network A18 is connected, the positive input terminal is grounded, and the output terminal is connected to the second input terminal of the leakage pressure switch A14. When the gate voltage is a negative voltage and lower than the comparator preset threshold, the comparator U4A outputs a high level, causing the drain switch A14 to be turned on, and the GaN HEMT drain bias is connected.

Further, the gate voltage generating and controlling circuit A15 may further include a resistor R5, a resistor R7, a resistor R8, a resistor R10 and a capacitor C16, wherein the resistor R5 is connected to the output terminal of the second transformer A13 and the anode input terminal of the comparator U4A. The resistor R7 is connected between the negative input terminal of the comparator U4A and the first resistor Rg, and the resistor R8 is connected between the output terminal of the comparator U4A and the second input terminal of the drain switch A14, and the resistor R10 is the grounding resistor. One end is connected to the positive input terminal of the comparator U4A, the capacitor C16 is a grounding capacitor, and the other end is connected to the second input end of the leakage pressure switch A14 for voltage protection and filtering.

Further, the gate voltage generation and control circuit A15 may further include: a first N-channel field effect transistor K1 connected between the drain-voltage switch A14 and the comparator U4A, wherein the drain connection of the first N-channel field effect transistor K1 The second input of the drain switch A14, the source is grounded, and the gate is connected through a resistor R8 The output of comparator U4A is grounded through capacitor C16. The high level of the output of the comparator U4A causes the first N-channel field effect transistor K1 to be turned on, thereby causing the drain switch A14 to be turned on.

Further, the gate voltage generation and control circuit A15 may further include: a second N-channel field effect transistor K3, the gate of the second N-channel field effect transistor K3 is connected to the output terminal of the drain-voltage switch A14, the drain is grounded, and the source is connected. Gate bias filter network A18.

Further, the gate voltage generating and controlling circuit A15 may further include: a first capacitor C17 and a second resistor R11 and a third resistor R12, the first capacitor C17 being connected to the gate and the drain of the second N-channel field effect transistor K3 The second resistor R11 is connected between the gate of the second N-channel field effect transistor K3 and the output terminal of the drain-operated switch A14, and the third resistor R12 is connected to the gate and drain of the second N-channel field effect transistor K3. Between the poles.

When the drain switch A14 is turned on, the drain voltage VDD charges the capacitor C17 through R11. Select the appropriate values of R11 and C17 to make the RC charging time longer than the settling time of the drain voltage VDD, and ensure that the V _GS rises automatically to the required gate voltage value after VDD is stabilized.

After the charging of the first capacitor C17 is completed, the voltage dividing circuit composed of the second resistor R11 and the third resistor R12 turns on the second N-channel field effect transistor K3, and VDD_FB is pulled down to 0V.

Further, the gate voltage generating and controlling circuit A15 may further include: a fourth resistor R14, a fifth resistor R13, a sixth resistor R15 and a resistor RW1, and the fourth resistor R14 is connected to the source of the second N-channel field effect transistor K3. Between the gate bias filter network A18, the fifth resistor R13 is connected between the source of the second N-channel field effect transistor K3 and the output of the third transformer A19, and the sixth resistor R15 and the resistor RW1 are connected in series to the third. Between the output of transformer A19 and the gate bias filter network A18.

Further, the gate voltage generating and controlling circuit A15 may further include: an amplifier U4B connected between the fourth resistor R14, the sixth resistor R15 and the gate bias filter network A18, and a negative input terminal and a fourth resistor of the amplifier U4B. R14 and sixth resistor R15 are connected, the positive input terminal is grounded, and the output terminal is connected to the gate bias filter network A18. As can be seen from Figure 2, the U4B inverting amplifier feedback resistor is directly connected to the GaN HEMT gate through a high-impedance line. The gate resistor Rg can be seen as part of the operational amplifier U4B. The V _{GS is} seen as the U4B output voltage shift. Therefore, the current flowing through R18 and Rg does not affect V _GS , ensuring that the V _GS voltage is always a stable preset value for different input powers and temperatures.

Further, the gate voltage generation and control circuit A15 may further include a resistor R18 connected between the U4B output terminal and the gate of the GaN HEMT.

Further, the gate voltage generating and controlling circuit A15 may further include: a tenth resistor R22, and the resistor R22 is a reverse-amplifier feedback resistor composed of U4B, which is directly connected to the negative input terminal of the amplifier U4B and the GaN HEMT through a high resistance line. Between the gates.

At the time of power-on, since the drain switch is not turned on, the drain gate voltage is not connected, and the second N-channel field effect transistor K3 is not turned on. The gate voltage at this time is:

However, V _{DD_FB} = R14 / (R13 + R14) × V _{1_1} ≠ 0 (2)

Select the appropriate resistance of the fourth resistor R14 and the fifth resistor R13 so that V _{GS is} lower than the GaN HEMT pinch-off voltage.

When the charging of C17 is completed, the second N-channel field effect transistor K3 is turned on, and VDD_FB is pulled down to 0V. V _{GS is} automatically raised to the preset gate pressure value:

After power-down, VDD becomes small, and the second N-channel field effect transistor K3 is turned off. VDD_FB is again changed to the value of equation (2). V _{GS is} pulled below the pinch-off voltage.

The gate voltage generation and control circuit operates normally under the discharge power supply of the drain bias filter network A17, the first ground capacitor group A11, and the second ground capacitor group A16 until VDD approaches 0V.

Further, the gate voltage generation and control circuit A15 may further include: a temperature compensation circuit, the input end of the temperature compensation circuit is connected to the output end of the third transformer A19, and the output end is connected to the negative input terminal of the amplifier U4B. Through the temperature compensation circuit, the temperature compensation of the gate voltage of the GaN HEMT can be realized, so that the GaN HEMT can work stably under different temperature conditions.

In one embodiment, the temperature compensation circuit may include: an NPN transistor K4, a seventh resistor R17, an eighth resistor R19, and a ninth resistor R21, a collector of the NPN transistor K4, and an output of the third transformer A19, and a seventh The resistor R17 is connected, the other end of the seventh resistor R17 is connected to the negative input terminal of the amplifier U4B, the base is connected to the collector of the NPN transistor K4 through the eighth resistor R19, and the emitter is connected through the ninth resistor R21 and grounded. Since the NPN transistor emitter forward voltage has a negative temperature coefficient, and the V _GS in the circuit has a positive temperature coefficient, it is consistent with the GaN HEMT gate temperature compensation coefficient direction, so that any value of R17 can be obtained. The temperature compensation coefficient value realizes the temperature compensation of the GaN HEMT gate voltage and keeps the gate quiescent current stable.

Further, the temperature compensation circuit may include a resistor R16 connected between the third transformer A19 and the collector of the NPN transistor K4 to function as a protection circuit.

The NPN transistor K4 emitter junction forward conduction voltage has a negative temperature coefficient. It can be known from equation (1) that V _GS in the circuit has a positive temperature coefficient, which is consistent with the GaN HEMT gate voltage temperature compensation coefficient direction requirement. Any suitable temperature compensation coefficient value can be obtained by selecting the appropriate R17 value.

The first resistor Rg can be regarded as a part of the operational amplifier U4B, and the V _{GS is} regarded as the U4B output voltage shifting, so that the current flowing through the resistor R18 and the first resistor Rg does not affect the V _GS , ensuring different input powers and different temperatures. The lower V _GS voltage is always a stable preset.

3 is a timing diagram of actual measured power-on of the third embodiment of the GaN HEMT bias circuit of the present invention.

In this embodiment, according to the measured power-on timing diagram, it can be known that the power-on timing requirements of the GaN HEMT are satisfied.

Figure 3 illustrates: a) the horizontal axis is time, the unit is ms, 20ms/div

b) The vertical axis is the voltage in units of V. In the figure, the grid pressure line is 1V/div, the left horizontal line is 0V, the middle horizontal line is -2.5V, and the right horizontal line is -1.34V; in the figure, the leakage line is 20V/div, and the left horizontal line is 0V, the horizontal line on the right is +48V.

4 is a timing diagram of measured power down of a fourth embodiment of a GaN HEMT bias circuit of the present invention.

In this embodiment, according to the measured power-down timing diagram, it can be known that the power-down timing requirement of the GaN HEMT is satisfied.

Figure 4 illustrates: a) The horizontal axis is time, in ms, 500ms/div

b) The vertical axis is the voltage in units of V. In the figure, the grid pressure line is 1V/div, the left horizontal line is -1.34V, the middle horizontal line is -2.5V, and the highest right side is 0V; in the figure, the leakage line is 40V/div, and the left horizontal line is + 48V, the horizontal line on the right is 0V.

FIG. 5 is a diagram showing changes in gate voltage with input power according to a fifth embodiment of the GaN HEMT bias circuit of the present invention.

In this embodiment, the gate voltage of a 200W saturated power and 15dB gain GaN HEMT at normal temperature of 25 °C varies with the RF input power. As the input power increases, the gate voltage of the GaN HEMT does not occur. Change, output a stable gate voltage.

In this embodiment, as the substrate temperature increases, the gate voltage of the GaN HEMT does not change greatly, and a stable gate voltage is output.

Through the embodiment of the invention, the gate voltage generation and control circuit satisfies the requirements of the GaN HEMT and the power-down timing, realizes the automatic power-on and power-down function of the GaN HEMT circuit, and avoids the GaN HEMT being burned by a large current, thereby ensuring the use of GaN. The wireless communication device of the HEMT works normally. Further, the gate voltage is kept stable under different input powers and the same temperature condition; at the same time, the gate voltage is adjustable at different temperatures to ensure the static working point is stable, and the gate quiescent current is kept stable. . Therefore, the GaN HEMT bias circuit enables the GaN HEMT circuit to not only automatically meet the upper and lower power-down timing requirements, but also to ensure stable operation of the GaN HEMT under different input powers and different temperature conditions.

The technical features of the above-described embodiments may be arbitrarily combined. For the sake of brevity of description, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction between the combinations of these technical features, All should be considered as the scope of this manual.

The above-described embodiments are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the invention. It should be noted that a number of variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be determined by the appended claims.

Claims

A gallium nitride high electron mobility electron transistor GaN HEMT bias circuit, comprising: a first ground capacitor group, a first transformer, a second transformer, a drain voltage switch, and a gate voltage generating and controlling circuit, wherein The first grounded capacitor group, the input end of the first transformer, and the first input end of the drain switch are connected to an external voltage input end, and the input end of the second transformer, the gate voltage generation and control a first input end of the circuit is connected to an output end of the first transformer, an output end of the second transformer is connected to a second input end of the gate voltage generating and control circuit, and an output end of the drain switch is a drain of the GaN HEMT, the gate voltage is generated and connected to a third input end of the control circuit, and a second input end of the drain switch is connected to the first output end of the gate voltage generating and control circuit, the gate A second output of the voltage generation and control circuit, a fourth input of the gate voltage generation and control circuit is coupled to the gate of the GaN HEMT.
The GaN HEMT bias circuit of claim 1 further comprising a second set of grounded capacitors, said second set of grounded capacitors being coupled to the output of said first transformer.
The GaN HEMT bias circuit of claim 1 further comprising a third transformer coupled to said first transformer output and said first input of said gate voltage generation and control circuit Between the ends.
The GaN HEMT bias circuit of claim 3, further comprising a gate bias filter network coupled to the second output of the gate voltage generation and control circuit Between the gates of GaN HEMTs.
The GaN HEMT bias circuit of claim 1 further comprising a drain bias filter network coupled to the output of the drain switch and the drain of the GaN HEMT between.
The GaN HEMT bias circuit of claim 4 further comprising a first resistor coupled between said gate bias filter network and a gate of the GaN HEMT.
The GaN HEMT bias circuit according to claim 4, wherein the gate voltage generation and control circuit comprises: a comparator, a power supply negative electrode of the comparator is connected to the second transformer output terminal, and a power source positive connection The third transformer output terminal is connected to the gate bias filter network, the positive input terminal is grounded, and the output terminal is connected to the second input end of the drain switch.
The GaN HEMT bias circuit according to claim 7, wherein said gate voltage generating and controlling circuit further comprises: a first N-channel field effect transistor connected between said drain switch and said comparator The drain of the first N-channel field effect transistor is connected to the second input end of the drain switch, the source is grounded, and the gate is connected to the output of the comparator.
The GaN HEMT bias circuit according to claim 8, wherein said gate voltage generating and controlling circuit further comprises: a second N-channel field effect transistor, a gate connection of said second N-channel field effect transistor The output of the drain switch is grounded, and the source is connected to the gate bias filter network.
The GaN HEMT bias circuit of claim 9, wherein the gate voltage generation and control circuit further comprises: a capacitor, a second resistor, and a third resistor, the capacitor being coupled to the second N-channel field Between the gate and the drain of the effect transistor, the second resistor is connected between the gate of the second N-channel field effect transistor and the output of the drain switch, and the third resistor is connected to the Between the gate and the drain of the second N-channel field effect transistor.
The GaN HEMT bias circuit according to claim 10, wherein the gate voltage generation and control circuit further comprises: a fourth resistor, a fifth resistor and a sixth resistor, wherein the fourth resistor is connected to the Between the source of the two N-channel FET and the gate bias filter network, the fifth resistor is connected between the source of the second N-channel FET and the output of the third transformer, A six resistor is coupled between the third transformer output and the gate bias filtering network.
The GaN HEMT bias circuit according to claim 11, wherein the gate voltage generation and control circuit further comprises: a fourth resistor, the sixth resistor, and the gate bias filter network Between the amplifiers, the negative input of the amplifier is connected to the fourth resistor and the sixth resistor, the positive input is grounded, and the output is connected to the gate bias filter network.
The GaN HEMT bias circuit according to claim 12, wherein the gate voltage generating and controlling circuit further comprises: a temperature compensation circuit, wherein the input end of the temperature compensation circuit is connected to an output end of the third transformer, The output is coupled to the negative input of the amplifier.
The GaN HEMT bias circuit according to claim 13, wherein the temperature compensation circuit comprises: an NPN transistor, a seventh resistor, an eighth resistor, and a ninth resistor, a collector of the NPN transistor and the first An output of the third transformer, the seventh resistor is connected, and the seventh The resistor is connected to the negative input terminal of the amplifier, the base is connected to the collector of the NPN transistor through the eighth resistor, and the emitter is connected through the ninth resistor and grounded.
The GaN HEMT bias circuit according to claim 12, wherein the gate voltage generation and control circuit further comprises: a tenth resistor connected to the amplifier input terminal and the gate of the GaN HEMT Between the poles.
The GaN HEMT bias circuit according to any one of claims 1 to 15, wherein the drain-operated switch comprises: a P-channel field effect transistor and a diode, a gate of the P-channel field effect transistor and the The gate voltage is generated and connected to the first output end of the control circuit, the source is connected to the third input terminal of the gate voltage generating and control circuit, and the drain is connected to the input end of the first transformer, and the anode of the diode is The source of the P-channel field effect transistor is connected, and the negative electrode is connected to the drain of the P-channel field effect transistor.