WO2016181513A1 - Power supply device - Google Patents

Power supply device Download PDF

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Publication number
WO2016181513A1
WO2016181513A1 PCT/JP2015/063683 JP2015063683W WO2016181513A1 WO 2016181513 A1 WO2016181513 A1 WO 2016181513A1 JP 2015063683 W JP2015063683 W JP 2015063683W WO 2016181513 A1 WO2016181513 A1 WO 2016181513A1
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Prior art keywords
circuit
voltage
capacitor
switching element
inductor
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PCT/JP2015/063683
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French (fr)
Japanese (ja)
Inventor
俊蔵 大島
Original Assignee
俊蔵 大島
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Priority to PCT/JP2015/063683 priority Critical patent/WO2016181513A1/en
Publication of WO2016181513A1 publication Critical patent/WO2016181513A1/en

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

Definitions

  • the present invention relates to a power supply device that supplies DC power to a load, and more particularly to a power supply device that can improve power factor and efficiency.
  • FIG. 10 shows a circuit diagram of a conventional power supply device 800.
  • the power supply device 800 shown in FIG. 10 is configured as a step-down AC-DC converter including a full-wave rectifier circuit 810, a low-pass filter 900, a power supply circuit 830 that supplies DC power to a load 820, and a control circuit 840.
  • Full-wave rectification circuit 810 performs full-wave rectification on AC voltage Vac of AC power supply 10 and converts it into DC voltage (pulsating DC voltage) Vdc.
  • An N-type MOSFET is used as the power switching element T831 of the power supply circuit 830.
  • the power supply circuit 830 has a power factor correction (PFC) function for suppressing the amplitude of the harmonic current below a limit value (referred to as “PFC standard”).
  • PFC power factor correction
  • the control circuit 840 turns on the switching element T831 in the set cycle, and turns off the switching element T831 when the drain current of the switching element T831 (voltage drop of the current detection resistor R831) becomes larger than the threshold value.
  • the magnitude (amplitude) of the current I1 is linked to the magnitude (amplitude) of the DC voltage Vdc.
  • the power factor cos ⁇ ( ⁇ : phase difference between the AC voltage Vac and the AC input current Iac) of the AC input power approaches “1”.
  • the current I1 is cut off while the switching element T831 is off. That is, the current I1 flows intermittently. For this reason, the harmonic current is included in the current I1.
  • a low-pass filter 900 is provided in order to prevent this harmonic current from propagating to the AC power supply side.
  • the low-pass filter 900 provided in the conventional power supply device 800 includes a capacitor having a small capacitance and an inductor having a large inductance in order to prevent the power factor from deteriorating.
  • An inductor having a large inductance has a large number of turns of the conductive wire.
  • the inductor becomes large, and thus it is necessary to form the inductor using a thin conducting wire.
  • the resistance value of the inductor increases and the loss of the inductor increases.
  • the conventional power supply apparatus has a limit in improving the efficiency because the loss of the inductor constituting the low-pass filter for preventing the harmonic current from propagating to the AC power supply side is large.
  • the present invention has been made in view of such a point, and an object of the present invention is to provide a power supply device capable of improving the power factor and improving the efficiency.
  • the present invention includes a rectifier circuit that converts an AC voltage from an AC power source into a DC voltage, a power supply circuit that supplies DC power to a load, and a control circuit that controls the power supply circuit.
  • the rectifier circuit converts an AC voltage into a DC voltage (pulsating DC voltage), and generates the converted DC voltage between the positive electrode end and the negative electrode end.
  • a full-wave rectifier circuit is typically used as the rectifier circuit.
  • the terms “positive electrode end” and “negative electrode end” are used as terms representing locations where a DC voltage is generated.
  • the power supply circuit includes first and second capacitors, first and second inductors, diodes, and switching elements.
  • the second inductor and the second capacitor are arranged in series between the positive terminal and the negative terminal of the rectifier circuit.
  • a first inductor, a parallel circuit of a load and a first capacitor, and a switching element are arranged in series.
  • a diode (freewheeling diode) is arranged in parallel in the series circuit of the first inductor and load and the parallel circuit of the first capacitor.
  • the inductance of the second inductor is set to a value larger than the inductance of the first inductor.
  • the control circuit is configured to turn on the switching element at a set cycle, and to turn off the switching element when the current flowing through the switching element becomes greater than a threshold linked to the magnitude of the DC voltage.
  • a “threshold value proportional to the magnitude (amplitude) of the DC voltage” is typically used.
  • the second inductor, the first inductor, and the second capacitor are arranged in series between the positive terminal and the negative terminal of the rectifier circuit.
  • a parallel circuit of a load and a first capacitor and a switching element are arranged in series at both ends of the series circuit of the first inductor and the second capacitor.
  • a diode (freewheeling diode) is arranged in parallel in the series circuit of the first inductor and load and the parallel circuit of the first capacitor.
  • the inductance of the second inductor is set to a value larger than the inductance of the first inductor.
  • the control circuit is configured to turn on the switching element at a set cycle and turn off the switching element when the current flowing through the switching element becomes greater than a threshold linked to the magnitude of the DC voltage, as in the first invention. ing.
  • the second capacitor is charged by the DC voltage of the rectifier circuit.
  • the switching element is turned on, the second capacitor is discharged through a path including the first inductor, the load, and the switching element.
  • the electromagnetic energy accumulated in the first inductor when the switching element is turned on is converted into a return current that flows through a path including the first inductor, the load, and the diode.
  • the control device is configured to execute the processing every clock cycle.
  • the threshold value is a value obtained by adding a value corresponding to the discharge charge amount of the second capacitor due to the decrease in the DC voltage during the clock cycle.
  • the threshold value is configured to be linked to a value obtained by subtracting the set value from the magnitude of the DC voltage. Then, when the magnitude of the DC voltage is smaller than the set value, the control device holds the switching element in the off state.
  • the switching element since the switching element is controlled so that the DC voltage (pulsating DC voltage) does not fall below the set value, the charge charged in the second capacitor when the DC voltage increases and the switching when the DC voltage decreases. The sum of absolute values of electric charges discharged from the second capacitor when the element is turned on is reduced, and the phase advance by the second capacitor is suppressed. Then, the capacity of the second capacitor can be increased accordingly.
  • a third capacitor that can be arranged in series with the second capacitor is provided.
  • a changeover switch for connecting the third capacitor in series with the second capacitor or for disconnecting the connection between the third capacitor and the second capacitor is used. For example, if the DC power supplied to the load is decreased by changing the threshold value in a state where the capacity of the second capacitor is set to a predetermined value, the power factor may deteriorate.
  • the power factor can be prevented from deteriorating by connecting the third capacitor in series with the second capacitor to reduce the combined capacitance.
  • a MOSFET parasitic diode is used as the diode (freewheeling diode). Then, the control circuit turns on the MOSFET within a set period after the switching element is turned off and when the cathode voltage of the parasitic diode becomes smaller than a value obtained by subtracting the first set value from the anode voltage, and the set period elapses. Later, when the cathode voltage of the parasitic diode becomes larger than the value obtained by subtracting the first set value from the anode voltage, the MOSFET is turned off.
  • the setting period is set to a period shorter than the period from when the return current starts to flow through the parasitic diode of the MOSFET until it disappears.
  • the MOSFET when the return current is passed through the MOSFET's parasitic diode, the MOSFET is turned on, so that the power loss is reduced and the efficiency is reduced as compared with the case where the return current is passed through the return diode. Can be improved.
  • the reflux current is passed through the parasitic diode of the MOSFET, it is preferable to use a voltage detection circuit that detects the voltage between the anode and the cathode of the parasitic diode in order to determine the on / off timing of the MOSFET.
  • a voltage detection circuit having first and second source follower circuits constituted by FETs is used.
  • the source resistance of the first source follower circuit is connected to the anode of the parasitic diode
  • the source resistance of the second source follower circuit is connected to the cathode of the parasitic diode.
  • a common bias voltage is applied to the gates of the FETs of the first and second source follower circuits.
  • the voltage between the anode and the cathode of the parasitic diode is converted into a difference between the current flowing through the first source follower circuit and the current flowing through the second source follower circuit.
  • a voltage detection circuit having first and second circuits is used.
  • the first circuit includes a diode arranged in series between the cathode of the parasitic diode and the ground, a first resistor, a first PMOSFET, a second resistor, and a first NMOSFET.
  • the gate and drain of the first PMOSFET are short-circuited, and the gate and drain of the first NMOSFET are short-circuited.
  • the second circuit includes a diode arranged in series between the anode of the parasitic diode and the ground, a third resistor, a second PMOSFET, a fourth resistor, and a second NMOSFET.
  • the gate of the second PMOSFET is connected to the gate of the first PMOSFET
  • the gate of the second NMOSFET is connected to the gate of the first NMOSFET.
  • the characteristics of the second PMOSFET and the second NMOSFET have the same characteristics as the first PMOSFET and the first NMOSFET, respectively.
  • the resistance value of the fourth resistor is set to be smaller than the resistance value of the second resistor.
  • the resistance value of the third resistor is set to be equal to or greater than the resistance value of the first resistor.
  • the drain voltage of the second NMOSFET is configured to change according to the voltage between the anode and the cathode of the parasitic diode.
  • the power supply device of the present invention can improve the power factor and the efficiency.
  • Other features, functions, and advantages of the present invention can be readily understood with reference to the specification, claims, and accompanying drawings.
  • FIG. 1 shows a circuit diagram of a first embodiment 100 of the power supply device of the present invention.
  • the power supply device 100 includes a full-wave rectifier circuit 110 that converts an AC voltage Vac from an AC power supply 10 into a DC voltage Vdc, a power supply circuit 130, a control circuit 140, a power supply circuit 180, and a drive signal output circuit 190. It is comprised by.
  • the control circuit 140 has a threshold correction circuit 150.
  • the full-wave rectifier circuit 110 has a plurality of diodes D111 to D114 connected in a bridge, full-wave rectifies the AC voltage Vac applied between the AC input terminals a and b, and between the positive terminal c and the negative terminal d.
  • a DC voltage Vdc is generated.
  • the DC voltage Vdc is a pulsating DC voltage having a magnitude (amplitude) that changes in accordance with the magnitude (amplitude) of the AC voltage Vac.
  • the negative terminal d of the full wave rectifier circuit 110 is grounded. For this reason, grounding any of the terminals means connecting the terminal to the negative electrode end d.
  • the power supply circuit 130 is disposed between the positive end c and the negative end d of the full-wave rectifier circuit 110 and one end 131 and the other end 132 of the load 120, and supplies DC power to the load 120.
  • a capacitor C131 having a capacitance C1 is disposed between one end 131 and the other end 132 of the load 120.
  • an inductor L131 having an inductance L1 and an inductor L132 having an inductance L2 are arranged in series. At this time, the inductor L131 is connected to one end 131, and the inductor L132 is connected to the positive end c.
  • a switching element T131 and a current detection resistor R131 are arranged in series between the other end 132 of the load 120 and the ground.
  • an N-type MOSFET is used as the switching element T131.
  • a capacitor C132 having a capacitance Cp is arranged between a connection point r between the inductor L131 and the inductor L132 and a fixed contact e of the changeover switch SW131.
  • the normally closed contact f of the changeover switch SW131 is grounded, and the normally open contact g is grounded via a capacitor C133 having a capacitance Cp1.
  • a diode D131 is arranged between the other end 132 of the load 120 and the connection point r. At this time, the anode of the diode D131 is connected to the other end 132, and the cathode is connected to the connection point r.
  • the capacitor C131 corresponds to the “first capacitor” of the present invention
  • the capacitor C132 corresponds to the “second capacitor” of the present invention
  • the capacitor C133 corresponds to the “third capacitor” of the present invention
  • the inductor L131 corresponds to the “first inductor” of the present invention
  • the inductor L132 corresponds to the “second inductor” of the present invention.
  • the power supply circuit 180 is disposed between the positive terminal c and the ground, and includes a resistor R181, a Zener diode ZD181, and a capacitor C181.
  • the power supply circuit 180 applies a voltage Vzd determined by the Zener voltage of the Zener diode ZD181 to the control circuit 140 and the drive signal output circuit 190.
  • the drive signal output circuit 190 is disposed between the voltage Vzd and the ground, and includes a switch SW191 and resistors R191 and R192. When the switch SW191 is turned on, the drive signal output circuit 190 outputs an H level drive signal that instructs the start of supply of DC power to the load 120 to the control circuit 140.
  • the control circuit 140 includes P-type MOSFETs T141, T142, T146, and T147, N-type MOSFETs T143 to T145, T148, and T149, resistors R141 to R144, a constant current source IDC141, a clock signal generation circuit 141, and a Schmitt trigger ST141. , D flip-flop DFF 141, AND circuit AND 141, drive circuit 142, and threshold correction circuit 150.
  • the magnitude of the current Iref flowing through the series circuit of the resistors R141 and T149 is substantially proportional to the magnitude (amplitude) of the DC voltage Vdc.
  • T148 and T149 and T146 and T147 are arranged to form a current mirror circuit. Let the drain current of T146 be I14.
  • a threshold value generation circuit for generating a threshold value (current threshold value) I14 is configured by T146 to T149 and the resistor R141.
  • the constant current I11 from the constant current source IDC 141 flows through T145 and the resistor R144, whereby the gate of T145 becomes a constant voltage.
  • the gate voltage at T145 is used as a bias voltage.
  • a first source follower circuit is formed by T144 and the resistor R143, and a current I12 flows through T142 and the first source follower circuit.
  • a second source follower circuit is formed by T143 and the resistor R142, and the current I13 flows through the T141, the second source follower circuit, and the current detection resistor R131.
  • N-type MOSFETs having the same characteristics are used as T143, T144, and T145.
  • resistors having the same resistance value are used as the resistors R142, R143, and R144.
  • the resistance value of the resistor R142 is set to a value at which the resistance value of the current detection resistor R131 can be ignored compared to the resistance value of the resistor R142.
  • the drive circuit 142 includes a T-type MOSFET T142a and an N-type MOSFET 142b, and an output terminal is connected to the gate of the switching element T131.
  • a clock signal is input from the clock signal generation circuit 141 to the reset terminal R bar of the DFF 141 at a set cycle (clock cycle).
  • the voltage at the connection point s between T141 and T143 is input to the clock terminal CLK of the DFF 141 via ST141.
  • the control circuit 140 turns on the switching element T131 at a set cycle (clock cycle). Further, when the current flowing through the switching element T131 (in this embodiment, the voltage drop of the current detection resistor R131) becomes larger than a threshold value linked to the magnitude (amplitude) of the DC voltage Vdc, the switching element T131 is turned off.
  • the threshold value generated from the threshold value generation circuit is corrected by the threshold value correction circuit 150.
  • the threshold correction circuit 150 will be described later.
  • the resistance value of the current detection resistor R131 is R1
  • the resistance value of the resistor R142 is R2.
  • the voltage drop of the current detection resistor R131 is “0”, so that [I12 ⁇ I11] and the drain of the T141 The current becomes equal to the current I12.
  • the drain current of T143 is also equal to the drain current of T141, since the drain current of T143 can flow up to a current having the same magnitude as the current I11, the voltage at the point s is lowered. That is, the voltage at point s is L level.
  • the switch SW191 since the switch SW191 is off, the drive signal output circuit 190 does not output an H level drive signal.
  • the switching element T131 maintains an off state.
  • the DC voltage Vdc causes the charging current I1 of the capacitor C132 to flow through the inductor L132, the capacitor C132, the fixed contact e of the changeover switch SW131, the normally closed contact f, and the ground path.
  • the threshold value changes when the DC voltage Vdc changes.
  • the threshold for the same DC voltage Vdc can be changed by changing the proportionality constant between the DC voltage Vdc and the current I14.
  • a method of changing the proportionality constant a method of changing the resistance value of the resistor R141, or a method of changing the current mirror ratio of T148 and T149 or T146 and T147 can be used.
  • the return current I3 flows through the inductor L131, the parallel circuit of the load 120 and the capacitor C131, and the path of the diode D131 due to the electromagnetic energy accumulated in the inductor L131.
  • a diode through which a return current flows is referred to as a “return diode”.
  • the charging current I1 of the capacitor C132 flows through the path of the fixed contact e and the normally closed contact f of the full-wave rectifier circuit 110, the inductor L132, the capacitor C132 and the changeover switch SW131. Thereby, the charge of the capacitor C132 discharged when the switching element T131 is turned on is supplemented.
  • the inductance L2 of the inductor L132 is small, charging of the capacitor C132 is completed during the OFF period of the switching element T131, and the current I1 becomes “0”.
  • the inductance L2 of the inductor L132 is increased, the charging current I1 continues to flow during the OFF period of the switching element T131.
  • the current I1 is an absolute value of the AC input current Iac. Therefore, by continuing the current I1 during the OFF period of the switching element T131, the AC input current Iac continues to flow during one cycle (ON period + OFF period) (also referred to as “control period”) of the switching element T131. Thus, the generation of harmonic current is suppressed.
  • the low-pass filter used in the conventional power supply device 800 shown in FIG. 10 can be removed.
  • the inductance of the inductor constituting the low pass filter can be reduced. Therefore, the efficiency can be improved and the product shape can be greatly reduced.
  • the on period of the switching element T131 is several ⁇ s.
  • the capacitor C132 is discharged, and the voltage VCp at the positive terminal of the capacitor C132 decreases.
  • the amount of decrease in VCp depends on the capacitance Cp of the capacitor C132. That is, as the capacitance Cp increases, the amount of decrease in VCp decreases.
  • the AC power supply 10 is 100 V and 60 Hz, the peak value of Vdc is 141 V.
  • the capacitance Cp of the capacitor C132 is set so that the decrease amount of the positive electrode voltage VCp due to the discharge is several V during the ON period of the switching element T131.
  • the capacitance Cp of the capacitor C132 is set to about 0.3 ⁇ f, for example.
  • the voltage (load voltage) of the load 120 constituted by a light emitting diode is VLED
  • the switching element T131 is turned on
  • the terminal voltage VL1 of the inductor L131 is expressed by (Expression 2).
  • Is at the time of I2 shutoff is expressed by (Equation 3).
  • (R2 / R1) ⁇ K ⁇ Vdc (VCp ⁇ VLED) / L1 ⁇ ts Since [Vdc ⁇ VCp], the above expression can be expressed as (Expression 4).
  • VCp is larger than Vdc at the start of discharge and smaller than Vdc at the end of discharge, and the average value during the discharge period is substantially equal to Vdc. Therefore, in (Expression 4) and (Expression 5), [VCp ⁇ Vdc] can be obtained.
  • the amount of Cp discharge charge is proportional to Vdc in a region where [Vdc >> VLED], and becomes larger than the Vdc proportional value as Vdc decreases and approaches VLED.
  • Cp discharge charge Cp charge current integrated value ⁇ Vdc ⁇ Cp (Formula 6)
  • the charge amount [ ⁇ Vdc ⁇ Cp] acts to advance the phase of the AC input current Iac with respect to the AC voltage Vac, and generates a harmonic current close to the fundamental frequency.
  • the Cp discharge charge amount is the Cp charge current integral of one cycle of the switching element T131. Almost equal to the value.
  • the AC input current Iac is the sum of the charging current of the capacitor C132, the current flowing through the resistor R181, and the current Iref flowing through the resistor R141. Since the current flowing through the resistors R181 and R141 is substantially proportional to Vdc, the AC input current Iac has a magnitude proportional to Vdc. Therefore, the AC input current Iac is substantially in phase with the AC voltage Vac, and the power factor approaches “1”.
  • the reflux current I3 will be described.
  • a counter electromotive force is generated in the inductor L131 in a direction in which the current I2 that was flowing through the inductor L131 when the switching element T131 is turned on is generated, so that the positive terminal voltage of the capacitor C131 increases.
  • the negative terminal voltage of the capacitor C131 is raised.
  • the negative terminal voltage of the capacitor C131 reaches a voltage higher than the positive terminal voltage VCp of the capacitor C132 by the forward voltage of the freewheeling diode D131, the inductor L131, the parallel circuit of the load 120 and the capacitor C131, and the path of the freewheeling diode D131, A reflux current I3 flows.
  • the back electromotive force generated in the inductor L131 is the sum of the inter-terminal voltage (load voltage) VLED of the capacitor C131 and the forward voltage VD1 of the freewheeling diode D131.
  • the reflux current I3 is proportional to (VLED + VD1) and linearly decreases with a gradient having a magnitude inversely proportional to L1.
  • L1 increases, the time until the return current I3 disappears becomes longer.
  • the switching element T131 is turned on while the return current I3 is flowing.
  • the electromagnetic energy newly accumulated in the inductor L131 when the switching element T131 is next off is [L1 ⁇ (Is 2 ⁇ I3rem 2 ) / 2]. Become.
  • inductor L131 is a [L1 ⁇ (Is) 2/ 2]
  • the electromagnetic energy [L1 ⁇ (I3rem) 2/ 2] is accumulated constantly inductor L131, is not output. That is, even I3rem flows back circuit, electromagnetic energy [L1 ⁇ (I3rem) 2/ 2] is not transmitted to the output side.
  • the return circuit power loss occurs due to a drop in the forward voltage of the wiring resistance and the return diode D131. Therefore, the efficiency is lowered due to the non-output I3rem flowing.
  • the larger the L1 the smaller the current gradient change when changing from I2 to I3, so the loss of the switching element T131 becomes smaller. Therefore, it is desirable to set the inductance L1 as large as possible within a range in which the return current I3 disappears during the OFF period of the switching element T131.
  • a method of changing the magnitude of the DC power supplied to the load 120 a method of changing the resistance value of the resistor R141 or a method of changing the current mirror ratio of T148 and T149 or T146 and T147. Can be used. If the capacitance Cp of the capacitor C132 is fixed at, for example, 0.3 ⁇ F, the power factor can be set within a predetermined range when the DC power is large (can satisfy the PFC standard), but if the DC power is reduced, the power In some cases, the rate cannot be set within a predetermined range (the PFC standard cannot be satisfied).
  • the Cp discharge charge amount decreases and the Cp charge current integral value decreases, and in the above-described (Equation 6), the condition of [Cp charge current integral value >> ⁇ Vdc ⁇ Cp] cannot be satisfied.
  • the changeover switch SW131 shown in FIG. 1 is switched to connect the fixed contact e and the normally open contact g.
  • the capacitor C133 having the capacitance Cp1 is connected in series to the capacitor C132, the combined capacitance (equivalent capacitance of Cp) is reduced, and the condition [Cp charging current integral value >> ⁇ Vdc ⁇ Cp] can be satisfied. .
  • the power factor can be set within a predetermined range even when the resistance value of the resistor R141 is increased.
  • the threshold correction circuit 150 will be described.
  • the current I1 is obtained.
  • the absolute value of AC input current Iac is substantially equal to current I1 flowing through inductor L132.
  • Solving (Equation 7) with Vdc constant, I1 is expressed by (Equation 8).
  • I1 is a convex waveform corresponding to the clock period. It becomes a continuous waveform.
  • the peak value (local maximum value) of the convex waveform has a magnitude proportional to Vdc in the region of [Vdc >> VLED], and becomes a value larger than the Vdc proportional value as (Vdc ⁇ VLED) decreases.
  • the fluctuation range of the convex waveform depends on the ratio of the clock period to the sine wave period. That is, when the period of the sine wave becomes relatively large with respect to the clock period, the fluctuation width of the convex waveform becomes small.
  • the amount of Cp discharge charge is decreased by [ ⁇ Vdc ⁇ Cp] when Vdc increases, and the amount of Cp discharge charge is decreased by [ ⁇ Vdc when Vdc decreases.
  • XCp] should be increased.
  • the Cp discharge charge amount is proportional to I14. Therefore, in order to prevent an increase in the phase advance of I1 due to an increase in Cp, when Vdc is increased, I14 is decreased by an amount corresponding to [ ⁇ Vdc ⁇ Cp], and when Vdc is decreased, I14 is decreased by [ ⁇ Vdc ⁇ Cp. ] Just increase by a considerable amount.
  • Cp is increased to increase the harmonic current of the clock frequency.
  • the amplitude is reduced.
  • the threshold correction circuit 150 includes P-type MOSFETs T153 and T154, N-type MOSFETs T151, T152, and T155, a capacitor C151, and diodes D151 and D152.
  • T151 and T152 and T153 and T154 are arranged to form a current mirror circuit.
  • the threshold correction circuit 150 operates as follows. When Vdc increases, a charging current flows through the capacitor C151 through the path of Vdc, capacitor C151, diode D151 and T151. At this time, since the potential of the anode of the diode D151 becomes higher than the ground level, T155 is off. The current flowing through the capacitor C151 is 90 degrees out of phase with respect to Vdc, and its magnitude is proportional to the differential value of Vdc, and is therefore proportional to [ ⁇ Vdc ⁇ Cp]. Since the current mirror circuit is constituted by T151 and T152, the drain current I15 of T152 is proportional to the charging current of the capacitor C151, and the magnitude thereof can be adjusted by the current mirror ratio of T151 and T152.
  • the current I15 proportional to [ ⁇ Vdc ⁇ Cp] is subtracted from the current I14 proportional to Vdc.
  • the capacitor C151 pushes down the anode potential of the diode D151 below the ground level, so that T155 is turned on.
  • T155 is turned on, the discharge current of the capacitor C151 flows through the paths of the capacitors C151, T153, T155, and the diode D152.
  • the discharge current of the capacitor C151 is proportional to [ ⁇ Vdc ⁇ Cp].
  • the drain current I16 of T154 is proportional to the discharge current of the capacitor C151, and the magnitude thereof can be adjusted by the current mirror ratio of T153 and T154. That is, in the process of decreasing Vdc, the current I16 proportional to [ ⁇ Vdc ⁇ Cp] is added to the current I14 proportional to Vdc. Accordingly, [Cp discharge charge amount ⁇ Vdc ⁇ Cp] in each clock cycle, that is, the Cp charge amount is proportional to Vdc, and an increase in phase advance due to an increase in Cp can be prevented.
  • the simulation result when the threshold value correction circuit 150 is provided is shown in FIG.
  • the simulation results shown in FIG. 2 are obtained when the values of the circuit elements are set as follows. Vac: AC 100 V, 60 Hz, L1: 50 ⁇ H, L2: 600 ⁇ H, Cp: 0.6 ⁇ F, C1: 500 ⁇ F, C151: 1 nF, clock cycle: 20 ⁇ s (H level period: 1.6 ⁇ s (when Vdc increases), 1.8 ⁇ s ( Vdc decrease)), VLED average value: 15 V, LED load current average value: 644 mA.
  • Vac AC 100 V, 60 Hz
  • L1 50 ⁇ H
  • L2 600 ⁇ H
  • Cp 0.6 ⁇ F
  • C1 500 ⁇ F
  • C151 1 nF
  • clock cycle 20 ⁇ s (H level period: 1.6 ⁇ s (when Vdc increases), 1.8 ⁇ s ( Vdc decrease))
  • VLED average value 15 V
  • LED load current average value 6
  • the horizontal axis represents elapsed time t (ms)
  • the first vertical axis represents the voltage (V) of the graph (1)
  • the second vertical axis represents the graphs (2) and (3).
  • the third axis of the vertical axis represents the current ( ⁇ A) of graphs (4) to (7).
  • Graph (1) solid line with white squares
  • Vdc V
  • Graph (2) solid line with white triangles
  • Graph (3) (broken line with a black triangle) represents I1 (mA) in the case where the threshold correction circuit 150 is provided.
  • Graph (4) (broken line with a black circle) represents a threshold value (current threshold value) I14 ( ⁇ A) before correction.
  • a graph (5) (a one-dot chain line with a white square) represents the correction value I15 ( ⁇ A).
  • Graph (6) two-dot chain line with a black square
  • Graph (7) (solid line with white circles) represents a corrected threshold value (current threshold value) [I14 ⁇ I15 + I16] ( ⁇ A).
  • the current waveforms shown in graphs (2) to (7) include harmonic current components.
  • the threshold when the threshold correction circuit 150 is not provided is set by I14 shown in the graph (4).
  • the phase of I1 (I1 before correction) shown in the graph (2) is advanced with respect to Vdc shown in the graph (1), and the amplitude of the eleventh harmonic current is , which is 3.32% of the amplitude of the fundamental current.
  • the threshold value correction circuit 150 is provided, the threshold value is the correction value I15 indicated by the graph (5) and the correction value indicated by the graph (6), which is indicated by the graph (4).
  • a graph (7) of a value [I14 ⁇ I15 + I16] corrected by the value I16 is obtained.
  • I1 (I1 after correction) shown in the graph (3) suppresses the phase advance with respect to Vdc, and the amplitude of the harmonic current higher than the eleventh harmonic is 50 kHz (clock period: In the case of 20 ⁇ s), it was 2.6%, but it was less than this at other frequencies.
  • the PFC standard since the PFC standard is satisfied, it is not necessary to provide a low-pass filter for suppressing the harmonic current. That is, the harmonic current can be sufficiently suppressed without providing a low-pass filter.
  • FIG. 3 shows a circuit diagram of a second embodiment 200 of the power supply device of the present invention. In the second embodiment 200, a method of changing the threshold value I14 is used.
  • the second embodiment 200 is different from the first embodiment except that the threshold correction circuit 150 of the first embodiment 100 is not provided in the control circuit 240 and a Zener diode ZD241 is added to the control circuit 240.
  • the configuration is the same as that of the embodiment 100. That is, the configuration of the threshold generation circuit of the control circuit 240 is different from the configuration of the threshold generation circuit of the control circuit 140.
  • the components to which the symbols shown in FIG. 1 and symbols other than the numbers in the hundreds are attached are the components of the first embodiment 100 shown in FIG. 1. Is the same.
  • the charge / discharge charge amount of Cp due to the change in Vdc is 2/3 compared to the case where the Zener diode ZD241 is not provided, and the phase advance due to Cp is increased. Decrease to 2/3. Therefore, the phase advance in the case where the Zener diode ZD241 is provided (second embodiment) and Cp is set to 0.6 ⁇ f, the Zener diode ZD241 is not provided and Cp is set to 0.4 ⁇ f. It is the same as the phase lead when In other words, in this embodiment, Cp can be increased while suppressing an increase in phase advance due to an increase in Cp.
  • the integral value of Iref and the half cycle of Vdc is proportional to the area of the half cycle of Vdc.
  • the integral value of the half cycle of Vdc of Iref flowing in the region of [Vdc> VZD241] is a portion where Vdc is VZD241 or less from the area of the half cycle of Vdc. Is proportional to the area obtained by subtracting (subtracting) the area. When this area is calculated for the case where VZD 241 is set to 47 V, it becomes 53.25% of the area of the half cycle of Vdc.
  • the phase advance of I1 does not increase even though it decreases. If resistance value R241a is further reduced, I1 increases and the amplitude of the fundamental current increases. In this case, the amplitude ratio of the harmonic current to the amplitude of the fundamental wave current becomes small.
  • the correlation between Iref and (Vdc ⁇ VZD241) can be set to a correlation different from the proportionality. For example, a circuit in which a resistor and a Zener diode are connected in series is connected in parallel with the resistor R241.
  • the simulation was performed by setting the values of the circuit elements of the second embodiment 200 as follows.
  • Vac AC 100 V, 60 Hz, L1: 50 ⁇ H, L2: 600 ⁇ H, Cp: 0.6 ⁇ F, C1: 500 ⁇ F, clock cycle: 20 ⁇ s (H level period: 2 ⁇ s (when Vdc increases), 2 ⁇ s (when Vdc decreases)), VZD241: 48V, VLED average value: 15.4V, LED load current average value: 729 mA.
  • the power factor was 0.98 or more.
  • the amplitude of the 11th to 39th harmonic currents is 2% or less of the amplitude of the fundamental wave current, which satisfies the PFC standard.
  • the amplitude of the harmonic current above the 40th harmonic was 3.7% when the frequency was 8.3 kHz and 2.6% when the frequency was 50 kHz, but it was less than these at other frequencies. It was. In this case, since the PFC standard is satisfied, it is not necessary to provide a low-pass filter for suppressing the harmonic current. That is, by providing the Zener diode ZD241 in the threshold generation circuit, it is possible to obtain a phase advance suppression effect equivalent to that of the threshold correction circuit 150 of the first embodiment 100.
  • the power factor correction method of the second embodiment can also be used in combination with the threshold correction circuit 150 of the first embodiment. In this case, for example, in FIG. 1, a Zener diode is added between the resistors R141 and T149 to decrease the resistance value of the resistor R141.
  • FIG. 4 shows a circuit diagram of a third embodiment 300 of the power supply device of the present invention.
  • the inductor L131 of the first embodiment 100 is removed, and the inductor L331 is disposed between the inductor L332 and the capacitor C332.
  • the inductor L331 has the same inductance L1 as the inductance L1 of the inductor L131 of the first embodiment 100.
  • the inductance L2 of the inductor L332 is set to be larger than the inductance L1 of the inductor L331 as in the first embodiment 100.
  • FIG. 4 the constituent elements to which the symbols shown in FIG.
  • FIG. 4 does not show the threshold correction circuit of the first embodiment 100 or the threshold generation circuit of the second embodiment for correcting the waveform of I1 to bring the power factor close to “1”.
  • the threshold value correction circuit and the threshold value generation circuit may be provided. This is the same in other embodiments described below.
  • the third embodiment 300 operates as follows.
  • the switching element T331 When the switching element T331 is off, the charging current I1 of the capacitor C332 flows through the full-wave rectifier circuit 310, the inductor L332, the inductor L331, the capacitor C332, the fixed contact e of the changeover switch SW331, the normally closed contact f, and the ground path.
  • the switching element T331 When the switching element T331 is turned on, the capacitor C332, the inductor L331, the parallel circuit of the load 320 and the capacitor C331, the switching element T331, the current detection resistor R331, the ground and the switch SW331 fixed contact e and the normally closed contact f, A discharge current I2 of the capacitor C332 flows.
  • the current I4 (not shown) also flows through the full-wave rectifier circuit 310, the inductor L332, the parallel circuit of the load 320 and the capacitor C331, the switching element T331, the current detection resistor R331, and the ground path.
  • [inductance L2 of inductor L332 >> inductance L1 of inductor L331] is satisfied, [I2 >> I4] is satisfied.
  • the difference between the first embodiment 100 and the third embodiment 300 is that the amount of decrease in potential at the point r or t when the switching element is turned on is different.
  • the first embodiment 100 when the switching element T131 is turned on, the potential at the point r becomes the potential of the positive terminal of the capacitor C132, and therefore the amount of decrease is smaller than that in the third embodiment.
  • variation of the electric current which flows through the inductor L132 decreases.
  • the potential at the point r when the switching element T131 is on is likely to fluctuate. For this reason, the periodicity of the current flowing through the inductor L132 is disturbed, and fluctuations with a period longer than the clock period are likely to occur.
  • the potential at the point t when the switching element T331 is on is the load voltage VLED, and there is little fluctuation. Thereby, it is excellent in the periodicity of the electric current which flows through the inductor L332. On the other hand, since the amount of decrease in the potential at the point t when the switching element T331 is on is large, the amplitude of the harmonic current of the clock frequency becomes large.
  • FIG. 5 shows a circuit diagram of a fourth embodiment 400 of the power supply device of the present invention.
  • a switching element T431 and a current detection resistor R431 are arranged in series between one end 431 of the load 420 and the positive end c of the full-wave rectifier circuit 410.
  • the control circuit 440 includes P-type MOSFETs T441 to T443, T448 and T449, N-type MOSFETs T444 to T447, resistors R441 to R444, constant current source IDC441, clock signal generation circuit 441, Schmitt trigger ST451, and D flip-flop.
  • the circuit includes a DFF 441, an AND circuit AND441, and a drive circuit 442.
  • the power supply circuit 430, the control circuit 440, the power supply circuit 480, and the drive signal output circuit 490 control the switching element T431 disposed between one end 431 of the load 420 and the positive end c of the full-wave rectifier circuit 410. It is configured to be able to.
  • the operation of the fourth embodiment 400 is similar to the operation of the first embodiment 100.
  • the switching element T431 When the switching element T431 is off, the charging current of the capacitor C432 flows through the full-wave rectifier circuit 410, the capacitor C432, the inductor L432, and the ground path.
  • the switching element T431 When the switching element T431 is turned on, the discharge current of the capacitor C432 flows through the capacitor C432, the current detection resistor R431, the switching element T431, the parallel circuit of the load 420 and the capacitor C431, and the path of the inductor L431.
  • the voltage drop (current flowing through T431) of the current detection resistor R431 becomes larger than the threshold value, the switching element T431 is turned off.
  • the return current flows through the path of the inductor L431, the return diode D431, and the parallel circuit of the load 420 and the capacitor C431 due to the electromagnetic energy accumulated in the inductor L431.
  • the inductance L1 of the inductor L431 is set to such a magnitude that the return current disappears during the OFF period of the switching element T431.
  • the inductance L2 of the inductor L432 is set to such a magnitude that the charging current of the capacitor C432 continues to flow during the OFF period of the switching element T431.
  • the switching element T431 is disposed between one end (positive electrode end) 431 of the load 420 and the positive electrode end c of the full-wave rectifier circuit 410, the wiring downstream of the switching element T431 is grounded. Thus, when an overcurrent flows, the switching element T431 and the downstream wiring can be protected.
  • the positions of the inductor L431, the parallel circuit of the load 420 and the capacitor C431 may be switched.
  • the efficiency of the first to fourth embodiments is determined by the loss of the diode used in the full-wave rectifier circuit, the switching loss of the switching element, the loss of the current detection resistor, the loss of the freewheeling diode, and the like. Among these losses, the loss of the freewheeling diode and the diode of the full wave rectifier circuit is large. In particular, the loss of the return diode is large. This is because the current (I1) flowing through the diode of the full-wave rectifier circuit is smaller than the return current (I3) flowing through the freewheeling diode.
  • the return diode used in the first to fourth embodiments is replaced with a MOSFET parasitic diode.
  • FIG. 500 A circuit diagram of the fifth embodiment 500 is shown in FIG.
  • the freewheeling diode D131 of the first embodiment 100 is replaced with an FT532 that is an N-type MOSFET, and a freewheeling current is passed through a parasitic diode of the FT532.
  • FT532 is a simple symbol for distinguishing an FET used as a freewheeling diode from other FETs.
  • a voltage detection circuit 560 and a drive circuit 570 are added.
  • the fifth embodiment 500 has the same configuration as the first embodiment 100 except for the FT 532, the voltage detection circuit 560, the drive circuit 570, and the power supply circuit 580.
  • FIG. 6 shows only the main part of the fifth embodiment 500. Below, FT532 of this embodiment is mainly demonstrated.
  • the power supply circuit 580 includes an N-type MOSFET T581, a resistor R581, a Zener diode ZD581, and a capacitor C581, which are disposed between one end 531 and the other end 532 of the load 520.
  • the power supply circuit 580 supplies power to the voltage detection circuit 560 that detects the voltage between the drain and source of the FT 532 (the voltage between the anode and cathode of the parasitic diode) and the drive circuit 570 that drives the FT 532.
  • the voltage detection circuit 560 includes P-type MOSFETs T561, T563, and T566, N-type MOSFETs T562, T564, T565, and T567, resistors R561 to R564, and a DC power supply V560. Since the voltage between the terminals of the resistor R561 becomes a constant voltage, the current flowing through the resistor R561 becomes a constant current. T567 and DC power supply V560 are drain voltage inputs for preventing a large voltage generated between the drain and source of FT532 from being input to the source of T564 via resistors R564 and R563 when switching element T531 is turned on. A limiting circuit is configured. FETs having the same characteristics are used as T561 and T563, and FETs having the same characteristics are used as T562 and T564. In addition, resistors having the same resistance value are used as the resistors R562 and R563.
  • the drive circuit 570 includes P-type MOSFETs T571, T573, and T574, N-type MOSFETs T572, T575, and T576, resistors R571 to R576, a diode D561, a Zener diode ZD561, a Schmitt trigger ST571, and an astable multivibrator 1Shot571.
  • the voltage at point s in FIG. 1 is input to the trigger terminal Trig of 1 Shot 571 via ST571.
  • 1Shot 571 is reset when the voltage at point s input to the reset terminal R is at L level.
  • the switching element T531 shifts from on to off, the s-point voltage changes from the L level to the H level.
  • the non-inverted output + Q becomes H level for a certain time.
  • the “certain time” is set to a time shorter than the time from when the reflux current starts to flow until it disappears.
  • the clock period is about 30 ⁇ s, it is preferably set to about 3 ⁇ s.
  • the resistance values of the resistors R574 and R575 can be set such that the gate voltage of T574, that is, the connection voltage of the resistors R574 and R575 is lower than the source voltage of the FT532 at any value of Vdc. .
  • the switching element T531 is turned off, and then the T574 is turned on for about 3 ⁇ s. Thereby, T573 can be turned on during this period, the gate of FT532 is charged, and FT532 is turned on.
  • a certain time during which the non-inverted output + Q of 1 Shot 571 becomes H level corresponds to the “predetermined period” of the present invention.
  • the FT532 since there is an FT532 OFF delay, the FT532 is substantially turned OFF at a timing when the return current exceeds the zero cross and starts to flow in the reverse direction.
  • back electromotive force is generated in the inductor L531
  • the inductance of the inductor L531 and the capacitance between the drain and source of the FT532 resonate, and the drain-source voltage of the FT532 is hunted.
  • the FT 532 may be cut off before the return current reaches the zero cross.
  • a resistor R564 is provided. As the resistance value of the resistor R564 is increased, the cutoff timing is advanced.
  • T575 is turned on for about 3 ⁇ s.
  • the w point voltage which is the output of the voltage detection circuit 560 that detects the magnitude of the source-drain voltage of the FT 532, decreases, and T576 and T572 are turned off.
  • T575 is on, T573 is on.
  • a positive voltage is applied to the gate of FT532, the gate is charged, and FT532 is turned on.
  • T575 is turned off, so that T573 is turned off and voltage application to the gate of FT532 is stopped.
  • FIG. 7 shows the waveforms of the respective parts when the fifth embodiment 500 is simulated.
  • the simulation conditions are as follows.
  • AC voltage Vac 100 V, 60 Hz
  • capacitor C532 capacitance Cp 0.3 ⁇ F
  • load 520 LED stack (6 pieces) (Series ⁇ 6 parallel) (Series ⁇ 6 parallel) (Series ⁇ 6 parallel)
  • resistance value of resistor R561 300k ⁇
  • resistance value of resistor R564 500 ⁇
  • clock period 30 ⁇ s
  • 1 Shot 571 timer time 3 ⁇ s
  • the horizontal axis represents the elapsed time t (ms)
  • the first vertical axis represents the voltage (V) of the graphs (1) to (3)
  • the second vertical axis represents the graph (4).
  • (6) represents the voltage (V)
  • the third axis of the vertical axis represents the current (A) in the graph (7).
  • the graph (1) (the one-dot chain line with a white circle) represents the positive voltage (V: first axis) of the capacitor C531.
  • Graph (2) two-dot broken line with black circles
  • Graph (3) (broken line with a white triangle) represents the positive terminal voltage VCp (V: first axis) of the capacitor C532.
  • a graph (4) (a dashed-dotted line with a white square) represents a source-drain voltage (V: second axis) of T574.
  • a graph (5) (a dashed-dotted line with a black square) represents a gate-source voltage of FT532 (V: second axis).
  • Graph (6) (broken line with a black triangle) represents [w point ⁇ source voltage of FT532] (V: second axis).
  • Graph (7) (solid line) represents current IL1 (A: third axis) flowing through inductor L531.
  • the switching element T531 is turned on, and the current flowing through the inductor L531 increases linearly. At this time, most of the current IL1 of the inductor L131 is the discharge current I2 of the capacitor C532. Due to the discharge of the capacitor C532, the positive terminal voltage VCp of the capacitor C532 decreases. When IL1 reaches 5A, the switching element T531 is turned off.
  • the negative terminal voltage of the capacitor C531 that has dropped to the ground level when the switching element T531 is turned on rises rapidly due to the back electromotive force of the inductor L531, and exceeds the positive terminal voltage VCp of the capacitor C532.
  • the return current I3 flows through the path of the inductor L531, the parallel circuit of the load 520 and the capacitor C531, and the parasitic diode of the FT532.
  • the negative terminal voltage of the capacitor C531 is clamped to a voltage slightly exceeding the positive terminal voltage VCp of the capacitor C532. 1 Shot 571 turns on T574, and the source-drain voltage of T574 becomes zero for 3 ⁇ s after the switching element T531 is turned off.
  • FIG. 8 shows a circuit diagram of the sixth embodiment 600.
  • the sixth embodiment 600 has the same configuration as that of the first embodiment 100 except for the FT 632, the voltage detection circuit 660, the drive circuit 670, and the power supply circuit 680.
  • the components to which the symbols shown in FIG. 1 and symbols other than the numbers in the hundreds are the same are the components of the first embodiment 100 shown in FIG. 1. Is the same. Further, FIG. 8 shows only the main part of the sixth embodiment 600.
  • the inductor L631 is arranged on the negative electrode side from the parallel circuit of the load 620 and the capacitor C631. For this reason, a P-type MOSFET is used as the FT 632 to be replaced with the freewheeling diode.
  • the circuit for controlling the FT 632 of the sixth embodiment 600 is different in configuration from the circuit for controlling the FT 532 of the fifth embodiment 500, but the concept is the same.
  • the power supply circuit 680 includes a P-type MOSFET T681, a resistor R681, a Zener diode ZD681, and a capacitor C681.
  • the circuit that controls the FT 632 operates within a range lower than the Zener voltage of the Zener diode ZD681 with reference to the positive terminal voltage VCp of the capacitor C632.
  • the voltage detection circuit 660 includes P-type MOSFETs T661, T663, T666, and T667, N-type MOSFETs T662, T664, and T665, resistors R661 to R664, and a DC power supply V660.
  • the drive circuit 670 includes P-type MOSFETs T671 to T673, N-type MOSFETs T674 to T676, resistors R671 to R676, a Zener diode ZD671, a Schmitt trigger ST671, and an astable multivibrator 1Shot671.
  • T672 Since T672 is turned on, T675 is turned on, the gate voltage of FT632 is lower than the source voltage, and FT632 is turned on. When 3 ⁇ s elapses after the switching element T631 is turned off, T672 is turned off. At this time, since the gate charge of the FT 632 remains, the FT 632 is kept on. When the reflux current monotonously decreases and approaches the zero cross, the potential at the point x decreases and T673 is turned on. At the same time, since T671 and T674 are turned on, T675 remains off and FT632 is turned off. That is, the FT 632 is turned on immediately after the switching element T631 is turned off, and turned off before the return current reaches the zero cross. Thereby, the power loss of FT632 by return current can be reduced.
  • FIG. 9 shows a circuit diagram of a seventh embodiment 700 using another configuration for replacing the free wheel diode with a MOSFET parasitic diode.
  • the seventh embodiment 700 has the same configuration as that of the first embodiment 100 except for the FT 732, the voltage detection circuit 760, and the drive circuit 770.
  • the components to which the symbols shown in FIG. 1 and symbols other than the numbers in the hundreds are the same are the components of the first embodiment 100 shown in FIG. 1. Is the same.
  • FIG. 9 shows only the main part of the seventh embodiment 700.
  • the freewheeling diode is replaced with a parasitic diode of FT732 which is an N-type MOSFET.
  • the voltage detection circuit 760 includes P-type MOSFETs T761 and T763, N-type MOSFETs T762 and T764, resistors R761 to R764, diodes D761 and D762, and a Zener diode ZD761.
  • a first series circuit in which a diode D762, resistors R763 and T763, resistors R764 and T764 are arranged in series is arranged between the drain of the FT732 and the ground, and a current corresponding to the magnitude of the voltage between the drain of the FT732 and the ground It is configured to flow.
  • the source of FT732 -It is comprised so that the electric current according to the voltage difference between drains may flow.
  • FETs having the same characteristics are used as T761 and T763, and FETs having the same characteristics are used as T762 and T764.
  • the voltage drop generated in the resistor R762 is the voltage drop generated in the resistor R764. It is set to be smaller. In this case, the resistance value of the resistor R762 is smaller than the resistance value of the resistor R764.
  • the resistance value of the resistor R761 is equal to the resistance value of the resistor R763
  • the drain-source voltage of the FT732 is zero
  • the current flowing through the first series circuit is equal to the current flowing through the second series circuit.
  • the source voltage of FT732 becomes larger than the drain voltage
  • a larger current can flow in the second series circuit than in the first series circuit.
  • the source-drain voltage of T762 increases due to the principle of active load.
  • the voltage at the connection point z between T762 and the resistor R762 increases, and the output of the Schmitt trigger ST772 becomes H level.
  • a current having the same magnitude as the current flowing through the first series circuit flows through the second series circuit.
  • the expansion of the drain-source voltage of T762 is limited by the voltage drop generated in the resistor R762.
  • the limit width of the increase of the drain-source voltage at T762 becomes smaller as the difference between the resistance value of the resistor R762 and the resistance value of the resistor R764 is smaller.
  • the source voltage of the FT732 decreases to the ground voltage. As a result, no current flows through the second series circuit, and the voltage drop across the resistor R762 becomes zero.
  • the drain voltage of T761 becomes equal to the drain voltage of T762.
  • the source-drain voltage of T761 is expanded to the positive terminal voltage VCp of the capacitor C732.
  • the maximum value approaches the peak value of the AC voltage.
  • a Zener diode ZD761 is arranged between the drain of FT732 and the drain of T761 to limit the expansion of the source-drain voltage of T761.
  • the drive circuit 770 includes N-type MOSFETs T771 and T773 to T776, P-type MOSFETs T772, resistors R771 and R772, Schmitt triggers ST771 and ST772, an astable multivibrator 1 Shot 771, an AND circuit AND771, and a DC power supply V770. ing. T771 and T772 are arranged to constitute a push-pull circuit.
  • T771 is turned on, T772 is turned off, and FT732 is turned on.
  • the reflux current I3 decreases to zero
  • the potential at the z point decreases.
  • the output of ST772 becomes L level
  • T776 is turned off, and FT732 is turned off.
  • the potential at the z point is preferably lowered before the source-drain voltage of the FT 732 becomes zero.
  • the resistance value of the resistor R761 needs to be set slightly larger than the resistance value of the resistor R763.
  • the voltage of the DC power supply V770 is set to about 6V.
  • the breakdown voltage of T774 may be about 10V.
  • T761 and T762 that may increase the drain-source voltage can be protected by the resistor R762 and the Zener diode ZD761. It can be protected with T773. For this reason, the only FETs that require a large breakdown voltage are FT732 and T773.
  • each circuit is configured based on GND.
  • the breakdown voltage of FET used can be made into a voltage lower than an alternating voltage except FT732 and T773.
  • these circuits (except for FT732 and T773) can be incorporated in the same IC chip as the circuit for controlling on / off of the switching element T731.
  • the present invention is not limited to the configuration described in the detailed description, and various modifications, additions, and deletions can be made without departing from the gist of the present invention.
  • the power supply apparatus of the present invention can supply DC power to various loads other than the light emitting diode. It is preferable to use the threshold value correction circuit shown in FIG. 1 or the threshold value generation circuit shown in FIG. 3 to correct the waveform of I1 and bring the power factor close to “1”.
  • the correction circuit and the threshold generation circuit can be omitted. Even in this case, the power factor can be improved and the efficiency can be improved.
  • Each structure demonstrated by embodiment can also be used independently, and can also be used combining the plurality selected suitably.
  • the values (for example, inductance, capacitance, resistance value) of elements constituting each circuit can be appropriately set according to the type of load.
  • an FET is preferably used, but an element other than the FET can also be used.
  • DESCRIPTION OF SYMBOLS 10 ... AC power source, 100, 200, 300, 400, 500, 600, 700, 800 ... Power supply device, 110, 210, 310, 410, 810 ... Full wave rectifier circuit, 120, 220, 320, 420, 520, 620 , 720, 820... Load, 121, 221, 321, 421, 521, 621, 721, 821... Light emitting diode (LED), 130, 230, 330, 430, 830. , 840 ... control circuit, 141, 241 ... clock signal generation circuit, 142, 242, 442, 560, 660, 760 ... drive circuit, 150 ...
  • LED Light emitting diode
  • threshold correction circuit 180, 280, 380, 480, 580, 680 ... power supply circuit , 190, 290, 390, 490 ... drive signal output circuit, 560, 660, 760 ... voltage detection Road, 900 ... low-pass filter.

Abstract

[Problem] To provide a technology of improving efficiency of a power supply device that supplies a load with direct current power. [Solution] A control circuit (140) turns on a switching element (T131) in a set cycle. Consequently, a capacitor (C132) discharges electricity via a parallel circuit of an inductor (L131), a capacitor (C131), and a load (120). Furthermore, the control circuit (140) turns off the switching element (T131) when a current flowing in the switching element (T131) becomes higher than a threshold interlocking with the magnitude of a direct current voltage. Consequently, a reflux current flows via a diode (D131) and a parallel circuit of the inductor (L131), the capacitor (C131), and the load (120). Furthermore, while the switching element (T131) is turned off, the capacitor (C132) is charged via an inductor (L132). The inductance of the inductor (L132) is set to a value larger than the inductance of the inductor (L131).

Description

電源装置Power supply
 本発明は、負荷に直流電力を供給する電源装置に関し、特に、力率および効率を向上させることができる電源装置に関する。 The present invention relates to a power supply device that supplies DC power to a load, and more particularly to a power supply device that can improve power factor and efficiency.
 従来、負荷に直流電力を供給する電源装置として、特開平9-47024号公報に開示されている電源装置が知られている。図10に、従来の電源装置800の回路図が示されている。
 図10に示されている電源装置800は、全波整流回路810、ローパスフィル900、負荷820に直流電力を供給する電力供給回路830、制御回路840を備える降圧型AC-DCコンバータとして構成されている。全波整流回路810は、交流電源10の交流電圧Vacを全波整流して直流電圧(脈動直流電圧)Vdcに変換する。電力供給回路830のパワースイッチング素子T831として、N型MOSFETが用いられている。また、電力供給回路830は、高調波電流の振幅を制限値(「PFC規格」と呼ばれる)以下に抑制するための力率改善(PFC:Power Factor Correction)機能を有している。制御回路840は、設定周期でスイッチング素子T831をオンし、スイッチング素子T831のドレイン電流(電流検出抵抗R831の電圧降下)が閾値より大きくなるとスイッチング素子T831をオフする。
Conventionally, a power supply device disclosed in Japanese Patent Laid-Open No. 9-47024 is known as a power supply device that supplies DC power to a load. FIG. 10 shows a circuit diagram of a conventional power supply device 800.
The power supply device 800 shown in FIG. 10 is configured as a step-down AC-DC converter including a full-wave rectifier circuit 810, a low-pass filter 900, a power supply circuit 830 that supplies DC power to a load 820, and a control circuit 840. Yes. Full-wave rectification circuit 810 performs full-wave rectification on AC voltage Vac of AC power supply 10 and converts it into DC voltage (pulsating DC voltage) Vdc. An N-type MOSFET is used as the power switching element T831 of the power supply circuit 830. In addition, the power supply circuit 830 has a power factor correction (PFC) function for suppressing the amplitude of the harmonic current below a limit value (referred to as “PFC standard”). The control circuit 840 turns on the switching element T831 in the set cycle, and turns off the switching element T831 when the drain current of the switching element T831 (voltage drop of the current detection resistor R831) becomes larger than the threshold value.
 図10に示されている電源装置800では、スイッチング素子T831がオンすると、全波整流回路810、ローパスフィルタ900、インダクタL831、負荷820とコンデンサC831の並列回路、スイッチング素子T831、電流検出抵抗R831および接地(グラウンド)の経路で電流I1が流れる。この時、インダクタL831(インダクタンスL)に、電磁エネルギーが蓄積される。そして、スイッチング素子T831がオフすると、インダクタL831に蓄積された電磁エネルギーにより、インダクタL831、負荷820とコンデンサC831の並列回路、ダイオードD831(「還流ダイオード」あるいは「フリーホイールダイオード」と呼ばれる)の経路で還流電流I3が流れる。 In power supply device 800 shown in FIG. 10, when switching element T831 is turned on, full-wave rectifier circuit 810, low-pass filter 900, inductor L831, a parallel circuit of load 820 and capacitor C831, switching element T831, current detection resistor R831, and A current I1 flows through a ground path. At this time, electromagnetic energy is accumulated in the inductor L831 (inductance L). When the switching element T831 is turned off, the electromagnetic energy accumulated in the inductor L831 causes the inductor L831, the parallel circuit of the load 820 and the capacitor C831, and the path of the diode D831 (referred to as “freewheel diode” or “freewheel diode”). A reflux current I3 flows.
 図10に示されている電源装置800では、電流I1の大きさ(振幅)が直流電圧Vdcの大きさ(振幅)に連動する。これにより、交流入力電力の力率cosθ(θ:交流電圧Vacと交流入力電流Iacの位相差)が「1」に近づく。
 なお、スイッチング素子T831がオフの間は電流I1が遮断される。すなわち、電流I1は、間欠的に流れる。このため、電流I1に高調波電流が含まれる。この高調波電流が交流電源側に伝搬するのを防止するためにローパスフィルタ900が設けられている。
In the power supply device 800 shown in FIG. 10, the magnitude (amplitude) of the current I1 is linked to the magnitude (amplitude) of the DC voltage Vdc. As a result, the power factor cos θ (θ: phase difference between the AC voltage Vac and the AC input current Iac) of the AC input power approaches “1”.
The current I1 is cut off while the switching element T831 is off. That is, the current I1 flows intermittently. For this reason, the harmonic current is included in the current I1. A low-pass filter 900 is provided in order to prevent this harmonic current from propagating to the AC power supply side.
特開平9-47024号公報JP-A-9-47024
 従来の電源装置800に設けられているローパスフィルタ900は、力率の悪化を防止するために、小さい容量を有するコンデンサと大きいインダクタンスを有するインダクタにより構成されている。大きいインダクタンスを有するインダクタは、導線の巻数が多くなる。ここで、太い導線を用いてインダクタを形成するとインダクタが大型になるため、細い導線を用いて形成する必要がある。一方、細い導線を用いてインダクタを形成すると、インダクタの抵抗値が大きくなり、インダクタの損失が増加する。
 このように、従来の電源装置は、高調波電流が交流電源側に伝搬するのを防止するためのローパスフィルタを構成するインダクタの損失が大きいため、効率を向上させるには限界があった。
 本発明は、このような点に鑑みて創案されたものであり、力率を改善することができるとともに、効率を向上させることができる電源装置を提供することを目的とする。
The low-pass filter 900 provided in the conventional power supply device 800 includes a capacitor having a small capacitance and an inductor having a large inductance in order to prevent the power factor from deteriorating. An inductor having a large inductance has a large number of turns of the conductive wire. Here, when an inductor is formed using a thick conducting wire, the inductor becomes large, and thus it is necessary to form the inductor using a thin conducting wire. On the other hand, when an inductor is formed using a thin conducting wire, the resistance value of the inductor increases and the loss of the inductor increases.
As described above, the conventional power supply apparatus has a limit in improving the efficiency because the loss of the inductor constituting the low-pass filter for preventing the harmonic current from propagating to the AC power supply side is large.
The present invention has been made in view of such a point, and an object of the present invention is to provide a power supply device capable of improving the power factor and improving the efficiency.
 本発明は、交流電源からの交流電圧を直流電圧に変換する整流回路、負荷に直流電力を供給する電力供給回路、電力供給回路を制御する制御回路を備えている。
 整流回路は、交流電圧を直流電圧(脈動直流電圧)に変換し、変換した直流電圧を正極端と負極端の間に発生する。整流回路としては、典型的には、全波整流回路が用いられる。「正極端」および「負極端」という用語は、直流電圧が発生する箇所を表す用語として用いられている。
 電力供給回路は、第1および第2のコンデンサ、第1および第2のインダクタ、ダイオード、スイッチング素子を有している。
 第1の発明では、整流回路の正極端と負極端の間に、第2のインダクタと第2のコンデンサが直列に配置されている。第2のコンデンサの端子間には、第1のインダクタ、負荷と第1のコンデンサの並列回路およびスイッチング素子が直列に配置されている。第1のインダクタおよび負荷と第1のコンデンサの並列回路との直列回路には、ダイオード(還流ダイオード)が並列に配置されている。
 第2のインダクタのインダクタンスは、第1のインダクタのインダクタンスより大きな値に設定されている。
 そして、制御回路は、設定周期でスイッチング素子をオンし、スイッチング素子を流れる電流が直流電圧の大きさに連動する閾値より大きくなるとスイッチング素子オフするように構成されている。「直流電圧の大きさに連動する閾値」としては、典型的には、「直流電圧の大きさ(振幅)に比例する閾値」が用いられる。
 これにより、スイッチング素子がオフすると、整流回路の直流電圧により第2のコンデンサが充電される。また、スイッチング素子がオンすると、第2のコンデンサは、第1のインダクタ、負荷およびスイッチング素子からなる経路で放電する。なお、スイッチング素子がオフすると、スイッチング素子のオン時に第1のインダクタに蓄積された電磁エネルギーは、第1のインダクタ、負荷およびダイオードからなる経路で流れる還流電流に変換される。
 第2の発明では、整流回路の正極端と負極端の間には、第2のインダクタ、第1のインダクタおよび第2のコンデンサが直列に配置されている。第1のインダクタと第2のコンデンサの直列回路の両端には、負荷と第1のコンデンサの並列回路およびスイッチング素子が直列に配置されている。第1のインダクタおよび負荷と第1のコンデンサの並列回路との直列回路には、ダイオード(還流ダイオード)が並列に配置されている。
 第2のインダクタのインダクタンスは、第1のインダクタのインダクタンスより大きな値に設定されている。
 そして、制御回路は、第1の発明と同様に、設定周期でスイッチング素子をオンし、スイッチング素子を流れる電流が直流電圧の大きさに連動する閾値より大きくなるとスイッチング素子をオフするように構成されている。
 これにより、スイッチング素子がオフすると、整流回路の直流電圧により第2のコンデンサが充電される。また、スイッチング素子がオンすると、第2のコンデンサは、第1のインダクタ、負荷およびスイッチング素子からなる経路で放電する。なお、スイッチング素子がオフすると、スイッチング素子のオン時に第1のインダクタに蓄積された電磁エネルギーは、第1のインダクタ、負荷およびダイオードからなる経路で流れる還流電流に変換される。
 第1および第2の発明では、スイッチング素子の各制御周期間(オン期間+オフ期間)に流れる交流入力電流の変動を抑制することができるとともに、交流入力電流を交流電圧に同期させることができる。これにより、高調波電流の発生を抑制することができ、高調波電流が交流側に伝搬するのを防止するためのローパスフィルタを除去することができ、あるいは、ローパスフィルタを構成するインダクタのインダクタンスを低減することができる。すなわち、本発明の電源装置は、力率を改善することができるとともに、効率を向上させることができる。
 第1の発明の異なる形態では、制御装置は、クロック周期毎に処理を実行するように構成されている。そして、直流電圧が増加過程にあるときには、閾値から、クロック周期間における直流電圧の増加分による第2のコンデンサの充電電荷量に対応する値を減算した値を閾値とし、直流電圧が減少過程にあるときには、閾値に、クロック周期間における直流電圧の減少分による第2のコンデンサの放電電荷量に対応する値を加算した値を閾値とする。
 本形態では、第2のコンデンサの容量を増大して高調波電流の発生をより抑制することができるため、高調波電流が交流側に伝搬するのを防止するためのローパスフィルタを除去することができる。これにより、本発明の電源装置は、力率を改善することができるとともに、効率をより向上させることができる。
 第1の発明の他の異なる形態では、閾値は、直流電圧の大きさから設定値を減算した値に連動するように構成されている。そして、制御装置は、直流電圧の大きさが設定値より小さい場合にはスイッチング素子をオフ状態に保持する。
 本形態では、直流電圧(脈動直流電圧)が設定値より低下しないようにスイッチング素子を制御しているため、直流電圧の増加時に第2のコンデンサに充電される電荷と、直流電圧の減少時にスイッチング素子のオン時に第2のコンデンサから放電される電荷の絶対値の和が減少し、第2のコンデンサによる位相進みが抑制される。そして、その分、第2のコンデンサの容量を増大させることができる。これにより、高調波電流の発生をより抑制することができるため、高調波電流が交流側に伝搬するのを防止するためのローパスフィルタを除去することができる。
 第1および第2の発明の他の異なる形態では、第2のコンデンサに直列に配置可能な第3のコンデンサを有している。好適には、第3のコンデンサを第2のコンデンサに直列接続し、あるいは、第3のコンデンサと第2のコンデンサの接続を解除する切り替えスイッチが用いられる。
 例えば、第2のコンデンサの容量が所定値に設定されている状態で、閾値を変更して負荷に供給する直流電力を減少させると、力率が悪化することがある。本形態では、このような場合には、第3のコンデンサを第2のコンデンサに直列に接続して合成容量を小さくすることによって、力率の悪化を防止することができる。
 第1および第2の発明の他の異なる形態では、ダイオード(還流ダイオード)としてMOSFETの寄生ダイオードが用いられている。そして、制御回路は、スイッチング素子がオフしてから設定期間内で、かつ、寄生ダイオードのカソード電圧が、アノード電圧から第1の設定値を減算した値より小さくなるとMOSFETをオンし、設定期間経過後で、かつ、寄生ダイオードのカソード電圧が、アノード電圧から第1の設定値を減算した値より大きくなるとMOSFETをオフするように構成されている。設定期間は、MOSFETの寄生ダイオードに還流電流が流れ始めてから消滅するまでの期間より短い期間に設定される。
 本形態では、還流電流をMOSFETの寄生ダイオードを介して流すとき、MOSFETをオンするように構成されているため、還流電流を還流ダイオードを介して流す場合に較べて電力損失が減少し、効率を向上させることができる。
 還流電流をMOSFETの寄生ダイオードを介して流す場合、MOSFETのオン、オフタイミングを判断するために寄生ダイオードのアノードとカソード間の電圧を検出する電圧検出回路を用いるのが好ましい。
 第1および第2発明の他の異なる形態では、FETにより構成される第1および第2のソースフォロア回路を有する電圧検出回路が用いられている。
 第1のソースフォロア回路のソース抵抗は、寄生ダイオードのアノードに接続され、第2のソースフォロア回路のソース抵抗は、寄生ダイオードのカソードに接続される。第1および第2のソースフォロア回路のFETのゲートには、共通のバイアス電圧が印加される。
 本形態では、寄生ダイオードのアノードとカソード間の電圧が、第1のソースフォロア回路を流れる電流と第2のソースフォロア回路を流れる電流の差に変換される。
 第1および第2の発明の他の異なる形態では、第1および第2の回路を有する電圧検出回路が用いられている。
 第1の回路は、寄生ダイオードのカソードと接地間に直列に配置されるダイオード、第1の抵抗、第1のPMOSFET、第2の抵抗および第1のNMOSFETにより構成される。第1のPMOSFETのゲートとドレインが短絡され、第1のNMOSFETのゲートとドレインが短絡されている。第2の回路は、寄生ダイオードのアノードと接地間に直列に配置されるダイオード、第3の抵抗、第2のPMOSFET、第4の抵抗および第2のNMOSFETにより構成される。第2のPMOSFETのゲートは、第1のPMOSFETのゲートに接続され、第2のNMOSFETのゲートは、第1のNMOSFETのゲートに接続されている。第2のPMOSFETおよび第2のNMOSFETの特性は、それぞれ第1のPMOSFETおよび第1のNMOSFETと同じ特性を有している。第4の抵抗の抵抗値は、第2の抵抗の抵抗値より小さくなるように設定されている。第3の抵抗の抵抗値は、第1の抵抗の抵抗値に等しいかあるいは大きくなるように設定されている。
 本形態では、第2のNMOSFETのドレイン電圧が、寄生ダイオードのアノードとカソード間の電圧に応じて変化するように構成されている。
The present invention includes a rectifier circuit that converts an AC voltage from an AC power source into a DC voltage, a power supply circuit that supplies DC power to a load, and a control circuit that controls the power supply circuit.
The rectifier circuit converts an AC voltage into a DC voltage (pulsating DC voltage), and generates the converted DC voltage between the positive electrode end and the negative electrode end. As the rectifier circuit, a full-wave rectifier circuit is typically used. The terms “positive electrode end” and “negative electrode end” are used as terms representing locations where a DC voltage is generated.
The power supply circuit includes first and second capacitors, first and second inductors, diodes, and switching elements.
In the first invention, the second inductor and the second capacitor are arranged in series between the positive terminal and the negative terminal of the rectifier circuit. Between the terminals of the second capacitor, a first inductor, a parallel circuit of a load and a first capacitor, and a switching element are arranged in series. A diode (freewheeling diode) is arranged in parallel in the series circuit of the first inductor and load and the parallel circuit of the first capacitor.
The inductance of the second inductor is set to a value larger than the inductance of the first inductor.
The control circuit is configured to turn on the switching element at a set cycle, and to turn off the switching element when the current flowing through the switching element becomes greater than a threshold linked to the magnitude of the DC voltage. As the “threshold value linked to the magnitude of the DC voltage”, a “threshold value proportional to the magnitude (amplitude) of the DC voltage” is typically used.
Thereby, when the switching element is turned off, the second capacitor is charged by the DC voltage of the rectifier circuit. Further, when the switching element is turned on, the second capacitor is discharged through a path including the first inductor, the load, and the switching element. When the switching element is turned off, the electromagnetic energy accumulated in the first inductor when the switching element is turned on is converted into a return current that flows through a path including the first inductor, the load, and the diode.
In the second invention, the second inductor, the first inductor, and the second capacitor are arranged in series between the positive terminal and the negative terminal of the rectifier circuit. A parallel circuit of a load and a first capacitor and a switching element are arranged in series at both ends of the series circuit of the first inductor and the second capacitor. A diode (freewheeling diode) is arranged in parallel in the series circuit of the first inductor and load and the parallel circuit of the first capacitor.
The inductance of the second inductor is set to a value larger than the inductance of the first inductor.
The control circuit is configured to turn on the switching element at a set cycle and turn off the switching element when the current flowing through the switching element becomes greater than a threshold linked to the magnitude of the DC voltage, as in the first invention. ing.
Thereby, when the switching element is turned off, the second capacitor is charged by the DC voltage of the rectifier circuit. Further, when the switching element is turned on, the second capacitor is discharged through a path including the first inductor, the load, and the switching element. When the switching element is turned off, the electromagnetic energy accumulated in the first inductor when the switching element is turned on is converted into a return current that flows through a path including the first inductor, the load, and the diode.
In the first and second inventions, fluctuations in the AC input current flowing during each control cycle (ON period + OFF period) of the switching element can be suppressed, and the AC input current can be synchronized with the AC voltage. . As a result, the generation of harmonic current can be suppressed, the low-pass filter for preventing the harmonic current from propagating to the AC side can be removed, or the inductance of the inductor constituting the low-pass filter can be reduced. Can be reduced. That is, the power supply device of the present invention can improve the power factor and the efficiency.
In a different form of the first invention, the control device is configured to execute the processing every clock cycle. When the DC voltage is in the increasing process, a value obtained by subtracting a value corresponding to the charge amount of the second capacitor due to the increase in the DC voltage during the clock period from the threshold is used as the threshold, and the DC voltage is in the decreasing process. In some cases, the threshold value is a value obtained by adding a value corresponding to the discharge charge amount of the second capacitor due to the decrease in the DC voltage during the clock cycle.
In this embodiment, since the generation of the harmonic current can be further suppressed by increasing the capacity of the second capacitor, it is possible to remove the low-pass filter for preventing the harmonic current from propagating to the AC side. it can. Thereby, the power supply device of this invention can improve a power factor while improving a power factor more.
In another different form of the first invention, the threshold value is configured to be linked to a value obtained by subtracting the set value from the magnitude of the DC voltage. Then, when the magnitude of the DC voltage is smaller than the set value, the control device holds the switching element in the off state.
In this embodiment, since the switching element is controlled so that the DC voltage (pulsating DC voltage) does not fall below the set value, the charge charged in the second capacitor when the DC voltage increases and the switching when the DC voltage decreases. The sum of absolute values of electric charges discharged from the second capacitor when the element is turned on is reduced, and the phase advance by the second capacitor is suppressed. Then, the capacity of the second capacitor can be increased accordingly. Thereby, since generation | occurrence | production of a harmonic current can be suppressed more, the low pass filter for preventing a harmonic current from propagating to the alternating current side can be removed.
In another different form of the first and second inventions, a third capacitor that can be arranged in series with the second capacitor is provided. Preferably, a changeover switch for connecting the third capacitor in series with the second capacitor or for disconnecting the connection between the third capacitor and the second capacitor is used.
For example, if the DC power supplied to the load is decreased by changing the threshold value in a state where the capacity of the second capacitor is set to a predetermined value, the power factor may deteriorate. In the present embodiment, in such a case, the power factor can be prevented from deteriorating by connecting the third capacitor in series with the second capacitor to reduce the combined capacitance.
In another different form of the first and second inventions, a MOSFET parasitic diode is used as the diode (freewheeling diode). Then, the control circuit turns on the MOSFET within a set period after the switching element is turned off and when the cathode voltage of the parasitic diode becomes smaller than a value obtained by subtracting the first set value from the anode voltage, and the set period elapses. Later, when the cathode voltage of the parasitic diode becomes larger than the value obtained by subtracting the first set value from the anode voltage, the MOSFET is turned off. The setting period is set to a period shorter than the period from when the return current starts to flow through the parasitic diode of the MOSFET until it disappears.
In this embodiment, when the return current is passed through the MOSFET's parasitic diode, the MOSFET is turned on, so that the power loss is reduced and the efficiency is reduced as compared with the case where the return current is passed through the return diode. Can be improved.
In the case where the reflux current is passed through the parasitic diode of the MOSFET, it is preferable to use a voltage detection circuit that detects the voltage between the anode and the cathode of the parasitic diode in order to determine the on / off timing of the MOSFET.
In another different form of the first and second inventions, a voltage detection circuit having first and second source follower circuits constituted by FETs is used.
The source resistance of the first source follower circuit is connected to the anode of the parasitic diode, and the source resistance of the second source follower circuit is connected to the cathode of the parasitic diode. A common bias voltage is applied to the gates of the FETs of the first and second source follower circuits.
In this embodiment, the voltage between the anode and the cathode of the parasitic diode is converted into a difference between the current flowing through the first source follower circuit and the current flowing through the second source follower circuit.
In another different form of the first and second inventions, a voltage detection circuit having first and second circuits is used.
The first circuit includes a diode arranged in series between the cathode of the parasitic diode and the ground, a first resistor, a first PMOSFET, a second resistor, and a first NMOSFET. The gate and drain of the first PMOSFET are short-circuited, and the gate and drain of the first NMOSFET are short-circuited. The second circuit includes a diode arranged in series between the anode of the parasitic diode and the ground, a third resistor, a second PMOSFET, a fourth resistor, and a second NMOSFET. The gate of the second PMOSFET is connected to the gate of the first PMOSFET, and the gate of the second NMOSFET is connected to the gate of the first NMOSFET. The characteristics of the second PMOSFET and the second NMOSFET have the same characteristics as the first PMOSFET and the first NMOSFET, respectively. The resistance value of the fourth resistor is set to be smaller than the resistance value of the second resistor. The resistance value of the third resistor is set to be equal to or greater than the resistance value of the first resistor.
In this embodiment, the drain voltage of the second NMOSFET is configured to change according to the voltage between the anode and the cathode of the parasitic diode.
 本発明の電源装置は、力率を改善することができるとともに、効率を向上させることができる。
 本発明の他の特徴、作用および効果は、本明細書、特許請求の範囲、添付図面を参照することで直ちに理解することができる。
The power supply device of the present invention can improve the power factor and the efficiency.
Other features, functions, and advantages of the present invention can be readily understood with reference to the specification, claims, and accompanying drawings.
本発明の電源装置の第1の実施形態の回路図である。It is a circuit diagram of a 1st embodiment of a power supply device of the present invention. 閾値補正回路を用いた場合のシミュレーション結果を示す図である。It is a figure which shows the simulation result at the time of using a threshold value correction circuit. 本発明の電源装置の第2の実施形態の回路図である。It is a circuit diagram of 2nd Embodiment of the power supply device of this invention. 本発明の電源装置の第3の実施形態の回路図である。It is a circuit diagram of 3rd Embodiment of the power supply device of this invention. 本発明の電源装置の第4の実施形態の回路図である。It is a circuit diagram of 4th Embodiment of the power supply device of this invention. 本発明の電源装置の第5の実施形態の回路図である。It is a circuit diagram of a 5th embodiment of a power supply device of the present invention. 第5の実施形態の電源装置のシミュレーション結果を示す図である。It is a figure which shows the simulation result of the power supply device of 5th Embodiment. 本発明の電源装置の第6の実施形態の回路図である。It is a circuit diagram of 6th Embodiment of the power supply device of this invention. 本発明の電源装置の第7の実施形態の回路図である。It is a circuit diagram of a seventh embodiment of the power supply device of the present invention. 従来の電源装置の回路図である。It is a circuit diagram of the conventional power supply device.
 以下の詳細な説明は、本発明の好ましい適用例を実施するための詳細情報を当業者に教示するに留まり、本発明の技術的範囲は、詳細な説明によって制限されず、特許請求の範囲の記載に基づいて定められる。このため、以下の詳細な説明における構成や方法の組み合わせは、広義の意味において、本発明を実施するのに全て必須であるというものではなく、添付図面の参照番号とともに記載された詳細な説明において、本発明の代表的形態を開示するに留まるものである。 The following detailed description is merely to provide those skilled in the art with detailed information for implementing the preferred embodiments of the present invention, and the technical scope of the present invention is not limited by the detailed description. Determined based on the description. For this reason, combinations of configurations and methods in the following detailed description are not all essential to implement the present invention in a broad sense, but in the detailed description described with reference numerals in the accompanying drawings. However, the present invention only discloses typical embodiments of the present invention.
 以下に、本発明の実施形態を、図面を参照しながら説明する。
 以下では、交流電圧を直流電圧に変換する全波整流回路を備え、発光ダイオード(LED)を有する負荷に直流電力を供給する降圧型AC-DCコンバータとして構成した場合について説明する。勿論、本発明の電源装置は、LED負荷以外の種々の負荷に直流電力を供給する電源装置として用いることができる。
 また、「電圧」、「電流」という記載は、特に断りがない限り、それぞれ「電圧の大きさ(振幅)」、「電流の大きさ(振幅)」を意味するものとして用いている。
Embodiments of the present invention will be described below with reference to the drawings.
Hereinafter, a case will be described in which a full-wave rectifier circuit that converts an AC voltage into a DC voltage is provided and configured as a step-down AC-DC converter that supplies DC power to a load having a light emitting diode (LED). Of course, the power supply device of the present invention can be used as a power supply device that supplies DC power to various loads other than LED loads.
Further, the terms “voltage” and “current” are used to mean “voltage magnitude (amplitude)” and “current magnitude (amplitude)”, respectively, unless otherwise specified.
[第1の実施形態]
 図1に、本発明の電源装置の第1の実施形態100の回路図が示されている。第1の実施形態の電源装置100は、交流電源10からの交流電圧Vacを直流電圧Vdcに変換する全波整流回路110、電力供給回路130、制御回路140、電源回路180および駆動信号出力回路190により構成されている。制御回路140は、閾値補正回路150を有している。
 全波整流回路110は、ブリッジ接続された複数のダイオードD111~D114を有し、交流入力端aおよびb間に印加される交流電圧Vacを全波整流し、正極端cおよび負極端d間に直流電圧Vdcを発生する。なお、直流電圧Vdcは、交流電圧Vacの大きさ(振幅)に応じて変化する大きさ(振幅)を有する脈動直流電圧である。
 本実施形態では、全波整流回路110の負極端dが接地されている。このため、いずれかの端子を接地することは、当該端子を負極端dに接続することを意味する。
[First Embodiment]
FIG. 1 shows a circuit diagram of a first embodiment 100 of the power supply device of the present invention. The power supply device 100 according to the first embodiment includes a full-wave rectifier circuit 110 that converts an AC voltage Vac from an AC power supply 10 into a DC voltage Vdc, a power supply circuit 130, a control circuit 140, a power supply circuit 180, and a drive signal output circuit 190. It is comprised by. The control circuit 140 has a threshold correction circuit 150.
The full-wave rectifier circuit 110 has a plurality of diodes D111 to D114 connected in a bridge, full-wave rectifies the AC voltage Vac applied between the AC input terminals a and b, and between the positive terminal c and the negative terminal d. A DC voltage Vdc is generated. The DC voltage Vdc is a pulsating DC voltage having a magnitude (amplitude) that changes in accordance with the magnitude (amplitude) of the AC voltage Vac.
In the present embodiment, the negative terminal d of the full wave rectifier circuit 110 is grounded. For this reason, grounding any of the terminals means connecting the terminal to the negative electrode end d.
 電力供給回路130は、全波整流回路110の正極端cおよび負極端dと負荷120の一方端131および他方端132間に配置され、負荷120に直流電力を供給する。以下に電力供給回路130の構成を説明する。
 負荷120の一方端131と他方端132の間に、容量C1を有するコンデンサC131が配置されている。
 負荷120の一方端131と正極端cの間には、インダクタンスL1を有するインダクタL131とインダクタンスL2を有するインダクタL132が直列に配置されている。この時、インダクタL131が一方端131に接続され、インダクタL132が正極端cに接続される。
The power supply circuit 130 is disposed between the positive end c and the negative end d of the full-wave rectifier circuit 110 and one end 131 and the other end 132 of the load 120, and supplies DC power to the load 120. The configuration of the power supply circuit 130 will be described below.
A capacitor C131 having a capacitance C1 is disposed between one end 131 and the other end 132 of the load 120.
Between the one end 131 and the positive end c of the load 120, an inductor L131 having an inductance L1 and an inductor L132 having an inductance L2 are arranged in series. At this time, the inductor L131 is connected to one end 131, and the inductor L132 is connected to the positive end c.
 負荷120の他方端132と接地の間には、スイッチング素子T131と電流検出抵抗R131が直列に配置されている。本実施形態では、スイッチング素子T131として、N型MOSFETが用いられている。
 インダクタL131とインダクタL132の接続点rと、切り替えスイッチSW131の固定接点eの間に、容量Cpを有するコンデンサC132が配置されている。切り替えスイッチSW131の常閉接点fは、接地され、常開接点gは、容量Cp1を有するコンデンサC133を介して接地されている。
 負荷120の他方端132と接続点rの間には、ダイオードD131が配置されている。この時、ダイオードD131のアノードが他方端132に接続され、カソードが接続点rに接続される。
A switching element T131 and a current detection resistor R131 are arranged in series between the other end 132 of the load 120 and the ground. In the present embodiment, an N-type MOSFET is used as the switching element T131.
A capacitor C132 having a capacitance Cp is arranged between a connection point r between the inductor L131 and the inductor L132 and a fixed contact e of the changeover switch SW131. The normally closed contact f of the changeover switch SW131 is grounded, and the normally open contact g is grounded via a capacitor C133 having a capacitance Cp1.
A diode D131 is arranged between the other end 132 of the load 120 and the connection point r. At this time, the anode of the diode D131 is connected to the other end 132, and the cathode is connected to the connection point r.
 コンデンサC131が、本発明の「第1のコンデンサ」に対応し、コンデンサC132が、本発明の「第2のコンデンサ」に対応し、コンデンサC133が、本発明の「第3のコンデンサ」に対応し、インダクタL131が、本発明の「第1のインダクタ」に対応し、インダクタL132が、本発明の「第2のインダクタ」に対応する。 The capacitor C131 corresponds to the “first capacitor” of the present invention, the capacitor C132 corresponds to the “second capacitor” of the present invention, and the capacitor C133 corresponds to the “third capacitor” of the present invention. The inductor L131 corresponds to the “first inductor” of the present invention, and the inductor L132 corresponds to the “second inductor” of the present invention.
 電源回路180は、正極端cと接地の間に配置され、抵抗R181、ツェナーダイオードZD181およびコンデンサC181により構成されている。電源回路180は、ツェナーダイオードZD181のツェナー電圧により定まる電圧Vzdを制御回路140および駆動信号出力回路190に印加する。
 駆動信号出力回路190は、電圧Vzdと接地の間に配置され、スイッチSW191、抵抗R191およびR192により構成されている。駆動信号出力回路190は、スイッチSW191がオンされると、負荷120への直流電力の供給の開始を指示するHレベルの駆動信号を制御回路140に出力する。
The power supply circuit 180 is disposed between the positive terminal c and the ground, and includes a resistor R181, a Zener diode ZD181, and a capacitor C181. The power supply circuit 180 applies a voltage Vzd determined by the Zener voltage of the Zener diode ZD181 to the control circuit 140 and the drive signal output circuit 190.
The drive signal output circuit 190 is disposed between the voltage Vzd and the ground, and includes a switch SW191 and resistors R191 and R192. When the switch SW191 is turned on, the drive signal output circuit 190 outputs an H level drive signal that instructs the start of supply of DC power to the load 120 to the control circuit 140.
 制御回路140は、P型MOSFETであるT141、T142、T146、T147、N型MOSFETであるT143~T145、T148、T149、抵抗R141~R144、定電流源IDC141、クロック信号発生回路141、シュミットトリガーST141、DフリップフロップDFF141、AND回路AND141、駆動回路142、閾値補正回路150により構成されている。 The control circuit 140 includes P-type MOSFETs T141, T142, T146, and T147, N-type MOSFETs T143 to T145, T148, and T149, resistors R141 to R144, a constant current source IDC141, a clock signal generation circuit 141, and a Schmitt trigger ST141. , D flip-flop DFF 141, AND circuit AND 141, drive circuit 142, and threshold correction circuit 150.
 抵抗R141とT149の直列回路を流れる電流Irefの大きさは、直流電圧Vdcの大きさ(振幅)にほぼ比例する。T148とT149およびT146とT147は、カレントミラー回路を構成するように配置されている。T146のドレイン電流をI14とする。T146~T149および抵抗R141により、閾値(電流閾値)I14を発生する閾値発生回路が構成されている。
 定電流源IDC141からの定電流I11がT145および抵抗R144に流れることによって、T145のゲートが定電圧となる。T145のゲート電圧は、バイアス電圧として用いられる。T144と抵抗R143により第1のソースフォロア回路が形成され、電流I12が、T142および第1のソースフォロア回路を流れる。T143と抵抗R142により第2のソースフォロア回路が形成され、電流I13が、T141、第2のソースフォロ回路および電流検出抵抗R131を流れる。
 なお、T143、T144およびT145として、同じ特性を有するN型MOSFETが用いられる。また、抵抗R142、R143およびR144として、等しい抵抗値を有する抵抗が用いられる。また、抵抗R142の抵抗値は、電流検出抵抗R131の抵抗値が抵抗R142の抵抗値に比べて無視できる値に設定される。
The magnitude of the current Iref flowing through the series circuit of the resistors R141 and T149 is substantially proportional to the magnitude (amplitude) of the DC voltage Vdc. T148 and T149 and T146 and T147 are arranged to form a current mirror circuit. Let the drain current of T146 be I14. A threshold value generation circuit for generating a threshold value (current threshold value) I14 is configured by T146 to T149 and the resistor R141.
The constant current I11 from the constant current source IDC 141 flows through T145 and the resistor R144, whereby the gate of T145 becomes a constant voltage. The gate voltage at T145 is used as a bias voltage. A first source follower circuit is formed by T144 and the resistor R143, and a current I12 flows through T142 and the first source follower circuit. A second source follower circuit is formed by T143 and the resistor R142, and the current I13 flows through the T141, the second source follower circuit, and the current detection resistor R131.
N-type MOSFETs having the same characteristics are used as T143, T144, and T145. Further, resistors having the same resistance value are used as the resistors R142, R143, and R144. Further, the resistance value of the resistor R142 is set to a value at which the resistance value of the current detection resistor R131 can be ignored compared to the resistance value of the resistor R142.
 駆動回路142は、P型MOSFETであるT142aとN型MOSFET142bにより構成され、出力端子がスイッチング素子T131のゲートに接続されている。
 DFF141のリセット端子Rバーには、設定周期(クロック周期)でクロック信号発生回路141からクロック信号が入力される。また、DFF141のクロック端子CLKには、T141とT143との接続点sの電圧がST141を介して入力される。
The drive circuit 142 includes a T-type MOSFET T142a and an N-type MOSFET 142b, and an output terminal is connected to the gate of the switching element T131.
A clock signal is input from the clock signal generation circuit 141 to the reset terminal R bar of the DFF 141 at a set cycle (clock cycle). The voltage at the connection point s between T141 and T143 is input to the clock terminal CLK of the DFF 141 via ST141.
 制御回路140は、設定周期(クロック周期)でスイッチング素子T131をオンする。また、スイッチング素子T131を流れる電流(本実施形態では、電流検出抵抗R131の電圧降下)が、直流電圧Vdcの大きさ(振幅)に連動する閾値より大きくなると、スイッチング素子T131をオフする。
 なお、本実施形態では、閾値発生回路から発生する閾値は、閾値補正回路150によって補正される。閾値補正回路150については、後述する。
The control circuit 140 turns on the switching element T131 at a set cycle (clock cycle). Further, when the current flowing through the switching element T131 (in this embodiment, the voltage drop of the current detection resistor R131) becomes larger than a threshold value linked to the magnitude (amplitude) of the DC voltage Vdc, the switching element T131 is turned off.
In the present embodiment, the threshold value generated from the threshold value generation circuit is corrected by the threshold value correction circuit 150. The threshold correction circuit 150 will be described later.
 次に、本実施形態100の動作を説明する。なお、電流検出抵抗R131の抵抗値をR1、抵抗R142の抵抗値をR2とする。
 最初に、基本的な動作を説明するため、閾値補正回路150を除いた回路の動作を説明する。
 先ず、スイッチSW191がオフしている場合について説明する。
 この時、全波整流回路110の正極端cと負極端d間に直流電圧Vdcが発生している。また、電源回路180は、電圧Vzdを制御回路140および駆動信号出力回路190に印加している。
 これにより、制御回路140において、電流I12、I13、IrefおよびI14が流れ、閾値(電流閾値)がセットされる。ここで、電流I14が抵抗R143に流れて[I12=I11-I14]となった場合、電流検出抵抗R131の電圧降下が「0」であるため、[I12<I11]となって、T141のドレイン電流が電流I12と等しくなる。T143のドレイン電流もT141のドレイン電流と等しくなるが、T143のドレイン電流は電流I11と同じ大きさの電流まで流し得るので、s点の電圧が引き下げられる。すなわち、s点の電圧は、Lレベルである。
 この時、スイッチSW191がオフであるため、駆動信号出力回路190からHレベルの駆動信号が出力されない。
 このため、クロック信号出力回路141から出力されるクロック信号がLレベルとなってDFF141がリセットされ、反転出力-QがHレベルとなっても、AND141の出力はHレベルとならない。したがって、スイッチング素子T131はオフ状態を維持する。
 スイッチング素子T131がオフしている時は、直流電圧Vdcにより、インダクタL132、コンデンサC132、切り替えスイッチSW131の固定接点eと常閉接点fおよび接地の経路で、コンデンサC132の充電電流I1が流れる。
Next, the operation of the present embodiment 100 will be described. The resistance value of the current detection resistor R131 is R1, and the resistance value of the resistor R142 is R2.
First, in order to explain the basic operation, the operation of the circuit excluding the threshold correction circuit 150 will be explained.
First, a case where the switch SW191 is off will be described.
At this time, a DC voltage Vdc is generated between the positive terminal c and the negative terminal d of the full-wave rectifier circuit 110. The power supply circuit 180 applies the voltage Vzd to the control circuit 140 and the drive signal output circuit 190.
Thereby, in the control circuit 140, currents I12, I13, Iref and I14 flow, and a threshold value (current threshold value) is set. Here, when the current I14 flows through the resistor R143 and becomes [I12 = I11−I14], the voltage drop of the current detection resistor R131 is “0”, so that [I12 <I11] and the drain of the T141 The current becomes equal to the current I12. Although the drain current of T143 is also equal to the drain current of T141, since the drain current of T143 can flow up to a current having the same magnitude as the current I11, the voltage at the point s is lowered. That is, the voltage at point s is L level.
At this time, since the switch SW191 is off, the drive signal output circuit 190 does not output an H level drive signal.
Therefore, even if the clock signal output from the clock signal output circuit 141 becomes L level and the DFF 141 is reset and the inverted output −Q becomes H level, the output of the AND 141 does not become H level. Therefore, the switching element T131 maintains an off state.
When the switching element T131 is off, the DC voltage Vdc causes the charging current I1 of the capacitor C132 to flow through the inductor L132, the capacitor C132, the fixed contact e of the changeover switch SW131, the normally closed contact f, and the ground path.
 スイッチSW191がオンされると、駆動信号出力回路190からHレベルの駆動信号が出力される。そして、クロック信号がLレベルとなると、DFF141がリセットされて反転出力-QがHレベルとなる。この状態で、次にクロック信号がHレベルとなると、AND141の出力がHレベルとなる。これにより、駆動回路142からスイッチング素子T131のゲートに駆動電圧が印加され、スイッチング素子T131はオンする。
 スイッチング素子T131がオンすると、コンデンサC132、インダクタL131、負荷120とコンデンサC131の並列回路、スイッチング素子T131、電流検出抵抗R131、接地および切り替えスイッチSW131の固定接点eと常閉接点fの経路で、コンデンサC132の放電電流I2が流れる。この時、インダクタL131に電磁エネルギー[L1×(I2)/2]が蓄積される。
When the switch SW191 is turned on, an H level drive signal is output from the drive signal output circuit 190. When the clock signal becomes L level, the DFF 141 is reset and the inverted output −Q becomes H level. In this state, when the clock signal becomes H level next time, the output of the AND 141 becomes H level. As a result, the drive voltage is applied from the drive circuit 142 to the gate of the switching element T131, and the switching element T131 is turned on.
When the switching element T131 is turned on, the capacitor C132, the inductor L131, the parallel circuit of the load 120 and the capacitor C131, the switching element T131, the current detection resistor R131, the ground and the path of the fixed contact e and the normally closed contact f of the changeover switch SW131, A discharge current I2 of C132 flows. At this time, electromagnetic energy [L1 × (I2) 2/ 2] is stored in the inductor L131.
 電流I2が電流検出抵抗R131(抵抗値R1)を流れると、電圧降下[R1×I2]が発生する。これにより、T143が流し得る電流値が[R1×I2/R2]だけ減少する。I2が増加して、[(R1×I2/R2)>I14]となると、T143が流し得る電流値がI12を下回り、s点の電圧が上昇してST141の出力がHレベルとなる。これにより、DFF141のクロック端子CLKにHレベルの信号が入力され、反転出力-QがLレベルとなる。したがって、スイッチング素子T131がオフする。
 電流I2が[(R2/R1)×I14]より大きくなるとスイッチング素子T131がオフされるので、[(R2/R1)×I14]が、電流I2に基づいてスイッチング素子T131を制御するときの閾値となる。
When the current I2 flows through the current detection resistor R131 (resistance value R1), a voltage drop [R1 × I2] occurs. As a result, the current value that T143 can flow is reduced by [R1 × I2 / R2]. When I2 increases and [(R1 × I2 / R2)> I14], the current value that T143 can flow is less than I12, the voltage at point s rises, and the output of ST141 becomes H level. As a result, an H level signal is input to the clock terminal CLK of the DFF 141, and the inverted output -Q becomes L level. Therefore, the switching element T131 is turned off.
When the current I2 becomes larger than [(R2 / R1) × I14], the switching element T131 is turned off. Therefore, [(R2 / R1) × I14] is a threshold value for controlling the switching element T131 based on the current I2. Become.
 電流I14は直流電圧Vdcの大きさ(振幅)に比例するので、直流電圧Vdcが変化すると閾値も変化する。直流電圧Vdcと電流I14の比例定数を変更することにより、同じ直流電圧Vdcに対する閾値を変更することができる。比例定数を変更する方法としては、抵抗R141の抵抗値を変更する方法や、T148とT149あるいはT146とT147のカレントミラー比を変更する方法を用いることができる。 Since the current I14 is proportional to the magnitude (amplitude) of the DC voltage Vdc, the threshold value changes when the DC voltage Vdc changes. The threshold for the same DC voltage Vdc can be changed by changing the proportionality constant between the DC voltage Vdc and the current I14. As a method of changing the proportionality constant, a method of changing the resistance value of the resistor R141, or a method of changing the current mirror ratio of T148 and T149 or T146 and T147 can be used.
 スイッチング素子T131がオフすると、インダクタL131に蓄積された電磁エネルギーにより、インダクタL131、負荷120とコンデンサC131の並列回路およびダイオードD131の経路で、還流電流I3が流れる。以下では、還流電流が流れるダイオードを、「還流ダイオード」という。
 同時に、全波整流回路110、インダクタL132、コンデンサC132および切り替えスイッチSW131の固定接点eと常閉接点fの経路で、コンデンサC132の充電電流I1が流れる。これにより、スイッチング素子T131がオンした時に放電したコンデンサC132の電荷が補充される。
 この時、インダクタL132のインダクタンスL2が小さいと、スイッチング素子T131のオフ期間中にコンデンサC132の充電が完了して電流I1が「0」になる。一方、インダクタL132のインダクタンスL2を大きくすると、スイッチング素子T131のオフ期間中、充電電流I1が流れ続けるようになる。
 ここで、電流I1は、交流入力電流Iacの絶対値である。したがって、スイッチング素子T131のオフ期間中も電流I1を流し続けることにより、スイッチング素子T131の1周期(オン期間+オフ期間)(「制御周期」ともいう)中、交流入力電流Iacが流れ続けることになり、高調波電流の発生が抑制される。
 これにより、図10に示されている従来の電源装置800で用いているローパスフィルタを除去することができる。あるいは、ローパスフィルタを除去することができない場合でも、ローパスフィルタを構成するインダクタのインダクタンスを低減することができる。したがって、効率を向上させることができるとともに、大幅に製品形状を小型化することができる。
When the switching element T131 is turned off, the return current I3 flows through the inductor L131, the parallel circuit of the load 120 and the capacitor C131, and the path of the diode D131 due to the electromagnetic energy accumulated in the inductor L131. Hereinafter, a diode through which a return current flows is referred to as a “return diode”.
At the same time, the charging current I1 of the capacitor C132 flows through the path of the fixed contact e and the normally closed contact f of the full-wave rectifier circuit 110, the inductor L132, the capacitor C132 and the changeover switch SW131. Thereby, the charge of the capacitor C132 discharged when the switching element T131 is turned on is supplemented.
At this time, if the inductance L2 of the inductor L132 is small, charging of the capacitor C132 is completed during the OFF period of the switching element T131, and the current I1 becomes “0”. On the other hand, when the inductance L2 of the inductor L132 is increased, the charging current I1 continues to flow during the OFF period of the switching element T131.
Here, the current I1 is an absolute value of the AC input current Iac. Therefore, by continuing the current I1 during the OFF period of the switching element T131, the AC input current Iac continues to flow during one cycle (ON period + OFF period) (also referred to as “control period”) of the switching element T131. Thus, the generation of harmonic current is suppressed.
As a result, the low-pass filter used in the conventional power supply device 800 shown in FIG. 10 can be removed. Alternatively, even when the low pass filter cannot be removed, the inductance of the inductor constituting the low pass filter can be reduced. Therefore, the efficiency can be improved and the product shape can be greatly reduced.
 コンデンサC132の充放電動作を以下に説明する。
 VdcとI14間の比例定数をKとすると、I14は、[I14=K×Vdc]と表される。
 I2を遮断する(スイッチング素子T131をオフする)閾値をIsとすると、Isは、(式1)で表される。
 Is=(R2/R1)×I14=(R2/R1)×K×Vdc (式1)
 I2が流れる経路の抵抗値は非常に小さいので、スイッチング素子T131がオンすると、I2は直線的に増大する。
The charging / discharging operation of the capacitor C132 will be described below.
When the proportionality constant between Vdc and I14 is K, I14 is expressed as [I14 = K × Vdc].
If Is is a threshold value for blocking I2 (turning off the switching element T131), Is is expressed by (Equation 1).
Is = (R2 / R1) × I14 = (R2 / R1) × K × Vdc (Formula 1)
Since the resistance value of the path through which I2 flows is very small, when switching element T131 is turned on, I2 increases linearly.
 発光ダイオードにより構成される負荷120の電流(負荷電流)が500mA程度で、かつ、クロック信号の周期(クロック周期)が20~30μs程度である場合、スイッチング素子T131のオン期間は数μsとなる。この間、コンデンサC132が放電し、コンデンサC132の正極端子の電圧VCpが低下する。VCpの低下量は、コンデンサC132の容量Cpに依存する。すなわち、容量Cpが大きくなるにつれて、VCpの低下量は少なくなる。交流電源10が、100V、60Hzである場合、Vdcのピーク値は141Vとなる。このピーク値に対して、スイッチング素子T131のオン期間において、放電による正極電圧VCpの低下量が数VとなるようにコンデンサC132の容量Cpを設定することが好ましい。コンデンサC132の容量Cpは、例えば、約0.3μfに設定される。
 一方、発光ダイオードにより構成される負荷120の電圧(負荷電圧)をVLEDとすると、スイッチング素子T131がオンした時、インダクタL131の端子間電圧VL1は、(式2)で表される。
 VL1=L1×(dI2/dt)=VCp-VLED
 (dI2/dt)=(VCp-VLED)/L1       (式2)
 すなわち、I2の増加率(増加勾配)は、(VCp-VLED)に比例し、L1に反比例する。
When the current (load current) of the load 120 constituted by the light emitting diode is about 500 mA and the period of the clock signal (clock period) is about 20 to 30 μs, the on period of the switching element T131 is several μs. During this time, the capacitor C132 is discharged, and the voltage VCp at the positive terminal of the capacitor C132 decreases. The amount of decrease in VCp depends on the capacitance Cp of the capacitor C132. That is, as the capacitance Cp increases, the amount of decrease in VCp decreases. When the AC power supply 10 is 100 V and 60 Hz, the peak value of Vdc is 141 V. With respect to this peak value, it is preferable to set the capacitance Cp of the capacitor C132 so that the decrease amount of the positive electrode voltage VCp due to the discharge is several V during the ON period of the switching element T131. The capacitance Cp of the capacitor C132 is set to about 0.3 μf, for example.
On the other hand, when the voltage (load voltage) of the load 120 constituted by a light emitting diode is VLED, when the switching element T131 is turned on, the terminal voltage VL1 of the inductor L131 is expressed by (Expression 2).
VL1 = L1 × (dI2 / dt) = VCp−VLED
(DI2 / dt) = (VCp−VLED) / L1 (Formula 2)
That is, the increase rate (increase gradient) of I2 is proportional to (VCp−VLED) and inversely proportional to L1.
 一方、スイッチング素子T131がオンしてI2が流れ始めてから遮断されるまでの時間をtsとすると、I2遮断時のIsは、(式3)で表される、
 Is=(dI2/dt)×ts=(VCp-VLED)/L1×ts
                              (式3)
 (式1)、(式3)を用いると、以下の式が成立する。
 (R2/R1)×K×Vdc=(VCp-VLED)/L1×ts
 [Vdc≒VCp]であるから、上式は(式4)のように表すことができる。
 ts=(R2/R1)×K×VCp/(VCp-VLED)×L1
                              (式4)
 ここで、tsは、[VCp≫VLED]が満足される領域では、VCpに依存しない一定値となり、(VCp-VLED)が減少するに連れてその一定値より大きくなっていく。
 スイッチング素子T131オン時のコンデンサC132の放電電荷量(以下、「Cp放電電荷量」という)は[Is×ts/2]となるので、(式5)が成立する。
 Cp放電電荷量=Is×(ts/2)
    =(L1/2)×[(R2/R1)×K]×VCp/(VCp-
VLED)                         (式5)
 VCpは、放電開始時点ではVdcより大きく、放電終了時点ではVdcより小さくなり、放電期間中の平均値はほぼVdcに等しくなる。したがって、(式4)および(式5)において、[VCp≒Vdc]とすることができる。Cp放電電荷量は、[Vdc≫VLED]となる領域ではVdcに比例し、Vdcが減少してVLEDに接近するに連れてVdc比例値より大きくなる。
On the other hand, if the time from when the switching element T131 is turned on to when I2 starts to flow and then shut off is ts, Is at the time of I2 shutoff is expressed by (Equation 3).
Is = (dI2 / dt) × ts = (VCp−VLED) / L1 × ts
(Formula 3)
When using (Expression 1) and (Expression 3), the following expression is established.
(R2 / R1) × K × Vdc = (VCp−VLED) / L1 × ts
Since [Vdc≈VCp], the above expression can be expressed as (Expression 4).
ts = (R2 / R1) × K × VCp / (VCp−VLED) × L1
(Formula 4)
Here, in a region where [VCp >> VLED] is satisfied, ts becomes a constant value independent of VCp, and becomes larger than (VCp−VLED) as the value of (VCp−VLED) decreases.
Since the discharge charge amount of the capacitor C132 when the switching element T131 is on (hereinafter referred to as “Cp discharge charge amount”) is [Is × ts / 2], (Equation 5) is satisfied.
Cp discharge charge = Is × (ts / 2)
= (L1 / 2) × [(R2 / R1) × K] 2 × VCp 2 / (VCp−
VLED) (Formula 5)
VCp is larger than Vdc at the start of discharge and smaller than Vdc at the end of discharge, and the average value during the discharge period is substantially equal to Vdc. Therefore, in (Expression 4) and (Expression 5), [VCp≈Vdc] can be obtained. The amount of Cp discharge charge is proportional to Vdc in a region where [Vdc >> VLED], and becomes larger than the Vdc proportional value as Vdc decreases and approaches VLED.
 スイッチング素子T131の1周期(オン期間+オフ期間)におけるVdcの変化量を△Vdcとすると、Vdcの増加過程では[△Vdc>0]となり、Vdcピーク時には[△Vdc=0]となり、Vdcの減少過程では[△Vdc<0]となる。コンデンサC132は、AC入力電流により、Vdcの増加過程では、Cp放電電荷量より[△Vdc×Cp]だけ多い電荷が充電され、Vdcの減少過程では、Cp放電電荷量より[△Vdc×Cp]だけ少ない電荷が充電される。
 従って、スイッチング素子T131の1周期において、(式6)が成立する。なお、スイッチング素子T131の1周期は、クロック信号出力回路141から出力されるクロック信号の周期(クロック周期)と一致する。
 Cp放電電荷量=Cp充電電流積分値-△Vdc×Cp    (式6)
 電荷量[△Vdc×Cp]は、交流電圧Vacに対して交流入力電流Iacの位相を進めるように作用し、基本周波数に近接した高調波電流を発生させる。
 ここで、[Cp充電電流積分値≫(△Vdc×Cp)]となるようにコンデンサC132の容量Cpの値を選定すれば、Cp放電電荷量は、スイッチング素子T131の1周期のCp充電電流積分値にほぼ等しくなる。
When the amount of change in Vdc in one cycle (on period + off period) of the switching element T131 is ΔVdc, [ΔVdc> 0] is obtained in the process of increasing Vdc, and [ΔVdc = 0] at the time of Vdc peak. In the decreasing process, [ΔVdc <0]. The capacitor C132 is charged with [ΔVdc × Cp] more charge than the Cp discharge charge amount in the process of increasing Vdc due to the AC input current, and [ΔVdc × Cp] than the Cp discharge charge amount in the process of decreasing Vdc. Only a small amount of charge is charged.
Therefore, (Equation 6) is established in one cycle of the switching element T131. Note that one cycle of the switching element T131 matches the cycle of the clock signal output from the clock signal output circuit 141 (clock cycle).
Cp discharge charge = Cp charge current integrated value−ΔVdc × Cp (Formula 6)
The charge amount [ΔVdc × Cp] acts to advance the phase of the AC input current Iac with respect to the AC voltage Vac, and generates a harmonic current close to the fundamental frequency.
Here, if the value of the capacitance Cp of the capacitor C132 is selected so that [Cp charge current integral value >> (ΔVdc × Cp)], the Cp discharge charge amount is the Cp charge current integral of one cycle of the switching element T131. Almost equal to the value.
 図1から理解されるように、交流入力電流Iacは、コンデンサC132の充電電流、抵抗R181を流れる電流および抵抗R141を流れる電流Irefの和である。抵抗R181およびR141を流れる電流はほぼVdcに比例するから、交流入力電流Iacは、Vdcに比例した大きさとなる。従って、交流入力電流Iacは、交流電圧Vacとほぼ同相となり、力率が「1」に近づくことになる。 As can be understood from FIG. 1, the AC input current Iac is the sum of the charging current of the capacitor C132, the current flowing through the resistor R181, and the current Iref flowing through the resistor R141. Since the current flowing through the resistors R181 and R141 is substantially proportional to Vdc, the AC input current Iac has a magnitude proportional to Vdc. Therefore, the AC input current Iac is substantially in phase with the AC voltage Vac, and the power factor approaches “1”.
 次に、還流電流I3について説明する。
 スイッチング素子T131がオフすると、インダクタL131に、スイッチング素子T131がオンの時にインダクタL131に流れていた電流I2を流し続ける方向に逆起電力が発生するため、コンデンサC131の正極端子電圧が上昇する。これにより、コンデンサC131の負極端子電圧が持ち上げられる。コンデンサC131の負極端子電圧が、コンデンサC132の正極端子電圧VCpより、還流ダイオードD131の順方向電圧だけ高い電圧に達すると、インダクタL131、負荷120とコンデンサC131の並列回路および還流ダイオードD131の経路で、還流電流I3が流れる。このとき、インダクタL131に発生する逆起電力は、コンデンサC131の端子間電圧(負荷電圧)VLEDと還流ダイオードD131の順方向電圧VD1を加算したものになる。
 -L1×(dI3/dt)=VLED+VD1
 -(dI3/dt)=(VLED+VD1)/L1
 還流電流I3は、(VLED+VD1)に比例し、L1に反比例する大きさの勾配で直線的に減少する。
Next, the reflux current I3 will be described.
When the switching element T131 is turned off, a counter electromotive force is generated in the inductor L131 in a direction in which the current I2 that was flowing through the inductor L131 when the switching element T131 is turned on is generated, so that the positive terminal voltage of the capacitor C131 increases. Thereby, the negative terminal voltage of the capacitor C131 is raised. When the negative terminal voltage of the capacitor C131 reaches a voltage higher than the positive terminal voltage VCp of the capacitor C132 by the forward voltage of the freewheeling diode D131, the inductor L131, the parallel circuit of the load 120 and the capacitor C131, and the path of the freewheeling diode D131, A reflux current I3 flows. At this time, the back electromotive force generated in the inductor L131 is the sum of the inter-terminal voltage (load voltage) VLED of the capacitor C131 and the forward voltage VD1 of the freewheeling diode D131.
−L1 × (dI3 / dt) = VLED + VD1
− (DI3 / dt) = (VLED + VD1) / L1
The reflux current I3 is proportional to (VLED + VD1) and linearly decreases with a gradient having a magnitude inversely proportional to L1.
 スイッチング素子T131がオンからオフに移行した時点では、[I3=I2=Is]が成立する。L1が大きくなるにつれて、還流電流I3が消滅するまでの時間が長くなる。還流電流I3が消滅するまでの時間がスイッチング素子T131のオフ期間を超えると、還流電流I3が流れている状態で、スイッチング素子T131がオンになる。
 スイッチング素子T131オン時の還流電流I3の値をI3remとすると、次回のスイッチング素子T131オフ時に、インダクタL131に新たに蓄積される電磁エネルギーは、[L1×(Is-I3rem)/2]となる。インダクタL131に蓄積される全電磁エネルギーが[L1×(Is)/2]であっても、電磁エネルギー[L1×(I3rem)/2]は、常時インダクタL131に蓄積され、出力されない。すなわち、還流回路にI3remが流れても、電磁エネルギー[L1×(I3rem)/2]は、出力側に伝達されない。還流回路には、配線抵抗と還流ダイオードD131の順方向電圧降下による電力損失が発生するので、出力されないI3remが流れることによって効率が低下する。
 一方、L1が大きい程、I2からI3に変化するときの電流勾配変化が小さくなるので、スイッチング素子T131の損失が小さくなる。従って、インダクタンスL1は、還流電流I3がスイッチング素子T131のオフ期間中に消滅する範囲内で、極力大きな値に設定することが望ましい。
[I3 = I2 = Is] is established when the switching element T131 shifts from on to off. As L1 increases, the time until the return current I3 disappears becomes longer. When the time until the return current I3 disappears exceeds the OFF period of the switching element T131, the switching element T131 is turned on while the return current I3 is flowing.
When the value of the return current I3 when the switching element T131 is on is I3rem, the electromagnetic energy newly accumulated in the inductor L131 when the switching element T131 is next off is [L1 × (Is 2 −I3rem 2 ) / 2]. Become. Also all the electromagnetic energy accumulated in inductor L131 is a [L1 × (Is) 2/ 2], the electromagnetic energy [L1 × (I3rem) 2/ 2] is accumulated constantly inductor L131, is not output. That is, even I3rem flows back circuit, electromagnetic energy [L1 × (I3rem) 2/ 2] is not transmitted to the output side. In the return circuit, power loss occurs due to a drop in the forward voltage of the wiring resistance and the return diode D131. Therefore, the efficiency is lowered due to the non-output I3rem flowing.
On the other hand, the larger the L1, the smaller the current gradient change when changing from I2 to I3, so the loss of the switching element T131 becomes smaller. Therefore, it is desirable to set the inductance L1 as large as possible within a range in which the return current I3 disappears during the OFF period of the switching element T131.
 負荷120に供給する直流電力の大きさを変更する方法としては、既に述べたように、抵抗R141の抵抗値を変更する方法や、T148とT149またはT146とT147のカレントミラー比を変更する方法を用いることができる。
 コンデンサC132の容量Cpを、例えば0.3μFに固定すると、直流電力が大きいときは力率を所定範囲に設定することができる(PFC規格を満たすことができる)が、直流電力を小さくすると、力率を所定範囲に設定することができなくなる(PFC規格を満たすことができなくなる)場合がある。例えば、Cp放電電荷量が減少してCp充電電流積分値が小さくなり、前述した(式6)において、[Cp充電電流積分値≫△Vdc×Cp]の条件を満足できなくなる。
 このような場合には、図1に示されている切り替えスイッチSW131を切り替えて、固定接点eと常開接点gを接続する。これにより、容量Cp1を有するコンデンサC133がコンデンサC132に直列に接続されて合成容量(Cpの等価容量)が減少し、[Cp充電電流積分値≫△Vdc×Cp]の条件を満足させることができる。例えば、コンデンサC133の容量Cp1を0.1μFとしておけば、[Cpの等価容量=0.075μF]となる。このようなコンデンサC133を用いると、抵抗R141の抵抗値を大きくした場合でも力率を所定範囲に設定することができる。
As described above, as a method of changing the magnitude of the DC power supplied to the load 120, a method of changing the resistance value of the resistor R141 or a method of changing the current mirror ratio of T148 and T149 or T146 and T147. Can be used.
If the capacitance Cp of the capacitor C132 is fixed at, for example, 0.3 μF, the power factor can be set within a predetermined range when the DC power is large (can satisfy the PFC standard), but if the DC power is reduced, the power In some cases, the rate cannot be set within a predetermined range (the PFC standard cannot be satisfied). For example, the Cp discharge charge amount decreases and the Cp charge current integral value decreases, and in the above-described (Equation 6), the condition of [Cp charge current integral value >> ΔVdc × Cp] cannot be satisfied.
In such a case, the changeover switch SW131 shown in FIG. 1 is switched to connect the fixed contact e and the normally open contact g. As a result, the capacitor C133 having the capacitance Cp1 is connected in series to the capacitor C132, the combined capacitance (equivalent capacitance of Cp) is reduced, and the condition [Cp charging current integral value >> ΔVdc × Cp] can be satisfied. . For example, if the capacitance Cp1 of the capacitor C133 is set to 0.1 μF, the equivalent capacitance of Cp = 0.075 μF is obtained. When such a capacitor C133 is used, the power factor can be set within a predetermined range even when the resistance value of the resistor R141 is increased.
 なお、図1に示す第1の実施形態100では、インダクタL131と、負荷120とコンデンサC131の並列回路は、直列に接続されている。このため、インダクタL131と、負荷120とコンデンサC131の並列回路の位置を入れ替えても、得られる機能は変わらない。 In addition, in 1st Embodiment 100 shown in FIG. 1, the parallel circuit of the inductor L131, the load 120, and the capacitor | condenser C131 is connected in series. For this reason, even if the position of the parallel circuit of the inductor L131, the load 120, and the capacitor C131 is switched, the obtained function does not change.
 次に、閾値補正回路150について説明する。
 最初に、電流I1を求める。
 AC入力電流Iacの絶対値は、インダクタL132に流れる電流I1にほぼ等しい。コンデンサC132の正極端子の電圧をVCpとし、[t=0]の時点でスイッチング素子T131がオンからオフに移行したものとし、その時のI1およびVCpの値(初期値)をそれぞれI1(0)およびVCp(0)とすると、I1は(式7)で表される。
Figure JPOXMLDOC01-appb-M000001
 Vdc一定として(式7)を解くと、I1は、(式8)で表される。
Figure JPOXMLDOC01-appb-M000002
但し
Figure JPOXMLDOC01-appb-M000003
Next, the threshold correction circuit 150 will be described.
First, the current I1 is obtained.
The absolute value of AC input current Iac is substantially equal to current I1 flowing through inductor L132. Assume that the voltage at the positive terminal of the capacitor C132 is VCp, and the switching element T131 has shifted from on to off at the time of [t = 0], and the values (initial values) of I1 and VCp at that time are I1 (0) and If VCp (0), I1 is expressed by (Equation 7).
Figure JPOXMLDOC01-appb-M000001
Solving (Equation 7) with Vdc constant, I1 is expressed by (Equation 8).
Figure JPOXMLDOC01-appb-M000002
However,
Figure JPOXMLDOC01-appb-M000003
 時点[t=0]で、[Vdc-VCp(0)>0]となって電流I1が増加し始めると、コンデンサC132がI1により充電され、VCpが上昇する。
 I1は、(式8)で表されるように、正弦波の一部を切り取った波形となる。I1は、
Figure JPOXMLDOC01-appb-M000004
でピーク値となる。この時、[Vdc-VCp=0]となる。
 その後、VCpは上昇するが、I1が減少する。そして、次のスイッチング素子T131のオン期間中に減少から増加に反転する。そして、次のスイッチング素子T131のオフ期間が始まり、I1が増加し始める時点で一周期が終了する。
 すなわち、クロック周期に対応して、[t=0]から始まるI1波形の一周期は、正弦波の一部からなる、上に凸の波形となり、I1は、クロック周期に対応した凸状波形が連なる波形になる。凸状波形のピーク値(極大値)は、[Vdc≫VLED]の領域ではVdcに比例した大きさとなり、(Vdc-VLED)が小さくなるに連れてVdc比例値より大きな値になる。
 凸状波形の変動幅(最小値とピーク値の差)は、クロック周期と正弦波の周期の比に依存する。すなわち、クロック周期に対して正弦波の周期が相対的に大きくなると、凸状波形の変動幅が小さくなる。
At time [t = 0], when [Vdc−VCp (0)> 0] and the current I1 starts to increase, the capacitor C132 is charged by I1, and VCp increases.
I1 is a waveform obtained by cutting off a part of a sine wave as represented by (Equation 8). I1 is
Figure JPOXMLDOC01-appb-M000004
At the peak value. At this time, [Vdc−VCp = 0].
Thereafter, VCp increases, but I1 decreases. Then, during the ON period of the next switching element T131, it is inverted from decrease to increase. Then, when the next off period of the switching element T131 starts and I1 starts to increase, one cycle ends.
That is, corresponding to the clock period, one period of the I1 waveform starting from [t = 0] is an upwardly convex waveform composed of a part of a sine wave, and I1 is a convex waveform corresponding to the clock period. It becomes a continuous waveform. The peak value (local maximum value) of the convex waveform has a magnitude proportional to Vdc in the region of [Vdc >> VLED], and becomes a value larger than the Vdc proportional value as (Vdc−VLED) decreases.
The fluctuation range of the convex waveform (difference between the minimum value and the peak value) depends on the ratio of the clock period to the sine wave period. That is, when the period of the sine wave becomes relatively large with respect to the clock period, the fluctuation width of the convex waveform becomes small.
 力率が「1」より低下し、かつ、高調波電流が発生する原因としては、以下の点が考えられる。
(原因1):(式6)に含まれている[△Vdc×Cp]によりI1の位相が進む。
(原因2):I1がクロック周期に同期した凸状波形を連ねた波形となるため、クロック周波数の高調波電流が発生する。凸状波形の変動幅が大きいほど、高調波電流の振幅が大きくなる。
(原因3):(式8)に含まれている初期値(Vdc-VCp(0))およびI1(0)のばらつきにより、I1のピーク値および変動幅がクロック周期の数倍の周期で不規則に変動し、クロック周波数より低い周波数の高調波電流が発生する。
(原因4):(Vdc-VLED)が小さい領域では、I1の増加勾配(増加率)が緩やかになり、スイッチング素子のオン期間が長くなる。このため、スイッチング素子遮断時のI1はVdcに比例しても、スイッチング素子のオン期間におけるCp放電電荷量がVdc比例値より相対的に大きくなる。したがって、Vdcが最小値から増加し、スイッチング素子がオン、オフを開始する際に、I1がステップ状に増加する。そして、これがきっかけとなって、(原因3)により、大きな振幅から始まる、クロック周期の数倍の周期を有する減衰振動が発生する。
The following points can be considered as the causes of the power factor lowering than “1” and the generation of harmonic current.
(Cause 1): The phase of I1 advances by [ΔVdc × Cp] included in (Expression 6).
(Cause 2): Since I1 is a waveform in which convex waveforms synchronized with the clock cycle are connected, a harmonic current having a clock frequency is generated. The larger the fluctuation range of the convex waveform, the higher the amplitude of the harmonic current.
(Cause 3): Due to variations in the initial values (Vdc−VCp (0)) and I1 (0) included in (Equation 8), the peak value and fluctuation range of I1 are not consistent with a period several times the clock period. It fluctuates regularly and generates a harmonic current with a frequency lower than the clock frequency.
(Cause 4): In the region where (Vdc−VLED) is small, the increasing gradient (increase rate) of I1 becomes gradual, and the ON period of the switching element becomes long. For this reason, even if I1 when the switching element is cut off is proportional to Vdc, the Cp discharge charge amount during the ON period of the switching element is relatively larger than the Vdc proportional value. Therefore, when Vdc increases from the minimum value and the switching element starts to turn on and off, I1 increases stepwise. This triggers a damped oscillation having a period several times the clock period starting from a large amplitude due to (Cause 3).
 (原因2)の対策としては、クロック周期を小さくし、正弦波周期を相対的に大きくする方法が効果的である。
 (式8)から、正弦波周期は、[2π×(L2×Cp)1/2]である。したがって、正弦波周期を大きくするには、L2またはCpを大きくすればよい。
 L2を大きくすると、内部抵抗による電力損失、製品形状やコストが増大する。このため、L2を大きくする方法は、好ましくない。
 一方、Cpを大きくすると、(式6)に含まれている[△Vdc×Cp]によるI1の位相進みが増大する。I1の位相進みが増大すると、力率が悪化する。
 Cpの増大によるI1の位相進みの増大を防止するためには、Vdc増加時は、Cp放電電荷量を[△Vdc×Cp]だけ減少させ、Vdc減少時は、Cp放電電荷量を[△Vdc×Cp]だけ増加させればよい。
 Cp放電電荷量は、I14に比例する。したがって、Cpの増大によるI1の位相進みの増大を防止するためには、Vdc増加時は、I14を[△Vdc×Cp]相当分だけ減少させ、Vdc減少時は、I14を[△Vdc×Cp]相当分だけ増加させればよい。
 本実施形態では、I14を増減させる(補正する)閾値補正回路150を設けることにより、I1の位相進みの増大(力率の悪化)を防止しながら、Cpを大きくしてクロック周波数の高調波電流の振幅を低減している。
As a countermeasure for (Cause 2), a method of reducing the clock cycle and relatively increasing the sine wave cycle is effective.
From (Equation 8), the sine wave cycle is [2π × (L2 × Cp) 1/2 ]. Therefore, in order to increase the sine wave period, L2 or Cp may be increased.
Increasing L2 increases power loss due to internal resistance, product shape and cost. For this reason, the method of increasing L2 is not preferable.
On the other hand, when Cp is increased, the phase advance of I1 due to [ΔVdc × Cp] included in (Expression 6) increases. As the phase advance of I1 increases, the power factor deteriorates.
In order to prevent an increase in the phase advance of I1 due to an increase in Cp, the amount of Cp discharge charge is decreased by [ΔVdc × Cp] when Vdc increases, and the amount of Cp discharge charge is decreased by [ΔVdc when Vdc decreases. XCp] should be increased.
The Cp discharge charge amount is proportional to I14. Therefore, in order to prevent an increase in the phase advance of I1 due to an increase in Cp, when Vdc is increased, I14 is decreased by an amount corresponding to [ΔVdc × Cp], and when Vdc is decreased, I14 is decreased by [ΔVdc × Cp. ] Just increase by a considerable amount.
In this embodiment, by providing a threshold correction circuit 150 that increases or decreases (corrects) I14, while preventing an increase in the phase advance of I1 (deterioration of the power factor), Cp is increased to increase the harmonic current of the clock frequency. The amplitude is reduced.
 閾値補正回路150は、P型MOSFETであるT153、T154、N型MOSFETであるT151、T152、T155、コンデンサC151、ダイオードD151、D152により構成されている。
 T151とT152およびT153とT154は、カレントミラー回路を構成するように配置されている。
The threshold correction circuit 150 includes P-type MOSFETs T153 and T154, N-type MOSFETs T151, T152, and T155, a capacitor C151, and diodes D151 and D152.
T151 and T152 and T153 and T154 are arranged to form a current mirror circuit.
 閾値補正回路150は、以下のように動作する。
 Vdcが増加する時には、Vdc、コンデンサC151、ダイオードD151およびT151の経路でコンデンサC151に充電電流が流れる。この時、ダイオードD151のアノードの電位が接地レベルより高くなるので、T155はオフしている。
 コンデンサC151を流れる電流は、Vdcに対して90度位相が進み、その大きさはVdcの微分値に比例するので、[△Vdc×Cp]に比例する。T151とT152によりカレントミラー回路が構成されているため、T152のドレイン電流I15は、コンデンサC151の充電電流に比例し、その大きさはT151とT152のカレントミラー比で調整することができる。
 すなわち、Vdcの増加過程では、Vdcに比例する電流I14から、[△Vdc×Cp]に比例する電流I15が減算される。
 一方、Vdcが減少する時には、コンデンサC151により、ダイオードD151のアノードの電位が接地レベル以下に押し下げられので、T155がオンする。T155がオンすると、コンデンサC151、T153、T155、ダイオードD152の経路でコンデンサC151の放電電流が流れる。コンデンサC151の放電電流は、[△Vdc×Cp]に比例する。T153とT154によりカレントミラー回路が構成されているため、T154のドレイン電流I16は、コンデンサC151の放電電流に比例し、その大きさはT153とT154のカレントミラー比で調整することができる。
 すなわち、Vdcの減少過程では、Vdcに比例する電流I14に、[△Vdc×Cp]に比例する電流I16が加算される。
 これにより、各クロック周期における[Cp放電電荷量-△Vdc×Cp]、すなわちCp充電電荷量がVdcに比例するようになり、Cpの増大による位相進みの増大を防止することができる。
The threshold correction circuit 150 operates as follows.
When Vdc increases, a charging current flows through the capacitor C151 through the path of Vdc, capacitor C151, diode D151 and T151. At this time, since the potential of the anode of the diode D151 becomes higher than the ground level, T155 is off.
The current flowing through the capacitor C151 is 90 degrees out of phase with respect to Vdc, and its magnitude is proportional to the differential value of Vdc, and is therefore proportional to [ΔVdc × Cp]. Since the current mirror circuit is constituted by T151 and T152, the drain current I15 of T152 is proportional to the charging current of the capacitor C151, and the magnitude thereof can be adjusted by the current mirror ratio of T151 and T152.
That is, in the increasing process of Vdc, the current I15 proportional to [ΔVdc × Cp] is subtracted from the current I14 proportional to Vdc.
On the other hand, when Vdc decreases, the capacitor C151 pushes down the anode potential of the diode D151 below the ground level, so that T155 is turned on. When T155 is turned on, the discharge current of the capacitor C151 flows through the paths of the capacitors C151, T153, T155, and the diode D152. The discharge current of the capacitor C151 is proportional to [ΔVdc × Cp]. Since the current mirror circuit is configured by T153 and T154, the drain current I16 of T154 is proportional to the discharge current of the capacitor C151, and the magnitude thereof can be adjusted by the current mirror ratio of T153 and T154.
That is, in the process of decreasing Vdc, the current I16 proportional to [ΔVdc × Cp] is added to the current I14 proportional to Vdc.
Accordingly, [Cp discharge charge amount−ΔVdc × Cp] in each clock cycle, that is, the Cp charge amount is proportional to Vdc, and an increase in phase advance due to an increase in Cp can be prevented.
 (原因3)および(原因4)の対策方法としては、Vdc立ち上がり後の(Vdc-VLED)が小さいときはスイッチング素子を動作させない方法が有効である。この方法については、後述する第2の実施形態(図3)で説明する。 As a countermeasure method for (Cause 3) and (Cause 4), a method in which the switching element is not operated when (Vdc−VLED) after the rise of Vdc is small is effective. This method will be described in a second embodiment (FIG. 3) described later.
 閾値補正回路150を設けた場合のシミュレーション結果が、図2に示されている。図2に示されているシミュレーション結果は、各回路要素の値を以下のように設定した場合のものである。Vac:AC100V,60Hz、L1:50μH、L2:600μH、Cp:0.6μF、C1:500μF、C151:1nF、クロック周期:20μs(Hレベル期間:1.6μs(Vdc増加時)、1.8μs(Vdc減少時))、VLED平均値:15V、LED負荷電流平均値:644mA。
 図2において、横軸は経過時間t(ms)を表し、縦軸の第1軸はグラフ(1)の電圧(V)を表し、縦軸の第2軸はグラフ(2)、(3)の電流(mA)を表し、縦軸の第3軸はグラフ(4)~(7)の電流(μA)を表している。
 また、グラフ(1)(白四角が付された実線)は、Vdc(V)を表している。グラフ(2)(白三角が付された実線)は、閾値補正回路150が設けられてない場合のI1(mA)を表している。グラフ(3)(黒三角が付された破線)は、閾値補正回路150が設けられている場合のI1(mA)を表している。グラフ(4)(黒丸が付された破線)は、補正前の閾値(電流閾値)I14(μA)を表している。グラフ(5)(白四角が付された一点鎖線)は、補正値I15(μA)を表している。グラフ(6)(黒四角が付された二点鎖線)は、補正値I16(μA)を表している。グラフ(7)(白丸が付された実線)は、補正後の閾値(電流閾値)[I14-I15+I16](μA)を表している。
 なお、図2には図示していないが、グラフ(2)~(7)で示されている電流波形は、高調波電流成分を含んでいる。
The simulation result when the threshold value correction circuit 150 is provided is shown in FIG. The simulation results shown in FIG. 2 are obtained when the values of the circuit elements are set as follows. Vac: AC 100 V, 60 Hz, L1: 50 μH, L2: 600 μH, Cp: 0.6 μF, C1: 500 μF, C151: 1 nF, clock cycle: 20 μs (H level period: 1.6 μs (when Vdc increases), 1.8 μs ( Vdc decrease)), VLED average value: 15 V, LED load current average value: 644 mA.
In FIG. 2, the horizontal axis represents elapsed time t (ms), the first vertical axis represents the voltage (V) of the graph (1), and the second vertical axis represents the graphs (2) and (3). The third axis of the vertical axis represents the current (μA) of graphs (4) to (7).
Graph (1) (solid line with white squares) represents Vdc (V). Graph (2) (solid line with white triangles) represents I1 (mA) when the threshold correction circuit 150 is not provided. Graph (3) (broken line with a black triangle) represents I1 (mA) in the case where the threshold correction circuit 150 is provided. Graph (4) (broken line with a black circle) represents a threshold value (current threshold value) I14 (μA) before correction. A graph (5) (a one-dot chain line with a white square) represents the correction value I15 (μA). Graph (6) (two-dot chain line with a black square) represents the correction value I16 (μA). Graph (7) (solid line with white circles) represents a corrected threshold value (current threshold value) [I14−I15 + I16] (μA).
Although not shown in FIG. 2, the current waveforms shown in graphs (2) to (7) include harmonic current components.
 図2から、以下のことが理解できる。
 閾値補正回路150が設けられていない場合の閾値は、グラフ(4)で示されているI14によって設定される。この時、グラフ(2)で示されているI1(補正前のI1)は、グラフ(1)で示されているVdcに対して位相が進んでおり、また、第11高調波電流の振幅が、基本波電流の振幅の3.32%である。この場合、PFC規格を満たすことができないため、高調波電流を抑制するためのローパスフィルタが必要となる。
 一方、閾値補正回路150が設けられている場合の閾値は、グラフ(4)で示されているI14をグラフ(5)で示されている補正値I15およびグラフ(6)で示されている補正値I16により補正した値[I14-I15+I16]のグラフ(7)となる。この時、グラフ(3)で示されているI1(補正後のI1)は、Vdcに対する位相進みが抑制され、第11高調波以上の高調波電流の振幅は、クロック周波数が50kHz(クロック周期:20μs)の場合に2.6%となったが、その他の周波数ではこれ以下になった。この場合、PFC規格を満たしているため、高調波電流を抑制するためのローパスフィルタを設ける必要がない。すなわち、ローパスフィルタを設けることなく、高調波電流を十分に抑制することができる。
The following can be understood from FIG.
The threshold when the threshold correction circuit 150 is not provided is set by I14 shown in the graph (4). At this time, the phase of I1 (I1 before correction) shown in the graph (2) is advanced with respect to Vdc shown in the graph (1), and the amplitude of the eleventh harmonic current is , Which is 3.32% of the amplitude of the fundamental current. In this case, since the PFC standard cannot be satisfied, a low-pass filter for suppressing harmonic current is required.
On the other hand, when the threshold value correction circuit 150 is provided, the threshold value is the correction value I15 indicated by the graph (5) and the correction value indicated by the graph (6), which is indicated by the graph (4). A graph (7) of a value [I14−I15 + I16] corrected by the value I16 is obtained. At this time, I1 (I1 after correction) shown in the graph (3) suppresses the phase advance with respect to Vdc, and the amplitude of the harmonic current higher than the eleventh harmonic is 50 kHz (clock period: In the case of 20 μs), it was 2.6%, but it was less than this at other frequencies. In this case, since the PFC standard is satisfied, it is not necessary to provide a low-pass filter for suppressing the harmonic current. That is, the harmonic current can be sufficiently suppressed without providing a low-pass filter.
[第2の実施形態]
 第1の実施形態では、閾値I14を補正値I15およびI16により補正した値を閾値として用いることにより、I1の波形を修正して力率を「1」に近づける(高調波電流を抑制する)方法を用いた。I1の波形を修正して力率を「1」に近付ける方法としては他の方法を用いることもできる。
 図3に、本発明の電源装置の第2の実施形態200の回路図が示されている。第2の実施形態200では、閾値I14を変更する方法を用いている。
 第2の実施形態200は、制御回路240に第1の実施形態100の閾値補正回路150が設けられていない点と、制御回路240にツェナーダイオードZD241が追加されている点を除いて、第1の実施形態100と同様の構成である。すなわち、制御回路240の閾値発生回路の構成が、制御回路140の閾値発生回路の構成と相違している。なお、図3において、図1に示されている記号と、百番台の数字以外が一致する記号が付されている構成要素は、図1に示されている第1の実施形態100の構成要素と同じものである。
[Second Embodiment]
In the first embodiment, by using the value obtained by correcting the threshold value I14 with the correction values I15 and I16 as the threshold value, the waveform of I1 is modified to bring the power factor closer to “1” (suppress harmonic current). Was used. Other methods can be used as a method of correcting the waveform of I1 to bring the power factor closer to “1”.
FIG. 3 shows a circuit diagram of a second embodiment 200 of the power supply device of the present invention. In the second embodiment 200, a method of changing the threshold value I14 is used.
The second embodiment 200 is different from the first embodiment except that the threshold correction circuit 150 of the first embodiment 100 is not provided in the control circuit 240 and a Zener diode ZD241 is added to the control circuit 240. The configuration is the same as that of the embodiment 100. That is, the configuration of the threshold generation circuit of the control circuit 240 is different from the configuration of the threshold generation circuit of the control circuit 140. In FIG. 3, the components to which the symbols shown in FIG. 1 and symbols other than the numbers in the hundreds are attached are the components of the first embodiment 100 shown in FIG. 1. Is the same.
 以下では、第1の実施形態100と異なっている構成(閾値発生回路の構成)についてのみ説明する。
 本実施形態200の閾値発生回路は、T246~T249、抵抗R241およびツェナーダイオードZD241により構成されている。
 抵抗R241の抵抗値をR241a、ツェナーダイオードZD241のツェナー電圧をVZD241とすると、Irefは以下の式で表される。
 Iref=(Vdc-VZD241)/R241a
 なお、I14はIrefに比例する。
 [Vdc<VZD241]の場合には、Irefが流れないので、I14がゼロになる。この時スイッチング素子T231がオフとなるように構成されていると、I1が流れないため、コンデンサ232の正極端子電圧VCpおよびVdcは、VZD241より低下しない。
 一方、[Vdc>VZD241]の場合には、Irefが流れる。この時、Irefは、(Vdc-VZD241)に比例する。
Only the configuration (configuration of the threshold generation circuit) that is different from the first embodiment 100 will be described below.
The threshold value generation circuit of the present embodiment 200 includes T246 to T249, a resistor R241, and a Zener diode ZD241.
If the resistance value of the resistor R241 is R241a and the Zener voltage of the Zener diode ZD241 is VZD241, Iref is expressed by the following equation.
Iref = (Vdc−VZD241) / R241a
Note that I14 is proportional to Iref.
In the case of [Vdc <VZD241], since Iref does not flow, I14 becomes zero. At this time, if the switching element T231 is configured to be turned off, I1 does not flow, so that the positive terminal voltages VCp and Vdc of the capacitor 232 do not decrease below the VZD241.
On the other hand, when [Vdc> VZD241], Iref flows. At this time, Iref is proportional to (Vdc−VZD241).
 いま、交流電圧Vacの振幅を141Vに設定し、VZD241を47V(=141V/3)に設定した場合について説明する。
 この場合、交流電圧Vacの半周期におけるVCpの変化範囲は47V~141Vとなり、[△Vdc×Cp]の絶対値の総和は[(141V-47V)×Cp×2]となる。一方、ツェナーダイオードZD241が設けられてない場合には、[△Vdc×Cp]の絶対値の総和は[141V×Cp×2]である。
 すなわち、ツェナーダイオードZD241が設けられている場合には、Vdcの変化に起因するCpの充放電電荷量は、ツェナーダイオードZD241が設けられていない場合に較べて2/3となり、Cpによる位相進みが2/3に減少する。
 したがって、ツェナーダイオードZD241が設けられ(第2の実施形態)、Cpが0.6μfに設定されている場合の位相進みは、ツェナーダイオードZD241が設けられてなく、Cpが0.4μfに設定されている場合の位相進みと同じになる。言い換えれば、本実施形態では、Cpの増大による位相進みの増大を抑制しながら、Cpを増大させることができる。
Now, a case where the amplitude of the AC voltage Vac is set to 141 V and the VZD 241 is set to 47 V (= 141 V / 3) will be described.
In this case, the change range of VCp in a half cycle of the AC voltage Vac is 47 V to 141 V, and the sum of absolute values of [ΔVdc × Cp] is [(141 V−47 V) × Cp × 2]. On the other hand, when the Zener diode ZD241 is not provided, the sum of absolute values of [ΔVdc × Cp] is [141V × Cp × 2].
That is, in the case where the Zener diode ZD241 is provided, the charge / discharge charge amount of Cp due to the change in Vdc is 2/3 compared to the case where the Zener diode ZD241 is not provided, and the phase advance due to Cp is increased. Decrease to 2/3.
Therefore, the phase advance in the case where the Zener diode ZD241 is provided (second embodiment) and Cp is set to 0.6 μf, the Zener diode ZD241 is not provided and Cp is set to 0.4 μf. It is the same as the phase lead when In other words, in this embodiment, Cp can be increased while suppressing an increase in phase advance due to an increase in Cp.
 ツェナーダイオードZD241が設けられてない場合には、Irefの、Vdcの半周期の積分値は、Vdcの半周期の面積に比例する。
 一方、ツェナーダイオードZD241が設けられている場合には、[Vdc>VZD241]の領域で流れるIrefの、Vdcの半周期の積分値は、Vdcの半周期の面積から、VdcがVZD241以下となる部分の面積を差し引いた(減算した)面積に比例する。VZD241を47Vに設定した場合についてこの面積を計算すると、Vdcの半周期の面積の53.25%となる。このため、抵抗R241の抵抗値が、ツェナーダイオードZD241が設けられてない場合と同じ(例えば、第1の実施形態100の抵抗R141の抵抗値と同じ)場合には、IrefのVdc半周期の積分値が、ツェナーダイオードZD241が設けられてない場合より減少する。
 IrefのVdc半周期の積分値を、ツェナーダイオードZD241が設けられていない場合と等しくするためには、抵抗値R241aを小さくすればよい。例えば、第1の実施形態100の抵抗R141の抵抗値をR141aとした場合、抵抗値R241aを、[R241a=R141a×0.5325]とすればよい。
 抵抗値R241aを変更(減少)しても、I1の位相進みは、減少することはあっても増加することはない。
 なお、抵抗値R241aをさらに小さくすると、I1が増大して、基本波電流の振幅が大きくなる。この場合、基本波電流の振幅に対する高調波電流の振幅比が小さくなる。
 また、Irefと(Vdc-VZD241)の相関関係を、比例とは異なる相関関係に設定することもできる。例えば、抵抗R241に並列に、抵抗とツェナーダイオードを直列に接続した回路を接続する。
In the case where the Zener diode ZD241 is not provided, the integral value of Iref and the half cycle of Vdc is proportional to the area of the half cycle of Vdc.
On the other hand, in the case where the Zener diode ZD241 is provided, the integral value of the half cycle of Vdc of Iref flowing in the region of [Vdc> VZD241] is a portion where Vdc is VZD241 or less from the area of the half cycle of Vdc. Is proportional to the area obtained by subtracting (subtracting) the area. When this area is calculated for the case where VZD 241 is set to 47 V, it becomes 53.25% of the area of the half cycle of Vdc. For this reason, when the resistance value of the resistor R241 is the same as the case where the Zener diode ZD241 is not provided (for example, the same as the resistance value of the resistor R141 of the first embodiment 100), the integration of Vref half cycle of Iref is performed. The value is smaller than when the Zener diode ZD241 is not provided.
In order to make the integral value of Vref half cycle of Iref equal to the case where the Zener diode ZD241 is not provided, the resistance value R241a may be reduced. For example, when the resistance value of the resistor R141 of the first embodiment 100 is R141a, the resistance value R241a may be set to [R241a = R141a × 0.5325].
Even if the resistance value R241a is changed (decreased), the phase advance of I1 does not increase even though it decreases.
If resistance value R241a is further reduced, I1 increases and the amplitude of the fundamental current increases. In this case, the amplitude ratio of the harmonic current to the amplitude of the fundamental wave current becomes small.
Further, the correlation between Iref and (Vdc−VZD241) can be set to a correlation different from the proportionality. For example, a circuit in which a resistor and a Zener diode are connected in series is connected in parallel with the resistor R241.
 第2の実施形態200の各回路要素の値を以下のように設定してシミュレーションした。
 Vac:AC100V,60Hz、L1:50μH、L2:600μH、Cp:0.6μF、C1:500μF、クロック周期:20μs(Hレベル期間:2μs(Vdc増加時)、2μs(Vdc減少時))、VZD241:48V、VLED平均値:15.4V、LED負荷電流平均値:729mA。
 シミュレーションした結果、力率は、0.98以上となった。また、第11~第39高調波電流の振幅は、基本波電流の振幅の2%以下となり、PFC規格を満たしている。なお、第40高調波以上の高調波電流の振幅は、周波数が8.3kHzの場合に3.7%となり、50kHzの場合に2.6%となったが、その他の周波数ではこれら以下になった。この場合、PFC規格を満たしているため、高調波電流を抑制するためのローパスフィルタを設ける必要がない。
 すなわち、閾値発生回路にツェナーダイオードZD241を設けることによって、第1の実施形態100の閾値補正回路150と同等の位相進み抑制効果を得ることができる。
 なお、第2の実施形態の力率改善方法は、第1の実施形態の閾値補正回路150と組み合わせて用いることもできる。この場合には、例えば、図1において、抵抗R141とT149の間にツェナーダイオードを追加し、抵抗R141の抵抗値を減少させる。
The simulation was performed by setting the values of the circuit elements of the second embodiment 200 as follows.
Vac: AC 100 V, 60 Hz, L1: 50 μH, L2: 600 μH, Cp: 0.6 μF, C1: 500 μF, clock cycle: 20 μs (H level period: 2 μs (when Vdc increases), 2 μs (when Vdc decreases)), VZD241: 48V, VLED average value: 15.4V, LED load current average value: 729 mA.
As a result of the simulation, the power factor was 0.98 or more. The amplitude of the 11th to 39th harmonic currents is 2% or less of the amplitude of the fundamental wave current, which satisfies the PFC standard. The amplitude of the harmonic current above the 40th harmonic was 3.7% when the frequency was 8.3 kHz and 2.6% when the frequency was 50 kHz, but it was less than these at other frequencies. It was. In this case, since the PFC standard is satisfied, it is not necessary to provide a low-pass filter for suppressing the harmonic current.
That is, by providing the Zener diode ZD241 in the threshold generation circuit, it is possible to obtain a phase advance suppression effect equivalent to that of the threshold correction circuit 150 of the first embodiment 100.
Note that the power factor correction method of the second embodiment can also be used in combination with the threshold correction circuit 150 of the first embodiment. In this case, for example, in FIG. 1, a Zener diode is added between the resistors R141 and T149 to decrease the resistance value of the resistor R141.
[第3の実施形態]
 図4に、本発明の電源装置の第3の実施形態300の回路図が示されている。
 第3の実施形態300は、第1の実施形態100のインダクタL131を除去し、インダクタL332とコンデンサC332の間にインダクタL331を配置している。インダクタL331は、第1の実施形態100のインダクタL131のインダクタンスL1と同じインダクタンスL1を有している。インダクタL332のインダクタンスL2は、第1の実施形態100と同様に、インダクタL331のインダクタンスL1より大きくなるように設定されている。
 なお、図4において、図1に示されている記号と、百番台の数字以外が一致する記号が付されている構成要素は、図1に示されている第1の実施形態の構成要素と同じものである。
 また、図4には、I1の波形を修正して力率を「1」に近づけるための第1の実施形態100の閾値補正回路あるいは第2の実施形態の閾値発生回路が図示されていないが、勿論、閾値補正回路と閾値発生回路の少なくとも一方を設けることもできる。この点は、以下に示す他の実施形態でも同様である。
[Third Embodiment]
FIG. 4 shows a circuit diagram of a third embodiment 300 of the power supply device of the present invention.
In the third embodiment 300, the inductor L131 of the first embodiment 100 is removed, and the inductor L331 is disposed between the inductor L332 and the capacitor C332. The inductor L331 has the same inductance L1 as the inductance L1 of the inductor L131 of the first embodiment 100. The inductance L2 of the inductor L332 is set to be larger than the inductance L1 of the inductor L331 as in the first embodiment 100.
In FIG. 4, the constituent elements to which the symbols shown in FIG. 1 and symbols other than the numbers in the hundreds are the same are the constituent elements of the first embodiment shown in FIG. The same thing.
FIG. 4 does not show the threshold correction circuit of the first embodiment 100 or the threshold generation circuit of the second embodiment for correcting the waveform of I1 to bring the power factor close to “1”. Of course, at least one of the threshold value correction circuit and the threshold value generation circuit may be provided. This is the same in other embodiments described below.
 第3の実施形態300は、以下のように動作する。
 スイッチング素子T331がオフのときは、全波整流回路310、インダクタL332、インダクタL331、コンデンサC332、切り替えスイッチSW331の固定接点eと常閉接点fおよび接地の経路で、コンデンサC332の充電電流I1が流れる。
 スイッチング素子T331がオンすると、コンデンサC332、インダクタL331、負荷320とコンデンサC331との並列回路、スイッチング素子T331、電流検出抵抗R331、接地および切り替えスイッチSW331の固定接点eと常閉接点fの経路で、コンデンサC332の放電電流I2が流れる。
 この時、全波整流回路310、インダクタL332、負荷320とコンデンサC331の並列回路、スイッチング素子T331、電流検出抵抗R331および接地の経路で、電流I4(図示省略)も流れる。しかしながら、[インダクタL332のインダクタンスL2≫インダクタL331のインダクタンスL1]の条件が満足されていると、[I2≫I4]となる。
The third embodiment 300 operates as follows.
When the switching element T331 is off, the charging current I1 of the capacitor C332 flows through the full-wave rectifier circuit 310, the inductor L332, the inductor L331, the capacitor C332, the fixed contact e of the changeover switch SW331, the normally closed contact f, and the ground path. .
When the switching element T331 is turned on, the capacitor C332, the inductor L331, the parallel circuit of the load 320 and the capacitor C331, the switching element T331, the current detection resistor R331, the ground and the switch SW331 fixed contact e and the normally closed contact f, A discharge current I2 of the capacitor C332 flows.
At this time, the current I4 (not shown) also flows through the full-wave rectifier circuit 310, the inductor L332, the parallel circuit of the load 320 and the capacitor C331, the switching element T331, the current detection resistor R331, and the ground path. However, when the condition [inductance L2 of inductor L332 >> inductance L1 of inductor L331] is satisfied, [I2 >> I4] is satisfied.
 なお、図1に示す第1の実施形態100においても、スイッチング素子T131がオンすると、全波整流回路110、インダクタL132、インダクタL131、負荷120とコンデンサC131の並列回路、スイッチング素子T131、電流検出抵抗R131および接地の経路で、電流I5(図示省略)が流れる。この場合も、[インダクタL132のインダクタンスL2≫インダクタ131のインダクタンスL1]の条件が満足されていると、[I2≫I5]となる。
 電流I5は、インダクタL132とインダクタL131を流れ、電流I4は、インダクタL232のみを流れているため、[I4>I5]となる。しかしながら、I4およびI5は、I2に比べると小さいため、図1に示されている回路と図4に示されている回路は等価な回路とみなすことができる。
Also in the first embodiment 100 shown in FIG. 1, when the switching element T131 is turned on, the full-wave rectifier circuit 110, the inductor L132, the inductor L131, the parallel circuit of the load 120 and the capacitor C131, the switching element T131, and the current detection resistor A current I5 (not shown) flows through the path of R131 and the ground. Also in this case, when the condition [inductance L2 of inductor L132 >> inductance L1 of inductor 131] is satisfied, [I2 >> I5] is satisfied.
Since the current I5 flows through the inductors L132 and L131, and the current I4 flows only through the inductor L232, [I4> I5] is satisfied. However, since I4 and I5 are smaller than I2, the circuit shown in FIG. 1 and the circuit shown in FIG. 4 can be regarded as equivalent circuits.
 第1の実施形態100と第3の実施形態300の違いは、スイッチング素子がオンした時のr点またはt点の電位の低下量が異なることである。
 第1の実施形態100では、スイッチング素子T131がオンしたとき、r点の電位は、コンデンサC132の正極端子の電位となるので、第3の実施形態より低下量が少なくなる。これにより、インダクタL132を流れる電流の変動が少なくなる。
 しかしながら、スイッチング素子T131オン時のr点の電位がふらつき易い。このため、インダクタL132を流れる電流の周期性が乱れ、クロック周期より長い周期の変動が発生し易くなる。
 これに対して、第3の実施形態300では、スイッチング素子T331オン時のt点の電位は、負荷電圧VLEDとなり、ふらつきが少ない。これにより、インダクタL332を流れる電流の周期性に優れる。一方、スイッチング素子T331オン時のt点の電位の低下量が大きいので、クロック周波数の高調波電流の振幅が大きくなる。
The difference between the first embodiment 100 and the third embodiment 300 is that the amount of decrease in potential at the point r or t when the switching element is turned on is different.
In the first embodiment 100, when the switching element T131 is turned on, the potential at the point r becomes the potential of the positive terminal of the capacitor C132, and therefore the amount of decrease is smaller than that in the third embodiment. Thereby, the fluctuation | variation of the electric current which flows through the inductor L132 decreases.
However, the potential at the point r when the switching element T131 is on is likely to fluctuate. For this reason, the periodicity of the current flowing through the inductor L132 is disturbed, and fluctuations with a period longer than the clock period are likely to occur.
On the other hand, in the third embodiment 300, the potential at the point t when the switching element T331 is on is the load voltage VLED, and there is little fluctuation. Thereby, it is excellent in the periodicity of the electric current which flows through the inductor L332. On the other hand, since the amount of decrease in the potential at the point t when the switching element T331 is on is large, the amplitude of the harmonic current of the clock frequency becomes large.
[第4の実施形態]
 第1~第3の実施形態では、スイッチング素子を負荷の他方端と全波整流回路の負極端の間に配置したが、スイッチング素子を負荷の一方端と全波整流回路の正極端の間に配置することもできる。
 図5に、本発明の電源装置の第4の実施形態400の回路図が示されている。第4の実施形態400では、負荷420の一方端431と全波整流回路410の正極端cの間に、スイッチング素子T431と電流検出抵抗R431を直列に配置している。
 制御回路440は、P型MOSFETであるT441~T443、T448、T449、N型MOSFETであるT444~T447、抵抗R441~R444、定電流源IDC441、クロック信号発生回路441、シュミットトリガーST451、DフリップフロップDFF441、AND回路AND441、駆動回路442により構成されている。
 電力供給回路430、制御回路440、電源回路480、駆動信号出力回路490は、負荷420の一方端431と全波整流回路410の正極端cの間に配置されているスイッチング素子T431を制御することができるように構成されている。
[Fourth Embodiment]
In the first to third embodiments, the switching element is disposed between the other end of the load and the negative end of the full-wave rectifier circuit. However, the switching element is disposed between one end of the load and the positive end of the full-wave rectifier circuit. It can also be arranged.
FIG. 5 shows a circuit diagram of a fourth embodiment 400 of the power supply device of the present invention. In the fourth embodiment 400, a switching element T431 and a current detection resistor R431 are arranged in series between one end 431 of the load 420 and the positive end c of the full-wave rectifier circuit 410.
The control circuit 440 includes P-type MOSFETs T441 to T443, T448 and T449, N-type MOSFETs T444 to T447, resistors R441 to R444, constant current source IDC441, clock signal generation circuit 441, Schmitt trigger ST451, and D flip-flop. The circuit includes a DFF 441, an AND circuit AND441, and a drive circuit 442.
The power supply circuit 430, the control circuit 440, the power supply circuit 480, and the drive signal output circuit 490 control the switching element T431 disposed between one end 431 of the load 420 and the positive end c of the full-wave rectifier circuit 410. It is configured to be able to.
 第4の実施形態400の動作は、第1の実施形態100の動作と類似している。
 スイッチング素子T431がオフの時は、全波整流回路410、コンデンサC432、インダクタL432および接地の経路で、コンデンサC432の充電電流が流れる。
 スイッチング素子T431がオンすると、コンデンサC432、電流検出抵抗R431、スイッチング素子T431、負荷420とコンデンサC431の並列回路およびインダクタL431の経路で、コンデンサC432の放電電流が流れる。
 電流検出抵抗R431の電圧降下(T431を流れる電流)が閾値より大きくなると、スイッチング素子T431がオフされる。この時、インダクタL431に蓄積された電磁エネルギーによって、インダクタL431、還流ダイオードD431および負荷420とコンデンサC431との並列回路の経路で、還流電流が流れる。
 インダクタL431のインダクタンスL1は、スイッチング素子T431のオフ期間内に還流電流が消滅する大きさに設定される。また、インダクタL432のインダクタンスL2は、スイッチング素子T431のオフ期間にコンデンサC432の充電電流が流れ続ける大きさに設定される。
The operation of the fourth embodiment 400 is similar to the operation of the first embodiment 100.
When the switching element T431 is off, the charging current of the capacitor C432 flows through the full-wave rectifier circuit 410, the capacitor C432, the inductor L432, and the ground path.
When the switching element T431 is turned on, the discharge current of the capacitor C432 flows through the capacitor C432, the current detection resistor R431, the switching element T431, the parallel circuit of the load 420 and the capacitor C431, and the path of the inductor L431.
When the voltage drop (current flowing through T431) of the current detection resistor R431 becomes larger than the threshold value, the switching element T431 is turned off. At this time, the return current flows through the path of the inductor L431, the return diode D431, and the parallel circuit of the load 420 and the capacitor C431 due to the electromagnetic energy accumulated in the inductor L431.
The inductance L1 of the inductor L431 is set to such a magnitude that the return current disappears during the OFF period of the switching element T431. Further, the inductance L2 of the inductor L432 is set to such a magnitude that the charging current of the capacitor C432 continues to flow during the OFF period of the switching element T431.
 第4の実施形態400では、スイッチング素子T431が負荷420の一方端(正極端)431と全波整流回路410の正極端cの間に配置されているため、スイッチング素子T431の下流の配線が接地して過電流が流れたとき、スイッチング素子T431および下流の配線を保護することができる。
 なお、第4の実施形態400において、インダクタL431と、負荷420とコンデンサC431の並列回路の位置を入れ替えてもよい。
In the fourth embodiment 400, since the switching element T431 is disposed between one end (positive electrode end) 431 of the load 420 and the positive electrode end c of the full-wave rectifier circuit 410, the wiring downstream of the switching element T431 is grounded. Thus, when an overcurrent flows, the switching element T431 and the downstream wiring can be protected.
In the fourth embodiment 400, the positions of the inductor L431, the parallel circuit of the load 420 and the capacitor C431 may be switched.
[第5の実施形態]
 第1~第4の実施形態の効率は、全波整流回路で用いられているダイオードの損失、スイッチング素子のスイッチング損失、電流検出抵抗の損失、還流ダイオードの損失等によって定まる。これらの損失の中で、還流ダイオードと全波整流回路のダイオードの損失が大きい。特に、還流ダイオードの損失が大きい。その理由は、全波整流回路のダイオードを流れる電流(I1)は、還流ダイオードを流れる還流電流(I3)より小さいからである。例えば、負荷の端子間電圧が20V、交流電圧の実効値が100Vである場合には、[I1/I3≒20V/100V=1/5]となる。また、I1は、直列接続された2個のダイオードを流れ、I3は、1個の還流ダイオードを流れる。このため、全波整流回路のダイオードの損失は、還流ダイオードの損失の約(1/2.5)となる。
 第5の実施形態では、還流電流が流れる時の損失を低減するために、第1~第4の実施形態で用いている還流ダイオードをMOSFETの寄生ダイオードに置き換えている。
[Fifth Embodiment]
The efficiency of the first to fourth embodiments is determined by the loss of the diode used in the full-wave rectifier circuit, the switching loss of the switching element, the loss of the current detection resistor, the loss of the freewheeling diode, and the like. Among these losses, the loss of the freewheeling diode and the diode of the full wave rectifier circuit is large. In particular, the loss of the return diode is large. This is because the current (I1) flowing through the diode of the full-wave rectifier circuit is smaller than the return current (I3) flowing through the freewheeling diode. For example, when the voltage between the terminals of the load is 20V and the effective value of the AC voltage is 100V, [I1 / I3≈20V / 100V = 1/5]. I1 flows through two diodes connected in series, and I3 flows through one freewheeling diode. For this reason, the loss of the diode of the full-wave rectifier circuit is about (1 / 2.5) of the loss of the freewheeling diode.
In the fifth embodiment, in order to reduce the loss when the return current flows, the return diode used in the first to fourth embodiments is replaced with a MOSFET parasitic diode.
 図6に、第5の実施形態500の回路図が示されている。
 第5の実施形態500では、第1の実施形態100の還流ダイオードD131がN型MOSFETであるFT532に置き換えられ、FT532の寄生ダイオードを介して還流電流を流すように構成されている。なお、「FT532」は、還流ダイオードとして用いられるFETを他のFETと区別するための簡略記号である。また、電圧検出回路560、駆動回路570が追加されている。
 第5の実施形態500は、FT532、電圧検出回路560、駆動回路570、電源回路580以外は、第1の実施形態100と同じ構成である。
 なお、図6において、図1に示されている記号と、百番台の数字以外が一致する記号が付されている構成要素は、図1に示されている第1の実施形態100の構成要素と同じものである。また、図6には、第5の実施形態500の要部のみが示されている。
 以下では、主に、本実施形態のFT532について説明する。
A circuit diagram of the fifth embodiment 500 is shown in FIG.
In the fifth embodiment 500, the freewheeling diode D131 of the first embodiment 100 is replaced with an FT532 that is an N-type MOSFET, and a freewheeling current is passed through a parasitic diode of the FT532. “FT532” is a simple symbol for distinguishing an FET used as a freewheeling diode from other FETs. In addition, a voltage detection circuit 560 and a drive circuit 570 are added.
The fifth embodiment 500 has the same configuration as the first embodiment 100 except for the FT 532, the voltage detection circuit 560, the drive circuit 570, and the power supply circuit 580.
In FIG. 6, the constituent elements to which the symbols shown in FIG. 1 and the symbols other than the numbers in the hundreds are the same are the constituent elements of the first embodiment 100 shown in FIG. Is the same. FIG. 6 shows only the main part of the fifth embodiment 500.
Below, FT532 of this embodiment is mainly demonstrated.
 電源回路580は、負荷520の一方端531と他方端532の間に配置されている、N型MOSFETであるT581、抵抗R581、ツェナーダイオードZD581およびコンデンサC581を有している。電源回路580は、FT532のドレイン・ソース間の電圧(寄生ダイオードのアノードとカソード間の電圧)を検出する電圧検出回路560、FT532を駆動する駆動回路570に電源を供給する。 The power supply circuit 580 includes an N-type MOSFET T581, a resistor R581, a Zener diode ZD581, and a capacitor C581, which are disposed between one end 531 and the other end 532 of the load 520. The power supply circuit 580 supplies power to the voltage detection circuit 560 that detects the voltage between the drain and source of the FT 532 (the voltage between the anode and cathode of the parasitic diode) and the drive circuit 570 that drives the FT 532.
 電圧検出回路560は、P型MOSFETであるT561、T563、T566、N型MOSFETであるT562、T564、T565、T567、抵抗R561~R564、直流電源V560により構成されている。
 抵抗R561の端子間電圧は定電圧になるので、抵抗R561を流れる電流は定電流になる。
 T567および直流電源V560は、スイッチング素子T531がオンしたとき、FT532のドレイン・ソース間に発生する大きな電圧が抵抗R564およびR563を介してT564のソースに入力されるのを防止するためのドレイン電圧入力制限回路を構成している。
 T561とT563として、同じ特性を有するFETが用いられ、T562とT564として、同じ特性を有するFETが用いられている。また、抵抗R562とR563として、同じ抵抗値を有する抵抗が用いられている。
The voltage detection circuit 560 includes P-type MOSFETs T561, T563, and T566, N-type MOSFETs T562, T564, T565, and T567, resistors R561 to R564, and a DC power supply V560.
Since the voltage between the terminals of the resistor R561 becomes a constant voltage, the current flowing through the resistor R561 becomes a constant current.
T567 and DC power supply V560 are drain voltage inputs for preventing a large voltage generated between the drain and source of FT532 from being input to the source of T564 via resistors R564 and R563 when switching element T531 is turned on. A limiting circuit is configured.
FETs having the same characteristics are used as T561 and T563, and FETs having the same characteristics are used as T562 and T564. In addition, resistors having the same resistance value are used as the resistors R562 and R563.
 駆動回路570は、P型MOSFETであるT571、T573、T574、N型MOSFETであるT572、T575、T576、抵抗R571~R576、ダイオードD561、ツェナーダイオードZD561、シュミットトリガーST571、非安定マルチバイブレータ1Shot571により構成されている。
 図1のs点の電圧が、ST571を介して1Shot571のトリガー端子Trigに入力される。1Shot571は、リセット端子Rバーに入力されるs点の電圧がLレベルのときにリセットされる。
The drive circuit 570 includes P-type MOSFETs T571, T573, and T574, N-type MOSFETs T572, T575, and T576, resistors R571 to R576, a diode D561, a Zener diode ZD561, a Schmitt trigger ST571, and an astable multivibrator 1Shot571. Has been.
The voltage at point s in FIG. 1 is input to the trigger terminal Trig of 1 Shot 571 via ST571. 1Shot 571 is reset when the voltage at point s input to the reset terminal R is at L level.
 本実施形態の動作を説明する。
 抵抗R564の抵抗値が0Ωである場合について説明する。
 スイッチング素子T531がオフすると、インダクタL531に蓄積されている電磁エネルギーによって還流電流が流れる。
 還流電流によってFT532の寄生ダイオードが順バイアスされると、FT532のドレイン電圧がソース電圧より低くなり、T564はT562のドレイン電流より大きい電流を流し得るようになる。これにより、T563とT564の接続点の電圧が低下する。そして、T565のソースとT566のソースとの接続点w点の電圧が低下し、T576がオフする。同時に、T572がオフし、T571がオフする。
The operation of this embodiment will be described.
A case where the resistance value of the resistor R564 is 0Ω will be described.
When the switching element T531 is turned off, a return current flows due to electromagnetic energy accumulated in the inductor L531.
When the parasitic diode of FT532 is forward-biased by the return current, the drain voltage of FT532 becomes lower than the source voltage, and T564 can pass a current larger than the drain current of T562. Thereby, the voltage of the connection point of T563 and T564 falls. Then, the voltage at the connection point w between the source of T565 and the source of T566 decreases, and T576 is turned off. At the same time, T572 is turned off and T571 is turned off.
 一方、スイッチング素子T531がオンからオフに移行すると、s点電圧がLレベルからHレベルへ変化する。この変化がST571を介して1Shot571のトリガー端子Trigに入力されると、非反転出力+Qが一定時間Hレベルになる。“一定時間”は、還流電流が流れ始めてから消滅するまでの時間より短い時間に設定される。例えば、クロック周期が30μs程度である場合には、約3μsに設定するのが好ましい。
 これにより、スイッチング素子T531がオフした後、約3μs間T575がオンし、抵抗R575が接地される。このとき、FT532のソース電圧がコンデンサC532の正極端子電圧VCpより高くなる。この状態において、T574のゲート電圧、すなわち、抵抗R574とR575の接続点電圧が、Vdcのいかなる値においてもFT532のソース電圧より低くなるように、抵抗R574とR575の抵抗値を設定することができる。
 このように抵抗R574と抵抗575の抵抗値を設定すると、スイッチング素子T531がオフした後、約3μs間T574がオンする。これにより、T573がこの間オンすることができ、FT532のゲートが充電されてFT532がオンする。
 1Shot571の非反転出力+QがHレベルとなる一定時間が、本発明の「所定期間」に対応する。
On the other hand, when the switching element T531 shifts from on to off, the s-point voltage changes from the L level to the H level. When this change is input to the trigger terminal Trig of 1 Shot 571 via ST571, the non-inverted output + Q becomes H level for a certain time. The “certain time” is set to a time shorter than the time from when the reflux current starts to flow until it disappears. For example, when the clock period is about 30 μs, it is preferably set to about 3 μs.
Thereby, after the switching element T531 is turned off, T575 is turned on for about 3 μs, and the resistor R575 is grounded. At this time, the source voltage of the FT532 becomes higher than the positive terminal voltage VCp of the capacitor C532. In this state, the resistance values of the resistors R574 and R575 can be set such that the gate voltage of T574, that is, the connection voltage of the resistors R574 and R575 is lower than the source voltage of the FT532 at any value of Vdc. .
When the resistance values of the resistor R574 and the resistor 575 are set in this manner, the switching element T531 is turned off, and then the T574 is turned on for about 3 μs. Thereby, T573 can be turned on during this period, the gate of FT532 is charged, and FT532 is turned on.
A certain time during which the non-inverted output + Q of 1 Shot 571 becomes H level corresponds to the “predetermined period” of the present invention.
 還流電流が単調減少すると、FT532の寄生ダイオードの順方向電圧が低下し、[ドレイン電圧<ソース電圧]の状態で、その差がゼロに近づく。これにより、w点の電圧が上昇し、T576がオンする。この時点では、T575が既にオフしているので、T571が例えオフであっても、抵抗R576によりT573のソース・ゲート間電圧がゼロになる。これにより、T573がオフ状態を維持するため、FT532がオフする。
 抵抗R564が0Ωである場合には、還流電流がゼロクロスに至るときに、w点電圧が上昇を始める。ここで、FT532のオフ遅れがあるため、FT532が実質的にオフするのは、還流電流がゼロクロスを超え、逆方向に流れ始めるタイミングとなる。このタイミングでオフすると、インダクタL531に逆起電力が発生し、インダクタL531のインダクタンスとFT532のドレイン・ソース間の容量が共振して、FT532のドレイン・ソース間電圧がハンチングする。これを避けるには、還流電流がゼロクロスに達する前にFT532を遮断すればよい。これを実現するために、抵抗R564が設けられている。抵抗R564の抵抗値を大きくするに連れて、遮断タイミングが早まる。
When the return current monotonously decreases, the forward voltage of the parasitic diode of FT532 decreases, and the difference approaches zero in the state of [drain voltage <source voltage]. As a result, the voltage at the point w increases and T576 is turned on. At this point, since T575 is already off, even if T571 is off, the source-gate voltage of T573 becomes zero by the resistor R576. Thereby, since T573 maintains an off state, FT532 is turned off.
When the resistance R564 is 0Ω, the w-point voltage starts to rise when the return current reaches the zero cross. Here, since there is an FT532 OFF delay, the FT532 is substantially turned OFF at a timing when the return current exceeds the zero cross and starts to flow in the reverse direction. When turned off at this timing, back electromotive force is generated in the inductor L531, the inductance of the inductor L531 and the capacitance between the drain and source of the FT532 resonate, and the drain-source voltage of the FT532 is hunted. To avoid this, the FT 532 may be cut off before the return current reaches the zero cross. In order to realize this, a resistor R564 is provided. As the resistance value of the resistor R564 is increased, the cutoff timing is advanced.
 以上を整理すると、スイッチング素子T531がオフして還流電流が流れ始めると、約3μs間T575がオンする。同時に、FT532のソース・ドレイン間電圧の大きさを検出する電圧検出回路560の出力であるw点電圧が低下し、T576およびT572がオフする。この時、T575がオンしているので、T573がオンする。これにより、FT532のゲートにプラス電圧が印加され、ゲートが充電されてFT532がオンする。
 約3μs経過すると、T575がオフするので、T573がオフし、FT532のゲートへの電圧印加がなくなる。この状態になっても、FT532のゲートに蓄積された電荷を放電する経路がない。このため、FT532のゲートがソースより高い電圧に保持され、FT532は、オンを維持する。
 還流電流がゼロクロスに近づくと、電圧検出回路560の出力(w点電圧)が上昇し、T576がオンする。これにより、FT532のゲートに蓄積された電荷が放電されるので、FT532がオフする。すなわち、FT532は、スイッチング素子T531のオフ直後にオンし、ゼロクロス直前までオンを維持し、ゼロクロス以前にオフする。
 これにより、スイッチング素子T531がオフして、インダクタL531により還流電流がFT532を流れるときの損失を低減することができる。
In summary, when the switching element T531 is turned off and the return current starts to flow, T575 is turned on for about 3 μs. At the same time, the w point voltage, which is the output of the voltage detection circuit 560 that detects the magnitude of the source-drain voltage of the FT 532, decreases, and T576 and T572 are turned off. At this time, since T575 is on, T573 is on. As a result, a positive voltage is applied to the gate of FT532, the gate is charged, and FT532 is turned on.
When about 3 μs elapses, T575 is turned off, so that T573 is turned off and voltage application to the gate of FT532 is stopped. Even in this state, there is no path for discharging the charge accumulated in the gate of FT532. For this reason, the gate of FT532 is held at a voltage higher than that of the source, and FT532 is kept on.
When the return current approaches the zero cross, the output (voltage at the point w) of the voltage detection circuit 560 increases and T576 is turned on. As a result, the charge accumulated in the gate of FT532 is discharged, so that FT532 is turned off. That is, the FT 532 is turned on immediately after the switching element T531 is turned off, is kept on until just before the zero cross, and is turned off before the zero cross.
Thereby, the switching element T531 is turned off, and the loss when the return current flows through the FT532 by the inductor L531 can be reduced.
 図7に、第5の実施形態500をシミュレーションしたときの各部の波形が示されている。
 シミュレーションの条件は次の通りである。
 交流電圧Vac:100V,60Hz、インダクタL531のインダクタンスL1:70μH、インダクタL532のインダクタンスL2:600μH、コンデンサC531の容量C1:500μF、コンデンサC532の容量Cp:0.3μF、負荷520:LEDスタック(6個直列×6並列)、電流検出抵抗R531の抵抗値R1:0.08Ω、抵抗R561の抵抗値:300kΩ、抵抗R562の抵抗値および抵抗R563の抵抗値:2kΩ、抵抗R564の抵抗値:500Ω、定電流源IDC141の電流11:40μA、クロック周期:30μs、1Shot571のタイマー時間:3μs、ツェナーダイオードZD581のツェナー電圧:18V、コンデンサC581の容量C2:1μF。
FIG. 7 shows the waveforms of the respective parts when the fifth embodiment 500 is simulated.
The simulation conditions are as follows.
AC voltage Vac: 100 V, 60 Hz, inductor L531 inductance L1: 70 μH, inductor L532 inductance L2: 600 μH, capacitor C531 capacitance C1: 500 μF, capacitor C532 capacitance Cp: 0.3 μF, load 520: LED stack (6 pieces) (Series × 6 parallel), resistance value R1 of current detection resistor R531, 0.08Ω, resistance value of resistor R561: 300kΩ, resistance value of resistor R562 and resistance value of resistor R563: 2kΩ, resistance value of resistor R564: 500Ω, constant Current source IDC 141 current 11: 40 μA, clock period: 30 μs, 1 Shot 571 timer time: 3 μs, Zener diode ZD581 Zener voltage: 18 V, Capacitor C581 capacitance C2: 1 μF.
 図7において、横軸は経過時間t(ms)を表し、縦軸の第1軸はグラフ(1)~(3)の電圧(V)を表し、縦軸の第2軸はグラフ(4)~(6)の電圧(V)を表し、縦軸の第3軸はグラフ(7)の電流(A)を表している。
 また、グラフ(1)(白丸が付された一点鎖線)は、コンデンサC531の正極電圧(V:第1軸)を表している。グラフ(2)(黒丸が付された二点破線)は、コンデンサC531の負極電圧(V:第1軸)を表している。グラフ(3)(白三角が付された破線)は、コンデンサC532の正極端子電圧VCp(V:第1軸)を表している。グラフ(4)(白四角が付された一点鎖線)は、T574のソース・ドレイン間電圧(V:第2軸)を表している。グラフ(5)(黒四角が付された一点鎖線)は、FT532のゲート・ソース間電圧)(V:第2軸)を表している。グラフ(6)(黒三角が付された破線)は、[w点-FT532のソース間電圧](V:第2軸)を表している。グラフ(7)(実線)は、インダクタL531を流れる電流IL1(A:第3軸)を表している。
In FIG. 7, the horizontal axis represents the elapsed time t (ms), the first vertical axis represents the voltage (V) of the graphs (1) to (3), and the second vertical axis represents the graph (4). (6) represents the voltage (V), and the third axis of the vertical axis represents the current (A) in the graph (7).
Further, the graph (1) (the one-dot chain line with a white circle) represents the positive voltage (V: first axis) of the capacitor C531. Graph (2) (two-dot broken line with black circles) represents the negative voltage (V: first axis) of capacitor C531. Graph (3) (broken line with a white triangle) represents the positive terminal voltage VCp (V: first axis) of the capacitor C532. A graph (4) (a dashed-dotted line with a white square) represents a source-drain voltage (V: second axis) of T574. A graph (5) (a dashed-dotted line with a black square) represents a gate-source voltage of FT532 (V: second axis). Graph (6) (broken line with a black triangle) represents [w point−source voltage of FT532] (V: second axis). Graph (7) (solid line) represents current IL1 (A: third axis) flowing through inductor L531.
 図7の波形から以下のことが分かる。
 経過時間[30.86ms]で、スイッチング素子T531がオンし、インダクタL531に流れる電流が直線的に増大する。このときのインダクタL131の電流IL1は、コンデンサC532の放電電流I2が大部分を占めている。コンデンサC532の放電により、コンデンサC532の正極端子電圧VCpが低下する。
 IL1が5Aになった時点で、スイッチング素子T531がオフする。これにより、スイッチング素子T531オン時に接地レベルまで低下していたコンデンサC531の負極端子電圧が、インダクタL531の逆起電力により急上昇し、コンデンサC532の正極端子電圧VCpを超える。これにより、インダクタL531、負荷520とコンデンサC531の並列回路およびFT532の寄生ダイオードの経路で、還流電流I3が流れる。この時、コンデンサC531の負極端子電圧は、コンデンサC532の正極端子電圧VCpをわずかに超えた電圧にクランプされる。
 1Shot571によりT574がオンし、T574のソース・ドレイン間電圧がスイッチング素子T531のオフ後3μs間ゼロになる。この間にFT532の寄生ダイオードに順方向電流が流れ、[w点-FT532のソース間電圧]がゼロまで低下する。これにより、T576がオフし、T573がオンするので、FT532のゲート・ソース間が充電されてFT532がオンする。
 インダクタL531による還流電流IL1が単調減少し、ゼロクロスに近づくと、[w点-FT532のソース間電圧]が上昇する。これにより、T576がオンし、FT532のゲートの電荷が放電し、FT532がオフする。
 インダクタL531の電流IL1がゼロになった後、コンデンサC531の負極端子電圧がコンデンサC532の正極端子電圧VCpより低下し、1周期が完了する。
The following can be understood from the waveform of FIG.
At the elapsed time [30.86 ms], the switching element T531 is turned on, and the current flowing through the inductor L531 increases linearly. At this time, most of the current IL1 of the inductor L131 is the discharge current I2 of the capacitor C532. Due to the discharge of the capacitor C532, the positive terminal voltage VCp of the capacitor C532 decreases.
When IL1 reaches 5A, the switching element T531 is turned off. As a result, the negative terminal voltage of the capacitor C531 that has dropped to the ground level when the switching element T531 is turned on rises rapidly due to the back electromotive force of the inductor L531, and exceeds the positive terminal voltage VCp of the capacitor C532. Thereby, the return current I3 flows through the path of the inductor L531, the parallel circuit of the load 520 and the capacitor C531, and the parasitic diode of the FT532. At this time, the negative terminal voltage of the capacitor C531 is clamped to a voltage slightly exceeding the positive terminal voltage VCp of the capacitor C532.
1 Shot 571 turns on T574, and the source-drain voltage of T574 becomes zero for 3 μs after the switching element T531 is turned off. During this time, a forward current flows through the parasitic diode of the FT 532, and [w point−the voltage between the sources of the FT 532] decreases to zero. As a result, T576 is turned off and T573 is turned on, so that the gate and the source of FT532 are charged and FT532 is turned on.
When the return current IL1 due to the inductor L531 monotonously decreases and approaches the zero cross, [w point−the voltage between the sources of the FT532] increases. Thereby, T576 is turned on, the charge of the gate of FT532 is discharged, and FT532 is turned off.
After the current IL1 of the inductor L531 becomes zero, the negative terminal voltage of the capacitor C531 is lower than the positive terminal voltage VCp of the capacitor C532, and one cycle is completed.
[第6の実施形態]
 図1に示されている第1の実施形態100において、インダクタL131と、負荷120とコンデンサC131の並列回路の位置を入れ替えても機能は変わらない。しかしながら、この場合、還流ダイオードをMOSFETの寄生ダイオードに置き換えるためには、図6に示されている構成を用いることができない。第6の実施形態では、還流ダイオードをMOSFETの寄生ダイオードに置き換えるための他の構成を用いている。図8に、第6の実施形態600の回路図が示されている。
 第6の実施形態600は、FT632、電圧検出回路660、駆動回路670、電源回路680以外は、第1の実施形態100と同じ構成である。
 なお、図8において、図1に示されている記号と、百番台の数字以外が一致する記号が付されている構成要素は、図1に示されている第1の実施形態100の構成要素と同じものである。また、図8には、第6の実施形態600の要部のみが示されている。
[Sixth Embodiment]
In the first embodiment 100 shown in FIG. 1, the function does not change even if the position of the parallel circuit of the inductor L131, the load 120, and the capacitor C131 is changed. However, in this case, the configuration shown in FIG. 6 cannot be used to replace the free wheel diode with the parasitic diode of the MOSFET. In the sixth embodiment, another configuration for replacing the freewheeling diode with a parasitic diode of the MOSFET is used. FIG. 8 shows a circuit diagram of the sixth embodiment 600.
The sixth embodiment 600 has the same configuration as that of the first embodiment 100 except for the FT 632, the voltage detection circuit 660, the drive circuit 670, and the power supply circuit 680.
In FIG. 8, the components to which the symbols shown in FIG. 1 and symbols other than the numbers in the hundreds are the same are the components of the first embodiment 100 shown in FIG. 1. Is the same. Further, FIG. 8 shows only the main part of the sixth embodiment 600.
 本実施形態600では、インダクタL631が、負荷620とコンデンサC631の並列回路より負極側に配置されている。このため、還流ダイオードと置き換えられるFT632としてP型MOSFETを用いている。第6の実施形態600の、FT632を制御する回路は、第5の実施形態500の、FT532を制御する回路と構成が異なっているが、コンセプトは同じである。 In the present embodiment 600, the inductor L631 is arranged on the negative electrode side from the parallel circuit of the load 620 and the capacitor C631. For this reason, a P-type MOSFET is used as the FT 632 to be replaced with the freewheeling diode. The circuit for controlling the FT 632 of the sixth embodiment 600 is different in configuration from the circuit for controlling the FT 532 of the fifth embodiment 500, but the concept is the same.
 電源回路680は、P型MOSFETであるT681、抵抗R681、ツェナーダイオードZD681およびコンデンサC681により構成されている。FT632を制御する回路は、コンデンサC632の正極端子電圧VCpを基準とし、それよりツェナーダイオードZD681のツェナー電圧だけ低い範囲で動作する。
 電圧検出回路660は、P型MOSFETであるT661、T663、T666、T667、N型MOSFETであるT662、T664、T665、抵抗R661~R664、直流電源V660により構成されている。
 駆動回路670は、P型MOSFETであるT671~T673、N型MOSFETであるT674~T676、抵抗R671~R676、ツェナーダイオードZD671、シュミットトリガーST671、非安定マルチバイブレータ1Shot671により構成されている。
The power supply circuit 680 includes a P-type MOSFET T681, a resistor R681, a Zener diode ZD681, and a capacitor C681. The circuit that controls the FT 632 operates within a range lower than the Zener voltage of the Zener diode ZD681 with reference to the positive terminal voltage VCp of the capacitor C632.
The voltage detection circuit 660 includes P-type MOSFETs T661, T663, T666, and T667, N-type MOSFETs T662, T664, and T665, resistors R661 to R664, and a DC power supply V660.
The drive circuit 670 includes P-type MOSFETs T671 to T673, N-type MOSFETs T674 to T676, resistors R671 to R676, a Zener diode ZD671, a Schmitt trigger ST671, and an astable multivibrator 1Shot671.
 本実施形態600の動作を説明する。
 図1のs点の電位が上昇し、ST671を介して1Shot671のトリガー端子TrigにHレベルの信号が入力されると、非反転出力+Qが約3μs間Hレベルになる。これにより、T676およびT672がオンする。
 同時に、FT632の寄生ダイオードが順方向にバイアスされ、インダクタL631による還流電流が流れる。そして、FT632のドレイン電圧が、ソース電圧より寄生ダイオードの順方向電圧降下分だけ大きくなる。これにより、x点の電位が上昇し、T671およびT673がオフし、T674がオフする。T672がオンしているのでT675がオンし、FT632のゲート電圧がソース電圧より低下してFT632がオンする。
 スイッチング素子T631オフ後3μs経過すると、T672がオフする。この時、FT632のゲートの電荷が残っているので、FT632はオンを維持する。
 還流電流が単調減少してゼロクロスに近づくと、x点の電位が低下してT673がオンする。同時に、T671およびT674がオンするので、T675がオフを維持し、FT632がオフする。すなわち、FT632は、スイッチング素子T631がオフした直後にオンし、還流電流がゼロクロスに至る前にオフする。これにより、還流電流によるFT632の電力損失を低減することができる。
The operation of the present embodiment 600 will be described.
When the potential at point s in FIG. 1 rises and an H level signal is input to the trigger terminal Trig of 1 Shot 671 via ST671, the non-inverted output + Q becomes H level for about 3 μs. Thereby, T676 and T672 are turned on.
At the same time, the parasitic diode of the FT 632 is forward-biased, and a return current by the inductor L631 flows. Then, the drain voltage of the FT 632 becomes larger than the source voltage by the forward voltage drop of the parasitic diode. As a result, the potential at the point x increases, T671 and T673 are turned off, and T674 is turned off. Since T672 is turned on, T675 is turned on, the gate voltage of FT632 is lower than the source voltage, and FT632 is turned on.
When 3 μs elapses after the switching element T631 is turned off, T672 is turned off. At this time, since the gate charge of the FT 632 remains, the FT 632 is kept on.
When the reflux current monotonously decreases and approaches the zero cross, the potential at the point x decreases and T673 is turned on. At the same time, since T671 and T674 are turned on, T675 remains off and FT632 is turned off. That is, the FT 632 is turned on immediately after the switching element T631 is turned off, and turned off before the return current reaches the zero cross. Thereby, the power loss of FT632 by return current can be reduced.
[第7の実施形態]
 図9に、還流ダイオードをMOSFETの寄生ダイオードに置き換えるための他の構成を用いた第7の実施形態700の回路図が示されている。
 第7の実施形態700は、FT732、電圧検出回路760、駆動回路770以外は、第1の実施形態100と同じ構成である。
 なお、図9において、図1に示されている記号と、百番台の数字以外が一致する記号が付されている構成要素は、図1に示されている第1の実施形態100の構成要素と同じものである。また、図9には、第7の実施形態700の要部のみが示されている。
 本実施形態では、還流ダイオードが、N型MOSFETであるFT732の寄生ダイオードに置き換えられている。
[Seventh Embodiment]
FIG. 9 shows a circuit diagram of a seventh embodiment 700 using another configuration for replacing the free wheel diode with a MOSFET parasitic diode.
The seventh embodiment 700 has the same configuration as that of the first embodiment 100 except for the FT 732, the voltage detection circuit 760, and the drive circuit 770.
In FIG. 9, the components to which the symbols shown in FIG. 1 and symbols other than the numbers in the hundreds are the same are the components of the first embodiment 100 shown in FIG. 1. Is the same. FIG. 9 shows only the main part of the seventh embodiment 700.
In this embodiment, the freewheeling diode is replaced with a parasitic diode of FT732 which is an N-type MOSFET.
 電圧検出回路760は、P型MOSFETであるT761、T763、N型MOSFETであるT762、T764、抵抗R761~R764、ダイオードD761、D762、ツェナーダイオードZD761により構成されている。
 ダイオードD762、抵抗R763、T763、抵抗R764およびT764が直列に配置された第1の直列回路がFT732のドレインと接地間に配置され、FT732のドレインと接地間の電圧の大きさに応じた電流が流れるように構成されている。
 ダイオードD761、抵抗R761、T761、抵抗R762およびT762が直列に配置された第2の直列回路がFT732のソースと接地間に配置され、FT732の寄生ダイオードが順方向にバイアスされたとき、FT732のソース・ドレイン間の差電圧に応じた電流が流れるように構成されている。
 T761とT763として、同じ特性を有するFETが用いられ、T762とT764として、同じ特性を有するFETが用いられている。
 抵抗R762の抵抗値は、第2の直列回路に流れ得る(流すことができる)電流が第1の直列回路の電流と等しいとき、抵抗R762に発生する電圧降下が、抵抗R764に発生する電圧降下より小さくなるように設定されている。この場合、抵抗R762の抵抗値は、抵抗R764の抵抗値より小さくなる。
The voltage detection circuit 760 includes P-type MOSFETs T761 and T763, N-type MOSFETs T762 and T764, resistors R761 to R764, diodes D761 and D762, and a Zener diode ZD761.
A first series circuit in which a diode D762, resistors R763 and T763, resistors R764 and T764 are arranged in series is arranged between the drain of the FT732 and the ground, and a current corresponding to the magnitude of the voltage between the drain of the FT732 and the ground It is configured to flow.
When a second series circuit in which a diode D761, resistors R761, T761, resistors R762 and T762 are arranged in series is arranged between the source of FT732 and the ground, and the parasitic diode of FT732 is forward-biased, the source of FT732 -It is comprised so that the electric current according to the voltage difference between drains may flow.
FETs having the same characteristics are used as T761 and T763, and FETs having the same characteristics are used as T762 and T764.
When the current that can flow through the second series circuit is equal to the current in the first series circuit, the voltage drop generated in the resistor R762 is the voltage drop generated in the resistor R764. It is set to be smaller. In this case, the resistance value of the resistor R762 is smaller than the resistance value of the resistor R764.
 抵抗R761の抵抗値と抵抗R763の抵抗値が等しい場合、FT732のドレイン・ソース間電圧がゼロであれば、第1の直列回路を流れる電流と第2の直列回路を流れる電流が等しくなる。一方、FT732のソース電圧がドレイン電圧より大きくなると、第2の直列回路に、第1の直列回路より大きな電流が流れ得るようになる。この時、アクティブロードの原理により、T762のソース・ドレイン間電圧が拡大する。これにより、T762と抵抗R762の接続点zの電圧が上昇し、シュミットトリガーST772の出力がHレベルとなる。このとき、第2の直列回路には第1の直列回路に流れる電流と同じ大きさの電流が流れる。これにより、T762のドレイン・ソース間電圧は、抵抗R762に発生する電圧降下により拡大が制限される。T762のドレイン・ソース間電圧の拡大の制限幅は、抵抗R762の抵抗値と抵抗R764の抵抗値の差が小さい程小さくなる。
 抵抗R761の抵抗値を抵抗R763の抵抗値より少し大きな値に設定すると、FT732のソース電圧が、ドレイン電圧より大きい範囲でドレイン電圧に接近すると、ドレイン・ソース間電圧がゼロになる前に、第2の直列回路の電流が第1の直列回路の電流より小さくなり、T762が飽和する。これにより、T761のドレイン・ソース間電圧が拡大してz点の電圧が低下し、ST772の出力がLレベルとなる。
When the resistance value of the resistor R761 is equal to the resistance value of the resistor R763, if the drain-source voltage of the FT732 is zero, the current flowing through the first series circuit is equal to the current flowing through the second series circuit. On the other hand, when the source voltage of FT732 becomes larger than the drain voltage, a larger current can flow in the second series circuit than in the first series circuit. At this time, the source-drain voltage of T762 increases due to the principle of active load. As a result, the voltage at the connection point z between T762 and the resistor R762 increases, and the output of the Schmitt trigger ST772 becomes H level. At this time, a current having the same magnitude as the current flowing through the first series circuit flows through the second series circuit. Thereby, the expansion of the drain-source voltage of T762 is limited by the voltage drop generated in the resistor R762. The limit width of the increase of the drain-source voltage at T762 becomes smaller as the difference between the resistance value of the resistor R762 and the resistance value of the resistor R764 is smaller.
When the resistance value of the resistor R761 is set to a value slightly larger than the resistance value of the resistor R763, when the source voltage of the FT732 approaches the drain voltage in a range larger than the drain voltage, before the drain-source voltage becomes zero, The current of the series circuit 2 becomes smaller than that of the first series circuit, and T762 is saturated. As a result, the drain-source voltage at T761 increases, the voltage at point z decreases, and the output at ST772 goes to L level.
 スイッチング素子T731がオンすると、FT732のソース電圧が接地電圧まで低下する。これにより、第2の直列回路に電流が流れなくなり、抵抗R762の電圧降下がゼロになる。
 T762が飽和すると、T761のドレイン電圧がT762のドレイン電圧に等しくなる。これにより、T761のソース・ドレイン間電圧がコンデンサC732の正極端子電圧VCpまで拡大する。その最大値は、交流電圧のピーク値に近づく。
 これを防止するには、ツェナーダイオードZD761をFT732のドレインとT761のドレインの間に配置し、T761のソース・ドレイン間電圧の拡大を制限する。
When the switching element T731 is turned on, the source voltage of the FT732 decreases to the ground voltage. As a result, no current flows through the second series circuit, and the voltage drop across the resistor R762 becomes zero.
When T762 is saturated, the drain voltage of T761 becomes equal to the drain voltage of T762. Thereby, the source-drain voltage of T761 is expanded to the positive terminal voltage VCp of the capacitor C732. The maximum value approaches the peak value of the AC voltage.
In order to prevent this, a Zener diode ZD761 is arranged between the drain of FT732 and the drain of T761 to limit the expansion of the source-drain voltage of T761.
 駆動回路770は、N型MOSFETであるT771、T773~T776、P型MOSFETであるT772、抵抗R771、R772、シュミットトリガーST771、ST772、非安定マルチバイブレータ1Shot771、AND回路AND771、直流電源V770により構成されている。
 T771とT772は、プッシュプル回路を構成するように配置されている。
The drive circuit 770 includes N-type MOSFETs T771 and T773 to T776, P-type MOSFETs T772, resistors R771 and R772, Schmitt triggers ST771 and ST772, an astable multivibrator 1 Shot 771, an AND circuit AND771, and a DC power supply V770. ing.
T771 and T772 are arranged to constitute a push-pull circuit.
 本実施形態700の動作を説明する。
 スイッチング素子T731がオンすると、T732のソースが接地され、抵抗R762とT762のドレインとの接続点zの電位が低下する。これにより、ST772の出力がLレベルとなり、AND771の出力がLとなる。これにより、T776がオフし、T775に定電流I8が流れる。また、抵抗R771、T773およびT774に、電流I8に等しい電流が流れ、T771がオフし、T772がオンし、FT732はオフする。
 スイッチング素子T731がオフすると、s点の電位が上昇し、1Shot771の出力+Qが一定期間Hレベルとなる。
 スイッチング素子T731のオフにより、還流電流I3が流れる。これにより、FT732の寄生ダイオードが順方向にバイアスされ、FT732のソース電圧がドレイン電圧より大きくなる。
 z点の電位が上昇すると、ST772の出力がHレベルになる。これにより、AND771の出力がHレベルになり、T776がオンする。T776がオンすると、T775に流れていた電流I8が遮断され、抵抗R771に流れていた電流がゼロになる。これにより、T771がオンし、T772がオフしてFT732がオンする。
 還流電流I3が減少してゼロになると、z点の電位が低下する。これにより、ST772の出力がLレベルとなり、T776がオフし、FT732がオフする。
 z点の電位が低下してFT732がオフするまでに遅れ時間があるため、FT732のソース・ドレイン間電圧がゼロになる前にz点の電位を立ち下げることが好ましい。このためには、抵抗R761の抵抗値を抵抗R763の抵抗値より若干大きく設定する必要がある。
The operation of the embodiment 700 will be described.
When the switching element T731 is turned on, the source of T732 is grounded, and the potential at the connection point z between the resistors R762 and T762 is lowered. As a result, the output of ST772 becomes L level and the output of AND771 becomes L. As a result, T776 is turned off, and a constant current I8 flows through T775. Further, a current equal to the current I8 flows through the resistors R771, T773, and T774, T771 is turned off, T772 is turned on, and FT732 is turned off.
When the switching element T731 is turned off, the potential at the point s rises, and the output + Q of 1 Shot 771 becomes the H level for a certain period.
When the switching element T731 is turned off, the return current I3 flows. Thereby, the parasitic diode of FT732 is forward-biased, and the source voltage of FT732 becomes larger than the drain voltage.
When the potential at point z rises, the output of ST772 becomes H level. As a result, the output of AND771 becomes H level and T776 is turned on. When T776 is turned on, the current I8 flowing through T775 is cut off, and the current flowing through the resistor R771 becomes zero. Thereby, T771 is turned on, T772 is turned off, and FT732 is turned on.
When the reflux current I3 decreases to zero, the potential at the z point decreases. As a result, the output of ST772 becomes L level, T776 is turned off, and FT732 is turned off.
Since there is a delay time until the potential at the z point decreases and the FT 732 is turned off, the potential at the z point is preferably lowered before the source-drain voltage of the FT 732 becomes zero. For this purpose, the resistance value of the resistor R761 needs to be set slightly larger than the resistance value of the resistor R763.
 直流電源V770の電圧は、6V程度に設定する。この場合、直流電源V770にゲートが接続されるT773のソース電圧は6V以上にはならないので、T774のブレークダウン電圧は10V程度でよいことになる。
 還流ダイオードとして用いられるFETを制御する回路に使われるFETのうち、ドレイン・ソース間電圧が大きくなる可能性のあるT761およびT762は、抵抗R762およびツェナーダイオードZD761で保護することができ、T774は、T773で保護することができる。このため、大きなブレークダウン電圧を必要とするFETは、FT732とT773のみとなる。
The voltage of the DC power supply V770 is set to about 6V. In this case, since the source voltage of T773 whose gate is connected to the DC power supply V770 does not exceed 6V, the breakdown voltage of T774 may be about 10V.
Among the FETs used in the circuit for controlling the FET used as the free-wheeling diode, T761 and T762 that may increase the drain-source voltage can be protected by the resistor R762 and the Zener diode ZD761. It can be protected with T773. For this reason, the only FETs that require a large breakdown voltage are FT732 and T773.
 第7の実施形態700は、各回路がGND基準で構成される。かつ、使用するFETのブレークダウン電圧は、FT732およびT773を除いて、交流電圧より低い電圧とすることができる。これにより、スイッチング素子T731をオン、オフ制御する回路と同じICチップ内に、これらの回路(但し、FT732およびT773を除く)を組み込むことが可能になる。 In the seventh embodiment 700, each circuit is configured based on GND. And the breakdown voltage of FET used can be made into a voltage lower than an alternating voltage except FT732 and T773. As a result, these circuits (except for FT732 and T773) can be incorporated in the same IC chip as the circuit for controlling on / off of the switching element T731.
 本発明は、詳細な説明に記載した構成に限定されず、本発明の要旨を逸脱しない範囲内で、種々の変更、追加、削除が可能である。
 発光ダイオードを有する負荷に直流電力を供給する場合について説明したが、本発明の電源装置は、発光ダイオード以外の種々の負荷に直流電力を供給することができる。
 I1の波形を修正して力率を「1」に近づけるための、図1に示されている閾値補正回路あるいは図3に示されている閾値発生回路を用いるのが好ましいが、このような閾値補正回路や閾値発生回路は省略することもできる。この場合でも、力率を改善することができるとともに、効率を向上させることができる。
 実施形態で説明した各構成は、単独で用いることもできるし、適宜選択した複数を組み合わせて用いることもできる。
 各回路を構成する素子の値(例えば、インダクタンス、容量、抵抗値)は、負荷の種類等に応じて適宜設定することができる。
 負荷に電力を供給するスイッチング素子としては、好適にはFETが用いられるが、FET以外の素子を用いることもできる。
The present invention is not limited to the configuration described in the detailed description, and various modifications, additions, and deletions can be made without departing from the gist of the present invention.
Although the case where DC power is supplied to a load having a light emitting diode has been described, the power supply apparatus of the present invention can supply DC power to various loads other than the light emitting diode.
It is preferable to use the threshold value correction circuit shown in FIG. 1 or the threshold value generation circuit shown in FIG. 3 to correct the waveform of I1 and bring the power factor close to “1”. The correction circuit and the threshold generation circuit can be omitted. Even in this case, the power factor can be improved and the efficiency can be improved.
Each structure demonstrated by embodiment can also be used independently, and can also be used combining the plurality selected suitably.
The values (for example, inductance, capacitance, resistance value) of elements constituting each circuit can be appropriately set according to the type of load.
As the switching element for supplying power to the load, an FET is preferably used, but an element other than the FET can also be used.
10…交流電源、100,200,300,400,500,600,700,800…電源装置、110,210,310,410,810…全波整流回路、120,220,320,420,520,620,720,820…負荷、121,221,321,421,521,621,721,821…発光ダイオード(LED)、130,230,330,430,830…電力供給回路、140,240,340,440,840…制御回路、141,241…クロック信号発生回路、142,242,442,560,660,760…駆動回路、150…閾値補正回路、180,280,380,480,580,680…電源回路、190,290,390,490…駆動信号出力回路、560,660,760…電圧検出回路、900…ローパスフィルタ。 DESCRIPTION OF SYMBOLS 10 ... AC power source, 100, 200, 300, 400, 500, 600, 700, 800 ... Power supply device, 110, 210, 310, 410, 810 ... Full wave rectifier circuit, 120, 220, 320, 420, 520, 620 , 720, 820... Load, 121, 221, 321, 421, 521, 621, 721, 821... Light emitting diode (LED), 130, 230, 330, 430, 830. , 840 ... control circuit, 141, 241 ... clock signal generation circuit, 142, 242, 442, 560, 660, 760 ... drive circuit, 150 ... threshold correction circuit, 180, 280, 380, 480, 580, 680 ... power supply circuit , 190, 290, 390, 490 ... drive signal output circuit, 560, 660, 760 ... voltage detection Road, 900 ... low-pass filter.

Claims (8)

  1.  交流電圧を整流した直流電圧を正極端と負極端の間に発生する整流回路と、前記整流回路と負荷の間に設けられる電力供給回路と、前記電力供給回路を制御する制御回路を備える電源装置であって、
     前記整流回路の前記正極端と前記負極端の間には、第2のインダクタと第2のコンデンサが直列に配置され、
     前記第2のコンデンサの端子間には、第1のインダクタ、第1のコンデンサと前記負荷との並列回路およびスイッチング素子が直列に配置され、
     前記第1のインダクタおよび前記第1のコンデンサと前記負荷との並列回路との直列回路には、ダイオードが並列に配置され、
     前記第2のインダクタのインダクタンスは、前記第1のインダクタのインダクタンスより大きな値に設定され、
     前記制御回路は、設定周期で前記スイッチング素子をオンし、前記スイッチング素子を流れる電流が前記直流電圧の大きさに連動する閾値より大きくなると前記スイッチング素子オフするように構成されており、
     前記スイッチング素子がオフのとき、前記第2のコンデンサが充電され、前記スイッチング素子がオンすると、前記第2のコンデンサが、前記第1のインダクタ、前記第1のコンデンサと前記直流負荷との並列回路および前記スイッチング素子からなる経路で放電し、また、前記スイッチング素子がオフすると、前記スイッチング素子のオン時に前記第1のインダクタに蓄積された電磁エネルギーが、前記第1のコンデンサと前記直流負荷との並列回路および前記ダイオードからなる経路を流れる還流電流に変換されるように構成されていることを特徴とする電源装置。
    A power supply apparatus comprising: a rectifier circuit that generates a DC voltage obtained by rectifying an AC voltage between a positive electrode end and a negative electrode end; a power supply circuit provided between the rectifier circuit and a load; and a control circuit that controls the power supply circuit Because
    Between the positive electrode end and the negative electrode end of the rectifier circuit, a second inductor and a second capacitor are arranged in series,
    Between the terminals of the second capacitor, a first inductor, a parallel circuit of the first capacitor and the load, and a switching element are arranged in series,
    A diode is arranged in parallel in a series circuit of the first inductor and the parallel circuit of the first capacitor and the load,
    The inductance of the second inductor is set to a value larger than the inductance of the first inductor,
    The control circuit is configured to turn on the switching element at a set cycle, and to turn off the switching element when a current flowing through the switching element becomes larger than a threshold linked to the magnitude of the DC voltage,
    When the switching element is off, the second capacitor is charged. When the switching element is on, the second capacitor is a parallel circuit of the first inductor, the first capacitor, and the DC load. When the switching element is discharged and when the switching element is turned off, electromagnetic energy accumulated in the first inductor when the switching element is turned on is generated between the first capacitor and the DC load. A power supply device configured to be converted into a return current flowing through a path including a parallel circuit and the diode.
  2.  交流電圧を整流した直流電圧を正極端と負極端の間に発生する整流回路と、前記整流回路と負荷の間に設けられる電力供給回路と、前記電力供給回路を制御する制御回路を備える電源装置であって、
     前記整流回路の前記正極端と前記負極端の間には、第2のインダクタ、第1のインダクタおよび第2のコンデンサが直列に配置され、
     前記第1のインダクタと前記第2のコンデンサとの直列回路には、第1のコンデンサと前記負荷との並列回路およびスイッチング素子が直列に配置され、
     前記第1のインダクタおよび前記第1のコンデンサと前記負荷との並列回路との直列回路には、ダイオードが並列に配置され、
     前記第2のインダクタのインダクタンスは、前記第1のインダクタのインダクタンスより大きな値に設定され、
     前記制御回路は、設定周期で前記スイッチング素子をオンし、前記スイッチング素子を流れる電流が前記直流電圧の大きさに連動する閾値より大きくなると前記スイッチング素子をオフするように構成されており、
     前記スイッチング素子がオフのとき、前記第2のコンデンサが充電され、前記スイッチング素子がオンすると、前記第2のコンデンサが、前記第1のインダクタ、前記第1のコンデンサと前記直流負荷との並列回路および前記スイッチング素子からなる経路で放電し、また、前記スイッチング素子がオフすると、前記スイッチング素子のオン時に前記第1のインダクタに蓄積された電磁エネルギーが、前記第1のコンデンサと前記直流負荷との並列回路および前記ダイオードからなる経路を流れる還流電流に変換されるように構成されていることを特徴とする電源装置。
    A power supply apparatus comprising: a rectifier circuit that generates a DC voltage obtained by rectifying an AC voltage between a positive electrode end and a negative electrode end; a power supply circuit provided between the rectifier circuit and a load; and a control circuit that controls the power supply circuit Because
    Between the positive terminal and the negative terminal of the rectifier circuit, a second inductor, a first inductor, and a second capacitor are arranged in series,
    In the series circuit of the first inductor and the second capacitor, a parallel circuit of the first capacitor and the load and a switching element are arranged in series,
    A diode is arranged in parallel in a series circuit of the first inductor and the parallel circuit of the first capacitor and the load,
    The inductance of the second inductor is set to a value larger than the inductance of the first inductor,
    The control circuit is configured to turn on the switching element at a set cycle, and to turn off the switching element when a current flowing through the switching element becomes larger than a threshold linked to the magnitude of the DC voltage,
    When the switching element is off, the second capacitor is charged. When the switching element is on, the second capacitor is a parallel circuit of the first inductor, the first capacitor, and the DC load. When the switching element is discharged and when the switching element is turned off, electromagnetic energy accumulated in the first inductor when the switching element is turned on is generated between the first capacitor and the DC load. A power supply device configured to be converted into a return current flowing through a path including a parallel circuit and the diode.
  3.  請求項1に記載の電源装置であって、
     前記制御装置は、クロック周期毎に処理を実行し、前記直流電圧が増加過程にあるときには、前記閾値から、前記クロック周期間における前記直流電圧の増加分による前記第2のコンデンサの充電電荷量に対応する値を減算した値を前記閾値とし、前記直流電圧が減少過程にあるときには、前記閾値に、前記クロック周期間における前記直流電圧の減少分による前記第2のコンデンサの放電電荷量に対応する値を加算した値を前記閾値とするように構成されていることを特徴とする電源装置。
    The power supply device according to claim 1,
    The control device executes processing for each clock cycle, and when the DC voltage is in an increasing process, the control device changes the charge amount of the second capacitor according to the increase in the DC voltage during the clock cycle from the threshold value. A value obtained by subtracting a corresponding value is set as the threshold value, and when the DC voltage is in a decreasing process, the threshold value corresponds to the discharge charge amount of the second capacitor due to the decrease in the DC voltage during the clock period. A power supply device configured to use a value obtained by adding values as the threshold value.
  4.  請求項1または3に記載の電源装置であって、
     前記閾値は、前記直流電圧の大きさから設定値を減算した値に連動するように構成され、
     前記制御装置は、前記直流電圧の大きさが前記設定値より小さい場合には前記スイッチング素子をオフするように構成されていることを特徴とする電源装置。
    The power supply device according to claim 1 or 3,
    The threshold is configured to be linked to a value obtained by subtracting a set value from the magnitude of the DC voltage,
    The control device is configured to turn off the switching element when the magnitude of the DC voltage is smaller than the set value.
  5.  請求項1~4のうちのいずれか一項に記載の電源装置であって、
     前記電力供給回路は、前記第2のコンデンサに直列に配置可能な第3のコンデンサを有していることを特徴とする電源装置。
    The power supply device according to any one of claims 1 to 4,
    The power supply circuit includes a third capacitor that can be arranged in series with the second capacitor.
  6.  請求項1~5のうちのいずれか一項に記載の電源装置であって、
     前記ダイオードとしてMOSFETの寄生ダイオードが用いられ、
     前記制御回路は、前記スイッチング素子がオフしてから設定期間内で、かつ、前記寄生ダイオードのカソード電圧が、アノード電圧から第1の設定値を減算した値より小さくなると前記MOSFETをオンし、前記設定期間経過後で、かつ、前記寄生ダイオードのカソード電圧が、アノード電圧から前記第1の設定値を減算した値より大きくなると前記MOSFETをオフするように構成されていることを特徴とする電源装置。
    The power supply device according to any one of claims 1 to 5,
    As the diode, a parasitic diode of MOSFET is used,
    The control circuit turns on the MOSFET when the cathode voltage of the parasitic diode becomes smaller than a value obtained by subtracting the first set value from the anode voltage within a set period after the switching element is turned off. The power supply device is configured to turn off the MOSFET when a cathode voltage of the parasitic diode becomes larger than a value obtained by subtracting the first set value from an anode voltage after a set period has elapsed. .
  7.  請求項6に記載の電源装置であって、
     前記寄生ダイオードのアノードとカソード間の電圧を検出する電圧検出回路を備え、
     前記電圧検出回路は、FETにより構成される第1のソースフォロア回路および第2のソースフォロア回路を有し、前記第1のソースフォロア回路のソース抵抗は、前記寄生ダイオードのアノードに接続され、前記第2のソースフォロア回路のソース抵抗は、前記寄生ダイオードのカソードに接続され、前記第1のソースフォロア回路のFETのゲートおよび第2のソースフォロア回路のFETのゲートに共通のバイアス電圧が印加され、前記寄生ダイオードのアノードとカソード間の電圧が、前記第1のソースフォロア回路を流れる電流と前記第2のソースフォロア回路を流れる電流の差に変換されるように構成されていることを特徴とする電源装置。
    The power supply device according to claim 6,
    A voltage detection circuit for detecting a voltage between the anode and cathode of the parasitic diode;
    The voltage detection circuit includes a first source follower circuit and a second source follower circuit configured by FETs, and a source resistance of the first source follower circuit is connected to an anode of the parasitic diode, The source resistance of the second source follower circuit is connected to the cathode of the parasitic diode, and a common bias voltage is applied to the gate of the FET of the first source follower circuit and the gate of the FET of the second source follower circuit. The voltage between the anode and the cathode of the parasitic diode is converted into a difference between a current flowing through the first source follower circuit and a current flowing through the second source follower circuit. Power supply.
  8.  請求項6に記載の電源装置であって、
     前記寄生ダイオードのアノードとカソード間の電圧を検出する電圧検出回路を備え、
     前記電圧検出回路は、第1の回路と第2の回路を有し、
      前記第1の回路は、前記寄生ダイオードのカソードに直列に接続されるダイオード、第1の抵抗、第1のPMOSFET、第2の抵抗および第1のNMOSFETにより構成され、前記第1のPMOSFETのゲートとドレインが短絡され、前記第1のNMOSFETのゲートとドレインが短絡され、かつ、ソースが接地され、
      前記第2の回路は、前記寄生ダイオードのアノードに直列に接続されるダイオード、第3の抵抗、第2のPMOSFET、第4の抵抗および第2のNMOSFETにより構成され、
     前記第2のPMOSFETのゲートが前記第1のPMOSFETのゲートに接続され、前記第2のNMOSFETのソースが接地され、前記第1のNMOSFETのゲートに接続されており、
     前記第2のPMOSFETは、前記第1のPMOSFETと同じ特性を有し、前記第2のNMOSFETは、前記第1のNMOSFETと同じ特性を有しており、
     前記第4の抵抗の抵抗値は、前記第2の抵抗の抵抗値より小さくなるように設定され、前記第3の抵抗の抵抗値は、前記第1の抵抗の抵抗値に等しいかあるいは大きくなるように設定されており、
     前記第2のNMOFETのドレイン電圧が、前記寄生ダイオードのアノードとカソード間の電圧に応じて変化するように構成されていることを特徴とする電源装置。
    The power supply device according to claim 6,
    A voltage detection circuit for detecting a voltage between the anode and cathode of the parasitic diode;
    The voltage detection circuit includes a first circuit and a second circuit,
    The first circuit includes a diode connected in series to the cathode of the parasitic diode, a first resistor, a first PMOSFET, a second resistor, and a first NMOSFET, and the gate of the first PMOSFET. And the drain are short-circuited, the gate and drain of the first NMOSFET are short-circuited, and the source is grounded,
    The second circuit includes a diode connected in series to the anode of the parasitic diode, a third resistor, a second PMOSFET, a fourth resistor, and a second NMOSFET,
    The gate of the second PMOSFET is connected to the gate of the first PMOSFET, the source of the second NMOSFET is grounded, and is connected to the gate of the first NMOSFET;
    The second PMOSFET has the same characteristics as the first PMOSFET, the second NMOSFET has the same characteristics as the first NMOSFET,
    The resistance value of the fourth resistor is set to be smaller than the resistance value of the second resistor, and the resistance value of the third resistor is equal to or greater than the resistance value of the first resistor. Is set to
    The power supply apparatus, wherein the drain voltage of the second NMOFET is configured to change according to a voltage between an anode and a cathode of the parasitic diode.
PCT/JP2015/063683 2015-05-12 2015-05-12 Power supply device WO2016181513A1 (en)

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JP2011091942A (en) * 2009-10-22 2011-05-06 Phoenix Electric Co Ltd Power supply circuit
JP2012169183A (en) * 2011-02-15 2012-09-06 Yoshikawa Rf System Kk Dimming-type lighting circuit
JP2013026079A (en) * 2011-07-22 2013-02-04 Kaga Electronics Co Ltd Led lighting device
WO2013128509A1 (en) * 2012-03-02 2013-09-06 パナソニック株式会社 Dc power supply circuit
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Patent Citations (6)

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Publication number Priority date Publication date Assignee Title
US7759881B1 (en) * 2008-03-31 2010-07-20 Cirrus Logic, Inc. LED lighting system with a multiple mode current control dimming strategy
JP2011091942A (en) * 2009-10-22 2011-05-06 Phoenix Electric Co Ltd Power supply circuit
JP2012169183A (en) * 2011-02-15 2012-09-06 Yoshikawa Rf System Kk Dimming-type lighting circuit
JP2013026079A (en) * 2011-07-22 2013-02-04 Kaga Electronics Co Ltd Led lighting device
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