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Publication numberWO2015114667 A3
Publication typeApplication
Application numberPCT/IN2015/000058
Publication date5 Nov 2015
Filing date29 Jan 2015
Priority date29 Jan 2014
Also published asWO2015114667A2
Publication numberPCT/2015/58, PCT/IN/15/000058, PCT/IN/15/00058, PCT/IN/2015/000058, PCT/IN/2015/00058, PCT/IN15/000058, PCT/IN15/00058, PCT/IN15000058, PCT/IN1500058, PCT/IN2015/000058, PCT/IN2015/00058, PCT/IN2015000058, PCT/IN201500058, WO 2015/114667 A3, WO 2015114667 A3, WO 2015114667A3, WO-A3-2015114667, WO2015/114667A3, WO2015114667 A3, WO2015114667A3
InventorsG. Sujan KUMAR, S Aniruddhan
ApplicantIndian Institute Of Technology Madras
Export CitationBiBTeX, EndNote, RefMan
External Links: Patentscope, Espacenet
Signal acquisition using a multi-frequency chopping in a single circuitry
WO 2015114667 A3
The present invention discloses a method and system for processing a plurality of signals together in a single circuitry using a multi-frequency chopping. The system is configured to include a first level chopping, an amplifier for amplification, a second level chopping, a filter for filtration and an Analog to Digital Converter (ADC). The system is further configured to receive low frequency input signals and apply the first level of chopping by translating signals to a higher frequency. Further, the system is configured to amplify the signals and apply the second level of chopping to translate the signal back to original frequency. During second level of chopping, signals are translated to new frequencies other than their baseband by chopping each signal at a different frequency. Further, the signals are combined into a single signal and send to an Analog-to-Digital Converter (ADC) for digitizing.
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Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US7170338 *24 Mar 200530 Jan 2007Cirrus Logic, Inc.Chopper stabilization circuits and methods
US8471744 *1 Dec 201125 Jun 2013Hong Kong Applied Science & Technology Research Institute Company, Ltd.Reduced residual offset sigma delta analog-to-digital converter (ADC) with chopper timing at end of integrating phase before trailing edge
International ClassificationH03M1/00, H04L27/26
Cooperative ClassificationH03F3/211, H03F3/387, A61B5/7225, A61B5/04004
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