WO2015109357A1

WO2015109357A1 - Phase cutting controlled dimmer arrangement with over-current protection when powering a lamp

Info

Publication number: WO2015109357A1
Application number: PCT/AU2015/000020
Authority: WO
Inventors: Philip Tracy
Original assignee: Hendon Semiconductors Pty Ltd
Priority date: 2014-01-24
Filing date: 2015-01-19
Publication date: 2015-07-30

Abstract

A phase cutting controlled dimmer arrangement with over-current protection including load control for back-to-back FETs or IGBTs with connected gates. There is a current sensing resistor that provides a first and second voltage. A first transistor has an electrical pathway to the second voltage and a second transistor has an electrical pathway to the first voltage such that when the second or first voltages exceeds a threshold voltage, this is commensurate with an over- current event of the back-to-back FETs or IGBTs, triggering the first or second transistor into conduction wherein conduction of the first or second transistors provides a means to turn OFF the back-to-back FETs or IGBTs thereby withdrawing power to the load.

Description

PHASE CUTTING CONTROLLED DIMMER ARRANGEMENT WITH OVER- CURRENT PROTECTION WHEN POWERING A LAMP

FIELD OF THE INVENTION

[001] This invention relates to a phase cutting control dimmer arrangement that includes short circuit protection elements and more particularly short circuit protection elements that require minimal specified holding current when in use, are designable and interface-able into the arrangement without introducing any significant complexity and/or multiple signal connections to a microcontroller and so forth, to provide a fast acting means to turn OFF and protect the solid state switching devices for the Dimmer if the provided switch load becomes short circuited and/or severely exceeds safe operating conditions of circuitry components.

BACKGROUND ART DISCUSSION

[002] Phase cutting control dimmer arrangements operate by switching AC mains supplies to a lamp or light load for only a chosen time portion of each AC mains supply half cycle. For two-wire trailing edge dimmers, also referred to as reverse phase control dimmers, these remove power from the end or trailing edge of each AC mains supply half cycle. The time period for the AC mains supply as applied to the load is determined conventionally by an analogue or digital timer, controlling the load switching device, that must be started and stopped at exact times during each AC mains supply half cycle.

[003] For two-wire trailing edge dimmers the two terminals are wired in series with the load and the time at which the timer is started and stopped, once again for the most part is derived from the processing of the voltage that appears across each of the active and load dimmer voltage terminals.

[004] Solid state switching devices, such as Field Effect Transistors (FETs) or Insulated Gate Bipolar Transistors (IGBTs), in these kinds of Dimmer

arrangements if the provided switch load becomes short circuited and/or severely exceeds safe operating conditions can be irrevocably damaged when an over current event occurs.

[005] As a consequence in order to avoid any overloading of the dimmer arrangement short circuit protection elements need to be configured into the control arrangement in order to provide short circuit protection as well as other over-current protection as a consequence of the usual switch load severely exceeding safe operating conditions for the solid state switching devices than otherwise have been expected.

[006] As stated in Australian Patent AU2007229437, circuitry can be introduced into the phase cutting control dimmer arrangement in an attempt to shield the switch from load circuit faults. Examples include a current sensing resistor in series with the regulating transistor wherein as the current increases, the voltage drop across the resistor causes the operation of the regulating transistor to limit the conduction of a pass transistor in series with the load. There are also more sophisticated designs, such as the use of a silicon controlled rectifier as part of a protection module to shield the load from circuit faults.

[007] Nonetheless up until now these kinds of protection modules that include the requisite short circuit protection elements to be incorporated into the phase cutting control dimmer arrangement as referenced above in many instances contribute significantly to circuit complexity, require multiple interfacing and signal generation when used in combination with a micro-controller to assist in operation, and notably the current drawn from the short circuit protection elements in order to guarantee a holding current for correct operation of the protection module itself, is such that the current cannot be made available within modern dimmer arrangements which are required to operate low wattage lights such as LEDs and so forth without great increase in the complexity of the phase cutting control dimmer arrangement's power supply. [008] Accordingly it is an object of this invention to provide a phase cutting controlled dimmer arrangement having short circuit protection elements that can provide for over-current protection having a fast acting means to turn OFF and protect the solid state switching devices when a switch load becomes short circuited or severely exceeds appropriate operating conditions with minimum specified values for the current for maintaining operation of the short circuit protection elements thereby not adding any significant complexity of the phase cutting control dimmer arrangement's power supply and at the same time simplified interfacing between the micro-controller and the switching

arrangement of the dimmer to just the one single connection thereby reducing the size, cost and requisite spacing required to accommodate the short circuit protection elements withinside the phase cutting control dimmer arrangement.

[009] Further objects and advantages of the invention will become apparent from a complete reading of the following specification.

SUMMARY OF THE INVENTION

[010] In one form of the invention there is provided a phase cutting controlled dimmer arrangement with over-current protection, said arrangement adapted to control the level of power switchable to a load, said arrangement including;

[01 1] a load control arrangement including back-to-back Field Effect

Transistors (FETs) or Insulated Gate Bipolar Transistors (IGBTs) with connected gates;

[012] a current sensing resistor in electrical communication with said back-to- back FETs or IGBTs, said current sensing resistor adapted to provide a first voltage at a first end across said current sensing resistor or a second voltage at second end across said current sensing resistor;

[013] a first transistor including an electrical pathway to the second end of said current sensing resistor so as to be in electrical communication with the provided second voltage across said current sensing resistor, such that when the second voltage exceeds a threshold voltage, said threshold voltage commensurate with an over-current event experienced by the FETs or IGBTs, said first transistor is triggered into conduction wherein said first transistor conduction provides a first means for said FETs or IGBTs to be turned OFF thereby withdrawing power to the load; and

[014] a second transistor having an electrical path connected to the first end of said current sensing resistor, said electrical path providing means for electrical communication with the first voltage across said current sensing resistor, such that when the second voltage across the current sensing resistor exceeds a threshold voltage, said threshold voltage commensurate with an over-current event experienced by the FETs or IGBTs, said second transistor is triggered into conduction, wherein said conduction provides a second means for the FETs or IGBTs to be turned OFF thereby withdrawing power to the load.

[015] In preference the first transistor and the second transistor are Bipolar Junction Transistors (BJT).

[016] In preference the first transistor and the second transistor are NPN Bipolar Junction Transistors.

[017] In preference load control arrangement for turning OFF and ON electrical power to the load includes a control switch with back-to-back Field Effect Transistors (FETs).

[018] In preference the current sensing resistor includes an electrical path at the first end connected to the source of one FET and at the second end of said current sensing resistor an electrical path connected to the source of the other FET.

[019] In preference the first transistor includes an electrical path from the emitter to the second voltage across the current sensing resistor and an electrical path from the base to the first voltage across the current sensing resistor.

[020] In preference the second transistor includes an electrical path from the emitter to the first voltage across the current sensing resistor and an electrical path from the base to the second voltage across the current sensing resistor.

[021] In preference the first transistor's first means, and the second transistor's second means to turn OFF the FETs includes a third transistor having an electrical path into the interconnected gates of the FETs when either the first transistor or the second transistor are triggered into conduction when an over- current event is experienced.

[022] In preference the third transistor is a BJT.

[023] In preference the collector of the third transistor includes an electrical path into the connected gates of the back-to-back FETs.

[024] In preference the third transistor is adapted to sink a current significantly larger than the FETs gate drive current available via a gate drive resistor such that the third transistor is adapted to discharge gate source capacitance of each FETs so as to quickly turn OFF said FETs before damaging of FETs due to the over-current event experienced.

[025] In preference the current sensing resistor is adjusted to provide a voltage drop of approximately 0.6 V measureable at the first voltage or the second voltage when current flowing through the current sensing resistor has a value commensurate with threshold voltage to trigger conduction for the first transistor or the second transistor when a short-circuit and/or severely exceeded AC supply current being switched by the FETs is experienced.

[026] In preference the first transistor and the second transistor each include an electrical path to a separate series resistor. [027] In preference each resistor connected in series is connected to the base of each of the first transistor and the second transistor.

[028] In preference each resistor connected in series with the base of each of the first transistor and the second transistor has as a large value so as to minimise the value of base current that can flow into the base of the first transistor and the second transistor when an over-current event is experienced.

[029] In preference each of the first transistor and the second transistor includes a collector resistor connect at one end via a path including the base- emitter of a fourth transistor to the positive DC power supply arrangement of the phase cutting control dimmer arrangement wherein said collector resistors are valued and adapted to minimise current to prevent the power supply

arrangement being overloaded.

[030] In preference the fourth transistor in electrical communication with a threshold voltage recognition resistor said threshold voltage recognition resistor along the electrical path between each of the collector resistors of the first transistor and second transistor and positive DC power supply arrangement respectively such that when current flows in the threshold voltage recognition resistor that exceeds the set threshold voltage this turns ON the fourth transistor.

[031] In preference the fourth transistor is a PNP BJT.

[032] In preference the threshold voltage recognition resistor has an electrical path into the base of the fourth transistor PNP BJT such that when the current flowing in the threshold voltage recognition resistor exceeds the threshold voltage, preferably of 0.6 V, this then results in turning ON the fourth transistor PNP BJT and wherein the collector voltage will rise to closely equal the positive voltage of the power supply, preferably 10V. [033] In preference the collector of the fourth transistor PNP BJT is connected to zero volt reference along a first electrical path through series resistor pair and a second electrical path through a current limiting resistor feeding into the base of the third transistor.

[034] In preference the series resistors pair connected to the collector of the fourth transistor PNP BJT are separated by a single electrical path into a microcontroller.

[035] In preference when the fourth transistor PNP BJT turns ON the collector voltage rises closely equal to the power supply enabling current to flow along the first electrical path through the series resistors pair and along the second electrical path through the resistor into the base of the third transistor thereby turning ON the second transistor and the third transistor.

[036] In preference wherein the second transistor, if not already turned ON by the voltage across the current sensing resistor, will be turned ON by the voltage developed across the current limiting resistor in series between the base of the second transistor and the zero volt reference as caused by the current flowing through the series resistor pair.

[037] In preference the third transistor will be turned ON by the voltage developed across a resistor between the base of the third transistor and its emitter or zero volt reference as caused by the current flowing along the second electrical path from the collector of the fourth transistor PNP BJT through the current limiting resistor to the base of the third transistor.

[038] In preference there is a capacitor across the threshold voltage

recognition resistor adapted to provide a filter to slow the response time of the arrangement so as to enable a fast enough response time to protect the FETs but not inadvertently too quick that it may falsely instigate the over-current protection by a momentary fast transient voltage that may have occurred on the AC mains supply. [039] In preference when the arrangement is not activated the voltage at the microcontroller interface at the junction between the series resistors pair connected to the collector of the fourth transistor will be zero volt.

[040] In preference when triggered into conduction the voltage at the base of the second transistor would be approximately 0.6 V and the voltage at the collector of the fourth transistor will be at 10 V.

[041] In preference the resistor divider series resistors are selected to provide a voltage at the microcontroller interface that is set close to the microcontroller's supply voltage but not exceeding the maximum allowed voltage.

[042] In preference the maximum allowed voltage established by the resistor divider series resistors is limited to +0.3 V above the microcontroller's supply voltage.

[043] In preference the microcontroller is programmed with a high impedance input configuration for the interface pin allowing the microcontroller to read at any time the status of the over-current protection without causing any change to it, adapted to re-set the over-current protection to an inactive state and be able to set the over-current protection to a protective state.

[044] In preference the ability of the single interface connection of the microcontroller allows a separate control path, that acts directly on the FET gates, whereby the microcontroller is adapted to turn OFF the FETs in response to other overload stimulus such as an over-temperature signal that is generated within the microcontroller, without requiring any external temperature sensing components or additional interface connections.

[045] Advantageously the arrangement in this invention is able to provide over- current protection that requires minimal holding current for the short-circuit protection elements, which in some embodiments can be less than 0.5 mA, while at the same time still maintaining a simplified interfacing with the remainder of the phase cutting control dimmer arrangement as there is only one single connection required with the microcontroller.

[046] Advantageously, unlike prior art arrangements, this invention allows interfacing with the microcontroller having just one microcontroller port. Modern conventional timer switches, dimmers and the like are required to fit into very small spaces and are built with extremely small componentry. Advantageously by being able to utilise a microcontroller with just the requirement of a single port pin means that there can be a significant reduction in size and associated costs.

[047] While there is only a single interface connection, advantageously the interfacing with the microcontroller through the single port pin however still is able, because of the circuit design configuration, to read at any time the status of the over-current protection connected with the short-circuit protection elements without causing any change to the actual circuit conditions per se.

[048] Essentially the microcontroller with the single connection, is still able to identify whether the short-circuit protection elements have been activated or not and be inherently adapted to be able to re-set the over-current protection module to the inactive state and to be able to set the over-current protection short-circuit protection elements to the tripped or protective state as required.

[049] Advantageously the ability to set the over-current protection module within the arrangement to the trip state allows the micro-controller a separate control path, that acts directly on the connected FET gates, whereby this separate control path is adapted to turn OFF the FETs in response to other overload stimulus such as over-temperature signal that is generated totally within the micro-controller, without requiring any external temperature sensing components or any additional interface connections.

[050] In preference the micro-controller includes an inbuilt temperature sensor. [051] In preference the micro-controller inbuilt temperature sensor is

programmable and/or adaptable to provide aggregate temperature data for the micro-controller which in turn provides temperature information for the microcontroller's surrounding environment that can be utilised in a total safety control system to protect the phase cutting controlled dimmer arrangement.

[052] Advantageously this arrangement allows the ability to switch OFF the FETs even if a fault in the drive signal is acting to turn the FETs ON.

[053] In order now to describe the invention in greater detail, a preferred embodiment will be presented with the assistance of the following figure and accompanying text.

[054] BRIEF DESCRIPTION OF THE DRAWING

[055] Figure 1 illustrates an electrical circuit of a two-wire trailing edge dimmer arrangement of a preferred embodiment of this invention including short-circuit protection elements for over-current protection when the dimmer arrangement is providing power and controlling the illumination levels of a lamp load.

[056] DETAILED DESCRIPTION OF THE INVENTION

[057] Referring to the drawing now in greater detail wherein Figure 1 provides a circuit arrangement for a two-wire trailing edge dimmer arrangement shown generally as (10) adapted to remove power from the end or trailing edge of each AC mains supply cycle. The dimmer terminals include ACTIVE (12) and LOAD (14).

[058] The dimmer terminal voltage is effectively bridged by rectifier diodes (16) and (18) and the parasitic diodes (24) and (26) which are contained in the corresponding Field Effect Transistors (FETs) (20) and (22) that comprise the load current switch. As illustrated, FETs (20) and (22) are arranged back-to- back and operate in the N-Channel enhancement mode having source terminals (21 ) and (23) connected together via resistor (33) with the gates (25) and (27) of each of the FETs (20) and (22) also connected with the drain terminals (29) and (31 ) acting as two power terminals.

[059] The FETs (20) and (22), each have corresponding intrinsic body diodes as introduced above (24) and (26) that allow conduction of current in one direction as configured back-to-back arrangements of the FETs (20) and (22) allows load current to be controlled in either direction.

[060] A first transistor (28) which is a NPN BJT transistor and a second transistor (30) which is a NPN BJT transistor, both provide sensing of a first voltage (32) and a second voltage (34) on either side of a current sensing resistor (33). The single sensing resistor (33) is adapted by interchanging the base and emitter connections to the single sensing resistor (33) so it can respond to either polarity of voltages (32) and (34) developed across the single sensing resistor (33). In the arrangement shown in Figure 1 the first transistor (28) is connected to the second voltage (34) on one side of the sensing resistor (33) wherein the second transistor is connected to the first voltage on the other side of the sensing resistor (33).

[061] The first transistor (28) and second transistor (30) provide the sensing of the voltage that will be developed across the sensing resistor (33) due to the AC mains current flowing in the main switching elements of the back-to-back FETs (20) and (22).

[062] In the preferred embodiment the single sensing resistor (33) is adjustable to provide a voltage drop of approximately 0.6 V when the current that is flowing in the sensing resistor (33) has a peak value at which the short-circuit protection elements within the arrangement (10) become operable.

[063] A typical value may be 20A peak and accordingly therefore provide a value for the sensing resistor of around 30 milliohms. As the current that can flow in an AC mains circuit when short-circuit is applied may be very much larger, of the order of 100A, the voltage across the sensing resistor (33) can reach a voltage of around 3 V. If the 3 V is applied directly to the base (99) and emitter (38) of the first transistor (28) or the base (71 ) and emitter (73) of the second transistor (30), the first transistor (28) and second transistor (30) would be destroyed.

[064] Accordingly in order to protect the first transistor (28) which is sensing the voltage (32) that is developed across the sensing resistor (33) as well as protecting the second transistor which is also sensing the voltage (34) developed across the sensing resistor (33) protection resistors (40) and (42), having large values preferably of the order of 100 kilo ohms are inserted in series with the respective first transistor (28) and the second transistor (30) to limit, to a small value of the order of 25 micro amps (μΑ), the current that can flow into base of the first transistor (28) and the base of the second transistor (30).

[065] When either the first transistor (28) or the second transistor (30) is made conductive, by the voltage (32) in the case of the second transistor (30) and the voltage (34) in the case of the first transistor (28) across the single sensing resistor (33) exceeding 0.6 V, the current that either the first transistor (28) or the second transistor (30) sink is limited by the respective collector resistors (44) and (46) that minimise the total current used by the phase cutting control dimmer arrangement (10) and prevent the 10 V provided by the power supply arrangement (48) being overloaded.

[066] As the person skilled in the art will appreciate the voltage (32) is really just the same voltage as (34), i.e. the voltage developed across the sensing resistor (33). The sensed voltage has two possible polarities if it is always referenced to the common or 0 V reference node labelled (34). In one case (32) is positive with respect to (34) and in the other case (32) is negative with respect to (34). The polarity depends on which mains half cycle causes the overload, for example what polarity the mains has when the overload occurs. [067] Typically the collector resistors (44) and (46) limit the current to about 0.25 mA. When current from resistor (44) or (46) flows into resistor (50), having a value of the order of 10 kilo ohms, this will cause the voltage across resistor (50) to exceed 0.6 V and cause a fourth transistor (52) which is a PNP BJT to turn ON.

[068] When the fourth transistor (52) turns ON its collector voltage (54) will rise to closely equal the 10 V in this preferred embodiment made available by the power supply arrangement (48). As the collector voltage (54) of the fourth transistor (52) rises closely to equal the 10 V provided by the power supply arrangement (48) this causes currents to flow through the paired resistors (56) and (58) as well as resistor (60).

[069] As the current flows through the paired resistors (56) and (58) this turns ON the second transistor (30) and with current flowing through resistor (60) the third transistor (36) is also turned ON.

[070] In the event that the second transistor (30) is not already ON by the fact that the voltage across the sensing resistor (33) exceeding 0.6 V, the second transistor (30) will be turned ON by the voltage developed across the current limiting protection resistor (42) as caused by the current in the series paired resistors (56) and (58). The third transistor (36) will be turned ON by the voltage developed across the resistor (41 ) caused by the current flowing through resistor (60).

[071] Capacitor (62) across resistor (50) provides a filter to slow the response time of the over-current protection elements so the over-current protection elements can be thus fast enough to protect the FETs (20) and (22), but no so fast that the over-current protection elements are tripped by very fast transient voltages which may occur on the AC mains supply.

[072] The third transistor (36) provides the path that will turn OFF the FETs (20) and (22), in response to an over-current event. The third transistor (36) is adapted to be able to sink a current much larger than the FET's (20) and (22) gate drive current (64) as provided via gate drive resistor (67) as the third transistor (36) is adapted to discharge the gate source capacitance of the FETs (20) and (22), which may be of the order of a few nano farads, and to which the third transistor (36) must be inherently capable to be able to quickly turn the FETs (20) and (22) OFF before a large current, due to the over-current event, is present long enough to damage the FETs (20) and (22).

[073] In the preferred embodiment shown, the use of the two separate collector resistors (44) and (46) of the first transistor (28) and second transistor (30) ensures that the required latching remains possible and is not prevented from happening under certain overload conditions.

[074] For example if the collectors of the first transistor (28) and second transistor (30) were connected, and there was just a single resistor to replace the separate resistors (44) and (46), it must be recognised that voltage across the sensing resistor (33) caused by a short-circuit in an AC mains circuit could be of the order of 100 A and the voltage across the sensing resistor (33) could therefore reach several volts.

[075] In a scenario such as the upper end of the sensing resistor (33) voltage is +3 V relative to the reference line (61 ), that being 0 V in the embodiment shown in Figure 1 , that is connected to the emitter (38) of the first transistor (28), the first transistor (28) is providing, via the collector resistor (44), the current to turn ON the fourth transistor (52). The first transistor (28) will be driven to saturation and the first transistor (28) collector will therefore have a potential of the order of 50 mV above 0 V.

[076] In a situation wherein the first transistor (28) collector was connected to the second transistor (30) collector and only a single resistor implemented, for example in Figure 1 resistor (46) would be removed, the second transistor (30) collector will then also bear the potential close to 0 V and consequently due to the conduction of the second transistor's (30) base-collector junction the second transistor (30) base (71 ) cannot reach a voltage greater than approximately 0.65 V above the 0 V reference (61 ). The second transistor (30) emitter (73), connected to the top of the sensing resistor (33) has a potential of +3 V and consequently that means that the second transistor (30) is reverse bias, because its base (71 ) being 0 V is approximately 3 V below its emitter voltage, and the second transistor (30) therefore cannot turn ON. Consequently the intended latching action involving the fourth transistor (52) and the second transistor (30) is prevented from happening.

[077] In the preferred embodiment the values of the series connected resistors (56) and (58) are selected to limit the current that would be available to flow into the interface pin (66) of the microcontroller (68).

[078] Under normal operation, when the over-current protection elements are not activated, the voltage at the microcontroller interface, that being at the junction (69) between the two resistors (56) and (58) will be at 0 V. When activated the voltage at the second transistor (30) base will be approximately 0.6 V and the fourth transistor (52) collector will be as referred to above 10 V made available by the power supply arrangement (48).

[079] The resistive divider resistors (56) and (58) are chosen to provide a voltage at the microcontroller (68) interface that is set close to the

microcontroller's supply voltage but will not exceed the maximum allowed voltage. That maximum allowed voltage is usually limited to +0.3 V above the microcontroller's supply voltage.

[080] The microcontroller is programmable to provide a high impedance input configuration for the interface pin (66) into the microcontroller (68) and accordingly is able to read the state of the short-circuit protection elements within the phase cutting control arrangement at any time.

[081] By briefly driving the interface pin (66) of the microcontroller (68) to 0 V, and then returning the pin (66) of the microcontroller (68) to the high impedance state, the microcontroller (68) can remove the base drive (71 ) to the second transistor (30) so the second transistor (30) turns OFF so that the over-current protection module or those short-circuit protection elements that make up the over-protection module may be re-set to the inactive state.

[082] By briefly driving the interface pin (66) of the microcontroller (68) to the microcontroller supply voltage, which in the preferred embodiment shown will be 3.3V, and returning the interfacing pin (66) back to the high impedance state, the microcontroller (68) can turn ON the second transistor (30) and set the over- current protection elements to the active or protective state as required.

[083] As discussed precedingly, the microcontroller (68) could also include an internal temperature sensor which could provide accurate temperature data for the microcontroller (68). This temperature information can provide

corresponding information as to the temperature of the surrounding

environment that can be used in the total safety control system to protect the FETs (20) and (22) in relation to over-temperature protection as an additional feature.

[084] The voltage levels that are generated by the interface with the

microcontroller (68) are adapted to match the logic voltage levels applied to the microcontroller pin (66) that would be most advantageous to minimising the supply current consumed by the microcontroller (68). In the arrangement shown in Figure 1 this is achieved by arranging that the two voltage levels generated in the active and inactive states wherein the over-current protection is put into operation to turn OFF the FETs due to an over-current situation can be adapted, by utilising the values of resistors (58) and (56) so that the voltage levels closely equal the logic voltages used by the microcontroller (68).

Generally these two voltage levels would be 0 V and the microcontroller supply voltage.

[085] As the efficiency of lamps has increased in very recent times the power used by those lamps has decreased. Modern electronic lamps rated at just 5 W will produce significant lighting so modern switches and dimmers must be able to work with lamp loads having power ratings about 10 times lower than the earlier incandescent lamps.

[086] A 5 W lamp on a 230 V mains supply has a nominal operating current of less than 22 milliamps. If that lamp is to be dimmed to 10% of its full brightness then the lamp current being passed by its dimmer may need to be reduced to 2.2 milliamps.

[087] In order to switch a light "OFF", or make it very dim, the current passing through the dimmer or switch, used to power that dimmer or switch, needs to be as small as possible. Certainly much less than 2.2 mA. While it is possible to design a dimmer that requires very little current to be drawn through the lamp in order to power the dimmer, it can be difficult to achieve values below 1 milliamp.

[088] The simplest powering arrangement passes a controlled load current directly through a low voltage zener diode so the available dc supply current equals the average current flowing in the lamp load. Complex arrangements using high frequency transformer-based power supplies that can increase the low voltage power supply current to multiples of the lamp load current are well known but have many disadvantages including their cost, physical size and potential generation of radio interference.

[089] Therefore it is advantageous to just reduce the dimmer's supply current requirement to a value that can be provided by simpler arrangements.

Therefore the average current passing through the load, or required for normal operation of the dimmer or switch, will ideally be less than 1 mA.

[090] If the switch is to electronically include a true OFF' state then that current may be required to be 10 times smaller. Electronic switches require protection against the connection of short-circuits and the prior art methods of protection generally have required the provision of more than 1 mA just for this, relatively small, protection part of the total switching arrangement, one that may include a microcontroller that can require a significant fraction of that 1 mA for its operation.

[091] Advantageously the total current drawn from the low voltage power supply in this invention is greatly reduced because the minimum specified value for holding current of small SCRs, as used in the prior art, is about 5 mA. Good design practice requires the designer to ensure that much current can flow in the SCR to guarantee it remains conductive. That requires the dimmer's low voltage supply to be capable of at least that 5 mA and more to allow for the rest of its operation.

[092] That much current cannot be made available in a modern dimmer without great increase in the complexity of its power supply. By contrast, when it is latched and protecting, in the arrangement in Figure 1 there is a total current drain less than 0.5 mA, a value that is still practical to simply provide in a modern dimmer. The current used in this arrangement, equivalent to the holding current of the SCR circuits, is about 0.25 mA. That's 1/20 of the holding current required by the SCR in the prior art arrangements.

[093] Because that current can be adjusted, by adjusting the resistor values in Figure 1 , and because the current used could be considerably further reduced, for example by substituting a FET for the third transistor (36), the value 0.5 mA is by no means any lower limit. It is just a compromise value resulting from the selection of very low cost and ultra-miniature components in a preferred embodiment of the invention.

Claims

CLAIMS:

1. A phase cutting controlled dimmer arrangement with over-current protection, said arrangement including; a load control arrangement including back-to-back Field Effect Transistors (FETs) or Insulated Gate Bipolar Transistors (IGBTs) with connected gates; a current sensing resistor in electrical communication with said back-to-back FETs or IGBTs, said current sensing resistor adapted to provide a first voltage at a first end across said current sensing resistor or a second voltage at second end across said current sensing resistor; a first transistor including an electrical pathway to the second end of said current sensing resistor so as to be in electrical communication with the provided second voltage across said current sensing resistor, such that when the second voltage exceeds a threshold voltage, said threshold voltage commensurate with an over-current event of the FETs or IGBTs, said first transistor is triggered into conduction wherein said first transistor conduction provides a first means for said FETs or IGBTs to be turned OFF thereby withdrawing power to the load; and a second transistor having an electrical path connected to the first end of said current sensing resistor, said electrical path providing means for electrical communication with the first voltage across said current sensing resistor, such that when the second voltage across the current sensing resistor exceeds a threshold voltage, said threshold voltage commensurate with an over-current event of the FETs or IGBTs, said second transistor is triggered into conduction, wherein said second transistor conduction provides a second means for the FETs or IGBTs to be turned OFF thereby withdrawing power to the load.

2. The arrangement of claim 1 wherein the first transistor and the second transistor are NPN Bipolar Junction Transistors (NPN BJT) and the load control arrangement for turning OFF and ON electrical power to the load includes a control switch with back-to-back Field Effect Transistors (FETs).

3. The arrangement of claim 2 wherein the current sensing resistor includes an electrical path at the first end of said current sensing resistor connected to a source of a first FET of the back-to-back FETs and wherein the current sensing resistor includes an electrical path at the second end of said current sensing resistor connected to the source of a second FET of the back-to-back FETs.

4. The arrangement of claim 3 wherein an emitter of the first transistor includes an electrical path connected to the second voltage across the current sensing resistor and wherein a base of the first transistor includes an electrical path connected to the first voltage across the current sensing resistor.

5. The arrangement of claim 4 wherein an emitter of the second transistor includes an electrical path connected to the first voltage across the current sensing resistor and wherein a base of the second transistor includes an electrical path connected to the second voltage across the current sensing resistor.

6. The arrangement of claim 5 wherein the first means provided by the first transistor conduction and second means provided by the conduction of the second transistor to turn OFF the FETs includes a third transistor having an electrical path into connected gates of the back-to-back FETs.

7. The arrangement of claim 6 wherein the third transistor is an NPN BJT transistor and wherein a collector of the third transistor includes an electrical path into the connected gates of the back-to-back FETs.

8. The arrangement of claim 7 wherein a first resistor is connected in series to the base of the first transistor and a second resistor is connected in series to the base of the second transistor.

9. The arrangement of claim 8 wherein each of the first transistor and the second transistor includes a collector resistor wherein each collector resistor is connected at one end to draw current via a threshold recognition resistor connected to a positive DC power supply arrangement.

10. The arrangement of claim 9 further including a fourth transistor in electrical communication with the threshold voltage recognition resistor such that when current flowing into the threshold voltage recognition resistor exceeds a threshold voltage the fourth transistor is adapted to ON.

1 1. The arrangement of claim 10 wherein the fourth transistor is a PNP BJT transistor and wherein the collector of the fourth transistor includes an electrical path connected to a zero volt reference via a resistor pair connected in series and a further electrical path through a current limiting resistor into a base of the third transistor.

12. The arrangement of claim 1 1 wherein the resistor pair connected in series connected to the collector of the fourth transistor are separated at a junction by a single electrical path into an interface pin of a microcontroller.

13. The arrangement of claim 12 further including a capacitor across the threshold voltage recognition resistor.

14. The arrangement of claim 13 wherein the microcontroller is programmed with a high impedance input configuration for the interface pin.

15. The arrangement of claim 14 wherein the microcontroller includes a separate control path into the connected gates of the back-to-back FETs adapted to turn OFF the back-to-back FETs.

16. The arrangement of claim 15 wherein the micro-controller includes an inbuilt temperature sensor.