WO2014204294A1 - An analogue to digital converter - Google Patents

An analogue to digital converter Download PDF

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Publication number
WO2014204294A1
WO2014204294A1 PCT/MY2014/000097 MY2014000097W WO2014204294A1 WO 2014204294 A1 WO2014204294 A1 WO 2014204294A1 MY 2014000097 W MY2014000097 W MY 2014000097W WO 2014204294 A1 WO2014204294 A1 WO 2014204294A1
Authority
WO
WIPO (PCT)
Prior art keywords
radix
digital
analogue
segment
binary
Prior art date
Application number
PCT/MY2014/000097
Other languages
French (fr)
Inventor
Tan KONG YEW
Abdul Majid Hasmayadi
Original Assignee
Mimos Berhad
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mimos Berhad filed Critical Mimos Berhad
Publication of WO2014204294A1 publication Critical patent/WO2014204294A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
    • H03M1/069—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps
    • H03M1/0692—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps using a diminished radix representation, e.g. radix 1.95
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
    • H03M1/687—Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type

Definitions

  • the present invention relates to an analogue to digital converter (ADC) which
  • the performance of analog to digital converters is generally limited by the matching accuracy of components. Improving the matching accuracy, while possible, is expensive or requires extra chip area.
  • the Binary Weighted DAC contains binary weighted resistor, capacitor or current source segment for each possible value of DAC output. This is one of the fastest conversion methods but suffers from poor accuracy because of the high precision required for each individual voltage or current. Such high-precision resistors, capacitors or current sources are sophisticated, so this type of converter is usually limited to 8-bit resolution or less.
  • thermometer coded DAC contains an equal resistor, capacitor or current source segment for each possible value of DAC output.
  • An 8-bitthermometer weighted DAC would have 255 segments, and a 16-bit thermometer weighted DAC would have 65,535 segments. This is perhaps the highest precision DAC architecture but a large area incurred thus hindering the balance of performance between the accuracy and speed.
  • the segment elements including: a binary to thermometer/ unitary decoder for unitary weight segment (3000); and a binary to radix ⁇ 2 decoder for (radix ⁇ 2) weight segment (2000) wherein the input signal is compared with the signal charged on capacitors from plurality of digital to analogue converter block (300) capacitor beginning from the most significant bit down to the least significant bit.
  • thermometer coded principle for the most significant bits and the binary weighted principle for the least significant bits.
  • a compromise is obtained between precision (by the use of the thermometer coded principle) and number of resistors, capacitors or current sources (by the use of the binary weighted principle).
  • the present invention not only combines the thermometer coded and binary coded segments but also a segment that has sub-radix 2 (radix ⁇ 2) weights.
  • Figure 2 illustrates block diagram of an example 12 bit multi segmentdigital to
  • the segment elements including: a binary to thermometer/unitary decoder for unitary weight segment (3000); and a binary to radix ⁇ 2 decoder for (radix ⁇ 2) weight segment (2000) wherein the input signal is compared with the signal charged on capacitors from plurality of digital to analogue converter block (300) capacitor beginning from the most significant bit down to the least significant bit.
  • FIG. 2 illustrates block diagram of an example of 12 bit multi segmentdigital to analogue converter block (300)with 4 bit radix 1.6 weighted (2000) + 4 bit unitary/thermometer weighted (3000) + 4 bit binary weighted (1000) capacitor array.
  • the specialdigital to analogue converter block (300)combination gives the best trade-off in terms of area, performance (DNL as measurement of static linearity) and complexity as there is no need to use attenuation or split capacitor especially for higher resolutiondigital to analogue converter blocksuch as 10 - 12 bits.
  • the unitary/ thermometer weighted capacitor array uses largest area but gives best linearity (as measured by this metric DNL, Differential Non-linearity) whereas binary weighted capacitor array uses the least area but gives the worst linearity (as measured by this metric DNL, Differential Non-linearity) and radix ⁇ 2 weighted capacitor array uses an area in between binary and unitary and gives linearity as well in between binary and unitary weighted DNL.

Abstract

The present invention relates to a small area multi segment DAC that is used within a successive approximation analog to digital converter. The present invention comprising: a comparator (100) for comparing input signal with a reference signal; a successive approximation logic (200) that takes input from the comparator (100); and a digital to analogue converter block (300) including a plurality of capacitors that receives input from the successive approximation logic (200) block and generates reference signal that is applied to the comparator (100). The present invention not only combines the thermometer coded (3000) and binary coded segments (1000) but also a segment that has sub-radix 2 (radix < 2) weights (2000). A sub-radix 2 weights (2000) is in between binary (1000) and unitary weights (3000), hence its area and decoder size is also in between the two while its differential non-linearity DNL parameter (measure of linearity) is in between the two as well.

Description

Description
Title of Invention: AN ANALOGUE TO DIGITAL CONVERTER
[ 1 ] FIELD OF INVENTION
[2] The present invention relates to an analogue to digital converter (ADC) which
converts the analogue signal to digital signal.
[3] BACKGROUND OF THE INVENTION
[4] The performance of analog to digital converters is generally limited by the matching accuracy of components. Improving the matching accuracy, while possible, is expensive or requires extra chip area. The Binary Weighted DAC contains binary weighted resistor, capacitor or current source segment for each possible value of DAC output. This is one of the fastest conversion methods but suffers from poor accuracy because of the high precision required for each individual voltage or current. Such high-precision resistors, capacitors or current sources are sophisticated, so this type of converter is usually limited to 8-bit resolution or less.
[5] The thermometer coded DAC contains an equal resistor, capacitor or current source segment for each possible value of DAC output. An 8-bitthermometer weighted DAC would have 255 segments, and a 16-bit thermometer weighted DAC would have 65,535 segments. This is perhaps the highest precision DAC architecture but a large area incurred thus hindering the balance of performance between the accuracy and speed.
[6] Therefore it is a need for an invention that can tackle those drawbacks.
[7] SUMMARY OF THE INVENTION
[8] According to an aspect of the present invention, the present invention providesan analogue to digital converter comprising: a comparator (100) for comparing input signal with a reference signal; a successive approximation logic (200) that takes input from the comparator (100) for determining the digital output code; and a digital to analogue converter block (300) iqcluding a plurality of capacitors that receives input from the successive approximation logic (200) block and generates reference signal that is applied to the comparator (100); characterised in that the digital to analogue converter block (300) further comprising a plurality of a binary weight (radix = 2) segment (1000), a (radix < 2) weight segment (2000) and a unitary weight (radix = 1) segment (3000) elements. The segment elements including: a binary to thermometer/ unitary decoder for unitary weight segment (3000); and a binary to radix < 2 decoder for (radix < 2) weight segment (2000) wherein the input signal is compared with the signal charged on capacitors from plurality of digital to analogue converter block (300) capacitor beginning from the most significant bit down to the least significant bit.
[9] The above provision is advantageous as the present invention combines the thermometer coded principle for the most significant bits and the binary weighted principle for the least significant bits. In this way, a compromise is obtained between precision (by the use of the thermometer coded principle) and number of resistors, capacitors or current sources (by the use of the binary weighted principle).
[10] The present invention not only combines the thermometer coded and binary coded segments but also a segment that has sub-radix 2 (radix < 2) weights. A sub-radix 2 weights is in between binary and unitary weights, hence its area and decoder size is also in between the two (for example for radix = 1.6, 6-bit sub-radix 2 DAC would have 7 segments) while its differential non-linearity DNL parameter (measure of linearity) is also in between the two.
[1 1 ] The present invention provides the optimal compromise between complexity and accuracy.
[ 12] BRIEF DESCRIPTION OF THE DRAWINGS
[13] Figure lillustrates Successive Approximation Analog Digital Converter (SA-ADC) block diagram.
[14] Figure 2illustrates block diagram of an example 12 bit multi segmentdigital to
analogue converter block (300)with 4 bit radix 1.6 weighted (2000) + 4 bit unitary/ thermometer weighted (3000) + 4 bit binary weighted (1000) capacitor array.
[15] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[16] As illustrated in Figure 1, generally, the present invention relates to an analogue to digital converter comprising: a comparator (100) for comparing input signal with a reference signal; a successive approximation logic (200) that takes input from the comparator (100) for determining the digital output code; and a digital to analogue converter block (300) including a plurality of capacitors that receives input from the successive approximation logic (200) block and generates reference signal that is applied to the comparator (100); characterised in that the digital to analogue converter block (300) further comprising a plurality of a binary weight (radix = 2) segment (1000), a (radix < 2) weight segment (2000) and a unitary weight (radix = 1) segment (3000) elements. The segment elements including: a binary to thermometer/unitary decoder for unitary weight segment (3000); and a binary to radix < 2 decoder for (radix < 2) weight segment (2000) wherein the input signal is compared with the signal charged on capacitors from plurality of digital to analogue converter block (300) capacitor beginning from the most significant bit down to the least significant bit.
[17] As illustrated in Figure 2,it illustrates block diagram of an example of 12 bit multi segmentdigital to analogue converter block (300)with 4 bit radix 1.6 weighted (2000) + 4 bit unitary/thermometer weighted (3000) + 4 bit binary weighted (1000) capacitor array.The specialdigital to analogue converter block (300)combination gives the best trade-off in terms of area, performance (DNL as measurement of static linearity) and complexity as there is no need to use attenuation or split capacitor especially for higher resolutiondigital to analogue converter blocksuch as 10 - 12 bits. The unitary/ thermometer weighted capacitor array uses largest area but gives best linearity (as measured by this metric DNL, Differential Non-linearity) whereas binary weighted capacitor array uses the least area but gives the worst linearity (as measured by this metric DNL, Differential Non-linearity) and radix < 2 weighted capacitor array uses an area in between binary and unitary and gives linearity as well in between binary and unitary weighted DNL.
Although the invention has been described with reference to particular embodiment, it is to be understood that the embodiment is merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiment that other arrangements may be devised without departing from the scope of the present invention as defined by the appended claims.

Claims

Claims
[Claim 1 ] An analogue to digital converter comprising:
a comparator (100) for comparing input signal with a reference signal; a successive approximation logic (200) that takes input from the comparator ( 100) for determining the digital output code; and a digital to analogue converter block (300) including a plurality of capacitors that receives input from the successive approximation logic (200) block and generates reference signal that is applied to the comparator ( 100);
characterised in that
the digital to analogue converter block (300) further comprising a plurality of a binary weight (radix = 2) segment ( 1000), a (radix < 2) weight segment (2000) and a unitary weight (radix = 1 ) segment (3000) elements.
[Claim 2] An analogue to digital converter as claimed in Claim 1 , wherein the segment elements further comprising: a binary to thermometer/unitary decoder for unitary weight segment (3000); and a binary to radix < 2 decoder for (radix < 2) weight segment (2000), wherein the input signal is compared with the signal charged on capacitors from plurality of digital to analogue converter block (300) capacitor beginning from the most significant bit down to the least significant bit.
[Claim 3] An analogue to digital converter as claimed in Claim 1, wherein the digital to analogue converter block (300) further comprising 12 bit multi segmentdigital to analogue converter block(300) with 4 bit radix 1.6 weighted (2000), 4 bit unitary/thermometer weighted (3000), and 4 bit binary weighted (1000) capacitor array.
PCT/MY2014/000097 2013-06-19 2014-05-02 An analogue to digital converter WO2014204294A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
MYPI2013002294A MY177180A (en) 2013-06-19 2013-06-19 An analogue to digital converter
MYPI2013002294 2013-06-19

Publications (1)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108574487A (en) * 2017-03-14 2018-09-25 爱思开海力士有限公司 Successive approximation register analog-digital converter with the digital analog converter based on split capacitor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7812757B1 (en) * 2009-06-12 2010-10-12 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Hybrid analog-to-digital converter (ADC) with binary-weighted-capacitor sampling array and a sub-sampling charge-redistributing array for sub-voltage generation
US20120200442A1 (en) * 2011-02-08 2012-08-09 Maxim Integrated Products, Inc. Precision sub-radix2 dac with linearity calibration

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7812757B1 (en) * 2009-06-12 2010-10-12 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Hybrid analog-to-digital converter (ADC) with binary-weighted-capacitor sampling array and a sub-sampling charge-redistributing array for sub-voltage generation
US20120200442A1 (en) * 2011-02-08 2012-08-09 Maxim Integrated Products, Inc. Precision sub-radix2 dac with linearity calibration

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108574487A (en) * 2017-03-14 2018-09-25 爱思开海力士有限公司 Successive approximation register analog-digital converter with the digital analog converter based on split capacitor
CN108574487B (en) * 2017-03-14 2021-09-24 爱思开海力士有限公司 Successive approximation register analog-to-digital converter

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Publication number Publication date
MY177180A (en) 2020-09-09

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