WO2012163395A1

WO2012163395A1 - An apparatus and a method of parallel receipt, forwarding and time stamping data packets using synchronized clocks

Info

Publication number: WO2012163395A1
Application number: PCT/EP2011/058816
Authority: WO
Inventors: Peter Korger
Original assignee: Napatech A/S
Priority date: 2011-05-30
Filing date: 2011-05-30
Publication date: 2012-12-06

Abstract

An apparatus comprising number of receiving and forwarding means and a controller. The receiving and forwarding means receiving and time stamping packets using clocks synchronized to a controller clock. The controller forwards a point in time to the receiving and forwarding means which add a transmission delay to have all clocks synchronized.

Description

AN APPARATUS AND A METHOD OF PARALLEL RECEIPT, FORWARDING AND TIME STAMPING DATA PACKETS USING SYNCHRONIZED CLOCKS

The present invention relates to a method of facilitating parallel receiving of data packets and time stamping these using synchronized clocks. In a number of set-ups, data packets may be received in parallel from a data connection or a plurality of parallel data connections but are desired handled or at least tagged in an order of reception. The present invention relates to a manner of obtaining such tagging or time stamping.

In a first aspect, the invention relates to an apparatus according to claim 1. In the present context, the apparatus is formed by a number of separate elements. The receiving elements are physically separate or separatable/detachable from each other so as to be individually replaceable/removable/introducible so that e.g. more or fewer receiving elements may be used to fulfil different requirements or desires. This exchange may be under any data transfer protocol, such as TCP, Ethernet, Bluetooth or the like, and using any type of data transfer, wired and/or wireless.

Also, the receiving elements thus are provided as separate pieces of hardware, and may each be embodied by a separate PCB, processor, FPGA or the like. Alternatively, the same

PCB/processor/FPGA may form an assembly being a plurality of the receiving elements where multiple such receiver element assemblies are then used. The controlling unit may be separate from the receiving elements or may form part of one or more thereof but is connected to the receiving elements so as to exchange data therewith.

Naturally, the individual means of the receiving elements may be obtained or shaped as individual elements, such as processors, software controlled or hardwired, FPGAs, special purpose circuits, ASICS or the like. Alternatively, multiple such means may be combined into a single such processor or the like.

Any number of receiving elements may be used, such as 2, 3, 4, 5, 6, 7, 8, 10, 15, 20 or more. These receiving elements may, as is described further below, be identical or nearly identical, or they may be instantiated or created as different circuits with different operations. Each receiving element may have a controlling unit, but only one is required. In another situation, only one receiving element comprises the controlling unit but is otherwise identical to the remaining receiving element. The controlling unit may be formed by any type of processor, hardwired or software controlled, or may be a special purpose circuit. The operation of the controlling unit is to synchronize the local clocks in order to obtain comparability of the time stamping carried out in the individual determining means. The communication links between the controlling unit and each receiving element may be any type of link, serial or parallel, wired and/or wireless, supporting any type of

communication, such as Ethernet, Bluetooth, WiFi, or communication standards usually used in computer systems and e.g. on motherboards.

The accessing/receiving means may actually receive and/or store the data or data packet. Alternatively, the data packet may be received or stored at another position or in an apparatus with which the receiving element communicates, whereby the data of the data packet is accessed remotely by reading the data while being stored in the other apparatus. The latter will usually provide a slower processing, as the data packet is accessed remotely.

The determining means is adapted to determine a point in time or receipt/access of a data packet. In general, any representation of time may be used, such as a standard

representation of a time; hour/minute/second. Alternatively, time may be represented in a more simple manner by a number. Naturally, this number may be wrapped around if desired.

As time naturally will change, the time or number is altered, such as

incremented/decremented, preferably at equidistant points in time. The passing of the time in the local clock of the individual determining means is controlled by a periodic signal, which is used for incrementing/decrementing the time/number. This periodic signal may be that derived by the second means or may be controlled thereby.

Usually, information is exchanged between elements on the basis of a periodic signal. This is the case both for analogue and digital signals. At times, multiple periodic signals may be involved, but only one is required. This periodic signal is generated by the transmitter and may be derived by the receiver. According to the invention, the second means derives this signal, which is also used by the fourth means when outputting information to the controlling unit.

Naturally, a periodic signal may be derived from another periodic signal by multiplying or down converting the frequency thereof. Using the same periodic signal both for the transmission and reception of the information as well as for the clocks of the controlling unit and the data receiving elements, at least the decrementing/incrementing of the times of all clocks are synchronized.

The local clocks are controllable by the derived signal. However, if information is not permanently received from the controlling unit, the derived signal may not always be available. In that situation, the local clocks may have an oscillator, the output of which may be controlled by the derived signal when available and which will then generate the periodic signal for decreasing/increasing the local time at least when no derived signal is available.

An alternative would be to ensure that data is always exchanged between the controlling unit and the data receiving element, whereby the derived periodic signal may always be available from that source.

The first information may comprise any representation of the point in time, such as the actual time or number, or any data derived therefrom. Preferably, the outputting means of all receiving elements output the same type of data, such as time or number, in order for the data to be directly comparable.

The information output of the outputting means of the controlling unit comprises a point in time, and the local time is set to this point in time added a transmission delay which will be described below. Therefore, the controlling unit is able to set the local points in time while the passing of time (decreasing/increasing) is synchronized to the periodic signal from the clock of the controlling unit.

When the clocks of the determining means are synchronized, the points in time of the receiving/forwarding means will be synchronized. Either the times of all clocks are the same, or offsets exist. If any two or more of the receiving elements means receive a data packet simultaneously, they will then preferably determine the same point in time and, preferably, the first information generated to these simultaneously received data packets will comprise the same point in time, such as the same number.

In one situation, the synchronized clocks will all, within a predetermined tolerance, simultaneously output identical points in time. In this respect, the "tolerance" may be within 1, 2, 3, 5, 10 or more clock cycles or timing units as defined by the periodic signal of the controller clock.

The transmission delay may be determined in each of two manners both characterized in a signal/information/message being transmitted from one of the controlling unit and the data receiving element and returned, where the transmission delay is determined from the time of transmission of the signal/message/information and the time of receipt of the return message/information/signal. In one manner, the controlling unit transmits a first signal to the second means of the data receiving element and logs a local point in time of transmittal of the first signal. Then, the controlling unit receives a signal from the fourth means of the data receiving element and logs a local time of receipt.

In the other manner, the data receiving element transmits, from the fourth means thereof, a third signal to the controlling unit and logs a local point in time of transmittal of the third signal, where after the second means of the data receiving element receives a fourth signal from the controlling unit and logs a local time of receipt.

In both circumstances, the transmission delay is determined from the time of transmission and the time of receipt.

As mentioned above, it is preferred that the representations of time in all determining means and the controlling means are the same.

In this situation, it is preferred that the data receiving element or the controlling means is adapted to receive the signal/message/information and immediately transmit a

signal/message/information to the other of the data receiving element and the controlling means. When the processing delay in the controlling means or the individual determining means is small, the transmission delay from controlling unit to the determining means may be determined as half the difference between the time of transmission and the time of receipt. If the processing delay in the controlling means or the determining means is not negligible, this may be taken into account. Naturally, different time delays may be present for different determining means.

Knowing the time delay, the individual determining means may be synchronized to the controlling unit by ensuring that the number, or any other representation of a point in time, is the same as that of the controlling unit. It is noted that the third and fourth means have different characteristics. These may be one and the same element which then outputs the information to the controlling unit based on the derived signal and which information relates to the point in time. Naturally, the third and fourth means may also output information to different elements, and the third means may output the point in time not based on the derived periodic signal.

In that or another situation, it may be desired to also store the data packet received. In this situation, it may be desired that: - the data receiving elements further comprise: means for receiving an address for storing at least part of the data packet, and means for facilitating storage of the at least part of the data packet at the address, - the controlling unit or another unit comprising : means for receiving the first information and means for, for each piece of first information received, determining an address and returning the address to the receiving means of the pertaining data receiving element. In general, the receiving/accessing means, the forwarding means and the facilitating means usually comprise drivers, connectors etc. required to handle this operation and communicate the data as required.

The address determining functionality is not necessarily performed in the controlling unit. Another unit may be provided which is or is not a part of the controlling unit or a data receiving element. As is the situation with the elements and means, this unit may also be instantiated as part of another element or means or may be separate therefrom and communicating with the individual elements using any of the above data communication methods and set-ups.

Preferably, the address is determined on the basis of the first information. This may be obtained in a number of manners. In one example, the address is determined from the point in time, and the purpose thereof may be to have the data packets, or the parts thereof, stored in an order of receipt. In another situation, the first information comprises additional information relating to the data packet, see further below, so as to determine a stream/type or the like of a data packet. Thus, not only the point in time may be used for determining the address, but data packets of certain streams or types may be stored together.

Even though it is less preferred, the address received may not be the actual address in the storing unit at which the data packet is to be stored. Alternatively, information may be received from which this address may be derived.

The controlling unit or other unit then will, for each piece of first information and thus each data packet, return an address.

In general, a data packet may be any type of a data unit to be transmitted on or transported by a network, data cable, data bus, trunk, or the like. Normally, a data unit conforms to one or more data standards, such as the Ethernet standard being an umbrella under which a number of different standards or data packet types exist, such as UDP and TCP data packets. A data packet usually has a number of different information items or types, such as address data, payload or the like, which are each positioned at well defined or known positions within the data packet. Such positions and types will typically differ from data packet type to data packet type, but usually, the data packet type, and thus the positions of individual contents thereof, may be determined from the actual data packet, where after the individual data items, such as address data and/or payload, may be derived, altered, and/or used in the analysis. The type or standard may be derived directly from the data packet, such as when a particular data item of the packet identifies the type/standard, or may be derived from data derived from the data packet, such as on the basis of recognition of types and positions of data items of the data packet and subsequently determination of type(s) or standard(s) of data packet in which such data may be found at such position(s).

Any part of a data packet may be stored. If the data packet is not desired output again, addressing information therein, e.g., may be deleted in order to not take up space. Data packets may be ordered and, if so, in a multiple of manners and for a number of reasons. Usually, data exchange between computers is a file transfer, TCP transfer, VoIP or the like, where the order of the individual packets is important. Usually, such transfers are called streams.

A stream of data packets normally is a sequence of data packets transmitted from a single transmitter to one or more receivers. These data packets relate to e.g. a single file or the like transmitted in smaller portions, being the payload of the packets. The transmitter and receiver, or any intermediate network elements, will usually then have addresses also represented in the packet. In addition, other stream identifying information may be present in the data packet, depending on the individual data packet standard.

Thus, a stream may be identified on the basis of e.g. the addresses and/or the stream identifying information, whereby, if used consistently, the same information may be derived, and any subsequent process may identify the stream merely from the information. Then, the packets of each stream may be stored in separate queues. Such information may also be provided in the first information, and the determined address may be determined also on the basis of such information.

In another situation, data packets may be provided with information therein determining the order thereof, such as a sequence number. Thus, also this information may be used for ordering the packets.

The facilitating means may store the at least part of the data packet directly in e.g. a storing unit, such as over a data connection or it may facilitate storing of the data packet if stored at another location. Then, the address may be transferred to this other location, which then handles the storing of the data packet.

A second aspect of the invention relates to an assembly comprising an apparatus according to the first aspect and a storage comprising a plurality of addresses at which data may be stored, the facilitating means being adapted to store the at least part of the data packet at the received address in the storage. This storage usually will be separate from the receiving means and/or controller but connected thereto so as to exchange data therewith (over wires or wirelessly).

Naturally, the storing unit may be any form of storing unit, such as a monolithic storing unit or one composed by a number of storing elements separated in space. Usual storing technologies are based on hard drives, floppy discs, RAM, ROM, PROM, EPROM, EEPROM, Flash, memory cards, CD-ROM, DVD, memory cards, or the like.

If separate storing units are provided, the address will describe both the identity of the actual storing unit and the "local address" therein.

Data packets may have different sizes and may then take up a different numbers of addresses. Preferably, a plurality of queues are defined in the storage as separate or non-overlapping groups of addresses, the determining means of the controlling unit being adapted to determine, from the first information, a queue to which to add the pertaining data packet, and to select an address from the groups of addresses of the pertaining queue.

A third aspect of the invention relates to a method of operating an apparatus according to claim 4. As mentioned above, the point in time of receipt/access may be represented differently in different receiving elements, as long as these are comparable, such as on the basis of knowledge of the differences between such representations.

Again, the synchronization is based at least on the synchronization of the passing of time, i.e. the incrementing and/or a decrementing of time or a number/value representing time. As mentioned above, this preferably also includes a synchronization of an actual point in time.

The local clock may comprise a local oscillator synchronized to the derived periodic signal for use when data is not transmitted from the controlling unit and, thus, no derived periodic signal is available. Alternatively, information may constantly be output by the controlling unit for receipt by the data receiving elements for a derived periodic signal to always be available. The transmission delay may be determined as half the difference between the time of transmission and the time of receipt, assuming that the controlling means or the determining means does not delay transmission of the signal output. If a delay is seen in the controlling means or the determining means, this may be taken into account.

Then, the controlling means or each of the one or more determining means may be adapted to, when receiving the first signal, immediately transmit a signal to the other of the determining means and the controlling means, in order to ensure that the delay determined primarily is a transmission delay and not a delay caused by the controlling means or the determining means.

In this situation, "immediately" will mean that no delay is introduced. This term may mean that the signal is output within a predetermined maximum period of time after receiving the first signal, such as within 100ns, such as within 10ns.

In a preferred embodiment: the receiving elements further: receive an address for storing at least part of the data packet, and facilitate storage of the at least part of the data packet at the address, the controlling unit or another unit: - receives the first information and for each piece of first information received, determines an address and returns the address to the receiving means of the pertaining data receiving element.

Thus, the controlling unit is also used for deriving an address, or another unit is used therefore, from the information received from the data receiving means. As mentioned above, this information may be the time of receipt alone, or may also relate to address data, stream data or the like.

Obviously, the facilitating step preferably comprises storing the at least part of the data packet at the received address in a storage comprising a plurality of addresses at which data may be stored.

In the following, preferred embodiments of the invention will be described with reference to the drawing, wherein : figure 1 illustrates a first embodiment according to the invention, figure 2 illustrates conversion from virtual address to physical address, - figure 3 illustrates synchronization of clocks between the allocator and an adapter of figure 1,

figure 4 illustrates a manner of ordering randomly received packets in a time sequence,

figure 5 illustrates load balancing between processors while maintaining order between the data packets, and

figure 6 illustrates load balancing within an adapter.

In figure 1, an embodiment 10 of an apparatus for analyzing and forwarding data frames is illustrated having a number of adapters 12 each connected to and receiving data from a network, such as the WWW. In this embodiment, the adapters 12 are individual blades or PCBs attachable to a bus structure or other structure which may also comprise the bus 32 described further below. Then, more or fewer such adapters 12 may be provided in order to alter the performance of the system.

In general, a system of this type may be used for receiving a large number of data packets and facilitate storage and/or forwarding thereof in a suitable manner. These data packets usually are transmitted between pairs of computers or networks on a data connection monitored by the present system. Thus, the data packets normally are not meant for nor addressed to or from the present system.

This data may, when stored, be processed by one or more subsequent processes or processors (not illustrated). In order to be able to handle very large amounts of data, structured storing is desired in order to achieve swift, yet structured, retrieval of the data. Also, a plurality of processors is provided when a single processor does not suffice, whereby separate storing of data for each processor is desired.

The processors may be used for analyzing the data traffic, for storing the data and/or for transmitting the data to other network elements, computers or the like, depending on the result of the processing in the processors.

Alternatively, or additionally, it may be desired to subsequently output the data again, whereby it may also or alternatively be desired to store the data in a manner or sequence in which the outputting is desired.

Normally, the data packets are parts of streams of data packets. When two processors or computers interact, a stream of data packets is exchanged. This stream may be a file transfer or an exchange of audio/video, such as Voice over IP. A stream is a sequence of data packets which are similar, and the belonging of a data packet to a stream is determinable, and it is desired that all data packets of a stream are stored together, in the desired order, handled by the same subsequent process or processor and/or output in that order.

The belonging of a received data frame to a stream is determined from an analysis of the frame. This analysis is described in further detail below. The present embodiment aims at providing a set-up in which multiple adapters 12 divide the task of analyzing the frames/packages and/or storing these. More particularly, the adapters 12 receive data frames from the network 14, such as the WWW, a trunk or network of any suitable type. Each adapter 12 receives a number of frames independently of the other adapters 12.

Preferably, all adapters, potentially except one, are identical and each comprises a so-called PHY 20, which is an element adapted to receive data frames from a network or data cable and a so-called MAC circuit 22 which converts the received frames to a standard usually used on data busses on e.g. computers.

Having received the data frame, it is provided with a time stamp in the circuit 24, where after the frame is fed to an analyzing circuit 26 which derives data relating to the data frame, such as relating to a standard the frame conforms to, such as whether it is VLAN and/or MPLS tagged, and potentially address data therefrom. A plurality of different types of standards are known, each of which defines which types of data (address, encapsulation, payload, error correction etc) are present in the frame and where such data is present. Depending on the particular type of packet, different types of data may be derived.

The circuit 26 outputs data identifying the data frame, such as its belonging to a data packet stream, or a queue in a central storage. Then, the length of the data frame, the ID/queue identification and the time stamp of the data frame is transmitted, in a request circuit 28, to a central server memory allocator or controller 16, which returns an address within the storage 18 in which the data frame is to be stored. This address is returned to a transfer circuit 30 also receiving the data frame and which subsequently transmits the data frame to the identified address via a common data bus 32, such as running a PCI Express (PCIe) protocol. This storing may be using Direct Memory Addressing, which means that the frame is stored directly at the desired address, and that no further analysis is required. This is the fastest manner of storing data in a data storage, but it requires that the physical address is known.

Naturally, the circuit 28 may alternatively output, together with or without the time stamp and length of the packet, other information identifying the frame (type, addresses or the like), whereby the allocator itself will determine the queue to which the frame is to be added and thus derive the address at which the frame is to be stored.

The "out of band" communication between the allocator 16 and the adapters 12 may be a low bandwidth point-to-point communication, a daisy chain topology, or a ring topology. This communication, as is described further below, is also used for synchronizing the clocks of the time stamp circuits 24. A suitable protocol for this communication may be a standard 64b/66b codec requiring approximately lGbps full duplex bandwidth per lOGbps of Ethernet front port (PHY) bandwidth.

It is noted that the above embodiment 10 may store the data frames in any number of queues in the storage 18. Which queue to forward a data packet to may depend on the future destiny of the frame. If the frame is to be analyzed by one or more processors, one queue may be provided for each processor, and the forwarding of frames to a queue may depend on how long the queue is before adding the packet. If the queue is long, and the processor thus busy, the packet may be provided in a shorter queue of a processor thus less busy.

It is noted that if most data frames relate to streams, it may not be desired to transmit frames relating to the same stream to different queues for analysis by different processors. In this manner, any load balancing between processors is preferably carried out by allocating all future frames from a newly started stream to a "starving" processor. An alternative to this is described further below, as is this load balancing.

Also, if the frame is at a later point in time to be output from the storage 18, the frames to be output may be provided in a particular queue and in an order in which the frames are to be output. Such outputting is described further below.

If a given quality of service is desired, any queue may be split up into a number of queues of different priorities, so that higher priority frames may overtake lower priority frames and then be handled (processed, output, analyzed or the like) swifter. Load balancing within an adapter 12

In Figure 6, it is seen that part of the elements, such as the PHY 20, MAC 22 and Time Stamp allocation 24 of an adapter 12 may be working at a higher speed than that of the other elements, such as the analyzer 26, the requester 28 and the transfer circuit 30. In this situation, multiple "instantiations" of these slower elements may be made in order to divide the data packet flow received and time stamped from the elements 20-24 into multiple parallel flows. In figure 6, the data packets received on a single PHY 20 are divided into four parallel flows. The elements 20-30 are not directly illustrated, but their positions in the flow are.

Naturally, load balancing between the individual flows may be carried out if desired. The lower line in figure 6 illustrates the alternative, where a high speed PHY 20 receives data packets which are handled in a single flow in the adapter 12. Load balancing of external processes or processors using multiple queues

Load balancing of processors or processes (not illustrated) reading data from the queues of the storage 18 may be performed in a number of manners. If an ordering (order of receipt or defined by data in the individual data packets) of data packets in stream or the like is not relevant, a single queue may be provided for each processor. If the queue of one processor runs full (how this may be determined is described further below), the allocator 16 may simply effect that more data packets is transmitted to the other queue(s).

If quality of service is desired, different queues may be used for different priorities.

If an ordering of the data packets of e.g. a stream is desired maintained, a scheme is illustrated in figure 5, wherein two adaptors 12 are illustrated receiving a total of 4 flows/streams of data.

The adaptors 12 transmit the data packets to a total of 8 queues (no. #0-#7) stored in the storage 18 for de-queuing by two processors (no. #0 and #1) using the following scheme: queues #0-#3 are handled by processor #0, and queues #4-#7 are handled by processor #1. Also, queues #0 and #4 are generally used for stream #0, queues #1 and #5 are used for stream #1 and so on.

Initially, data packets of stream #0 are transmitted to queue #0, but as this queue grows full, the allocator 16 starts transmitting data packets from stream #0 to queue #4. However, processor #1 is not allowed to de-queue and analyze such packets, until processor #0 has emptied queue #0. In order to control this, four bits are allocated, one for each stream, the value of which determines which processor may handle packets from each queue. In figure 5, the top bit controls the access to stream #0, and as its value is "0", this means that processor #0 may handle this queue and thus de-queue packets from queue #0.

It is seen that the two bottom bits are "1" indicating that processor #1 is allowed to handle streams #2 and #3 and thus de-queue from queues #6 and #7. When a processor is allowed to process more than a single queue, it may select the next queue to be processed in any suitable manner, such as round robin, priority, queue length, or the like.

The four bits are controlled by the processors and stored in the storage 18. When more than two processors are used, an ordering or sequence thereof is decided, so that when processor #1 has emptied a queue, either it will alter the corresponding bit(s), or processor #2 will notice that the queue of processor #1 is empty, alter the corresponding bit(s) and then start de-queuing its corresponding queue. The same order is used by the controller to determine to which queue, if one is full, to add the next data.

Then, in order to maintain the ordering of the data in the queues, the allocator 16, if changing a queue, will always select a new queue which is empty. Naturally, if more than two processors are able to handle a single queue, more bits are used for each flow to indicate which processor is presently allowed to process the flow.

Virtual address - physical address

In order to make the set-up more easily adapted to different systems, it is preferred that the request circuit 28, the transfer circuit 30, the allocator 16 as well as any de-queuing circuitry in or connected to the storage 18 operate in a virtual address space.

Due to the standard requirement that only a given maximum block size may be allocated for DMA, and the fact that such allocated blocks may be positioned at different or random positions in the memory in different systems or from time to time of operating the same apparatus, direct operation using the physical addresses becomes cumbersome. Hence, virtual addresses are preferred.

Presently, an address (see figure 2) with a total length of 32 bits is divided into two parts of which one part has a number of bits adapted to address all addresses in a maximum size allocatable block. In the present example, the max size block or segment has a size of 4MB, requiring 22 bits for addressing. This part of the virtual and physical address is the same and is used for addressing within a single block/segment.

In order to avoid the fact that physical blocks/segments may be positioned at different addresses in the storage 18, the virtual addresses are all, at least for each queue, defined as consecutive addresses, irrespective of the fact that these may be positioned in different blocks/segments. Thus, the 32 bits will be interpreted as a number of consecutive addresses. This may be sub-divided into a number of 4Mbyte blocks/segments, but virtually positioned consecutively. The virtual address may thus be seen as an initial 10-bit part indicating one of the consecutive virtual blocks/segments and the last 22 bits as an internal addressing within this block/segment.

In the physical reality in the storage 18, the last 22 bits addressing within a segment/block may be maintained, but the first 10-bit part of the virtual address is simply converted into an addressing or identification of one of the physically allocated blocks/segments. For this use, a Look Up Table is provided for translating the first 10 bits of the virtual address to an actual identification - i.e. a 10-bit address - of an actually allocated block/segment. This Look-Up Table (LUT) may be set up at initialization of the embodiment. This is illustrated in figure 2. It is noted that also the read/write pointers, which are described below, may be used in the virtual address space, which again makes e.g. determination of a queue length much easier, when the virtual addresses are defined as sequential addresses.

Naturally, as will be seen further below, if a process/processor de-queues a data item from the storage 18, the address and size (or number of addressable elements taken up) thereof may be returned to the allocator 16 as the physical address or the virtual address. In either case, the allocator 16 is able to determine the virtual address and update the pointers accordingly.

Timing - synchronization of clock between the allocator 16 and the adapters 12

In order to have reliable and comparable time stamps for the frames received, it is desired to have synchronized clocks in the adapters 12 and the allocator 16.

Clock phase synchronization is presently obtained by forwarding, with the data transferred from the allocator 16 to the transfer circuits 30, a clock signal which is encoded in the data transferred but recoverable as is usual in the art. The adapters 12 are adapted to derive this clock signal and use it both in the transfer circuit 30 and the request circuit 28, as illustrated in figure 3.

Having synchronized the phases, the actual clock time is synchronized by determining a transmission delay between the allocator 16 and the relevant adapter 12.

This transmission delay may be determined by transmitting either from the adapter 12 or the allocator 16 a signal (while determining a point in time of transmission), which the other of the adapter and the allocator 16 returns, where the point in time of receipt of this return signal is determined. The difference between the point in time of receipt and the point in time of transmission then forms the basis for a determination of the delay, such as by dividing this time difference in two. Naturally, a processing time in the other of the adapter and the allocator may be subtracted if desired. Now, the allocator 16 transmits its actual point in time to the adapter 12 which then adapts its time to the clock time of the allocator 16 added the determined transmission delay. If the points in time of transmission and receipt are determined by the allocator 16, also these points in time or the transmission delay for this adapter 12, if determined by the allocator 16, may be forwarded to the adapter 12.

Preferably, the other of the allocator and the adapter immediately transmits the return signal or message, so that any processing delay in this adapter/allocator may be negligible.

Alternatively, this delay may be determined or assumed. The contents of the

instructions/signals/messages are not important.

Naturally, different time delays may exist between the allocator 16 and different adapters 12.

Step 2 is the transmission from the allocator 16 to the adapter 12 of an instruction to set the local adapter time to a value being the present local time of the allocator 16 added the determined time delay. Thus, when the adapter 12 receives this instruction, it will set its local time to the time which the local time at the allocator 16 in the meantime has advanced to. Then, the clock times of the allocator 16 and the adapter 12 is synchronized to within a clock cycle of the clock signal. As the phases or clock pulses are also synchronized, the clocks will remain synchronized.

This recovered clock is then also used for time stamping the data packets received. Thus, all time stamps are synchronized to within a clock cycle.

As a number of instructions may be pending between the allocator 16 and any of the adapters 12, an identifier is provided in each instruction/request. Presently, the identifier is a time stamp between 0 and 7 (3 bits) which is shifted and wrapped around in synchronism with the clock. Thus, the allocator 16, when sending an instruction, will add the time stamp, and the adapter 12, when replying to that instruction, will copy the time stamp into the reply, so that the allocator 16 is able to determine to which instruction the reply relates.

Naturally, the present synchronization of the adapter 12 to the allocator 16 may be performed for any number of adapters 12. The adapters 12 may be connected to the allocator 16 in a star configuration in which all adapters 12 communicate directly with the allocator 16, in a ring topology, or in a daisy chain configuration having the allocator 16 at an end of a string of adapters 12 which then communicate with the allocator through one or more other adapters 12. Operation of the allocator 16 For each of the queues of the storage 18, the allocator 16 has two queues (see figure 4) : a RIFO (Random In First Out) and a FIRO (First In Random Out) queue.

The FIRO queue holds the pending requests from all adapters 12 and relating to the pertaining queue of the storage 18. A Write pointer points to the next free position of the FIRO queue. A request received from an adapter 12 is received and provided in this position.

The RIFO queue holds information relating to when frames for the storage queue are to be output as well as an order thereof. Each entry in the RIFO queue relates to a point in time of the clock, and a read pointer points to the present point in time of the RIFO queue.

When a request is received, the time stamp thereof is derived, and an identifier is provided in the RIFO queue at the corresponding position or point in time. It is noted that this position or point in time may be sooner than other frames for the same storage queue due to the fact that information from some adapters 12 or the processing in such adapters 12 may take longer than from/in others.

In figure 4, it is seen that the first frame in the FIRO queue has a later transmission time that the next frame.

The Read pointer of the RIFO queue advances once per clock cycle, and if an identifier is seen at the new position of the Read pointer, the corresponding position of the FIRO queue is addressed and a transmission instruction is transmitted to the pertaining adapter 12. Then, the corresponding entry of the FIRO queue is removed (or an end pointer is advanced to this position).

Naturally, the FIRO and RIFO queues may be implemented as circular queues.

In order to take into account any time delays caused by e.g. data transmission between the adapters 12 and the allocator 16 as well as processing times in the adapters 12, the Read pointer preferably relates to a point in time delayed in relation to the actual point in time as defined by the synchronized clocks and which is used for providing the time stamps of the frames (as is also forwarded in the requests stored in the FIRO). In this regard, when the entry is provided at the correct position in the RIFO queue, the time stamp of the relevant request is no longer needed and is discarded in order to not take up space in the tables.

Thus, the time of the Read pointer may be several, such as 3, 4, 5, 6, 7, 8, 9, 10 or more clock cycles behind the real clock. Then, a frame time stamped at e.g. time 120 may be forwarded to the FIRO queue and entered into the RIFO queue at time 120, which is addressed (Read pointer advanced to that position) at time 130.

At all times and for each queue in the storage 18, the allocator 16 has two pointers, a Write pointer identifying the next address at which a next frame from an adapter 12 is to be stored, and a Read pointer identifying the address of the next stored frame of this queue to be de-queued for further analysis, forwarding or the like. When a new frame is to be stored, the Write address is forwarded, i.e. the next virtual address is converted into its physical address which is forwarded, to the pertaining transfer circuit 30, which then facilitates storing of the frame. At the same time, the allocator 16 increases the pertaining Write pointer with a value corresponding to the size of the frame.

In the situation where one or more of the queues hold frames for further analysis of e.g. a processor, the number of frames in such a queue, or the fill level of the queue, will illustrate how busy this processor is. This is simply determined by the difference in addresses between the Write pointer and the Read pointer of the queue, when virtual addresses are used. The de-queuing of frames from the storage 18 may be facilitated by any apparatus or process/processor, such as one connected to the storage. De-queuing a frame from the storage 18 causes this apparatus/process/processor to alter the Read pointer of this queue correspondingly.

In general, adding frames to the storage 18 makes the allocator 16 alter the write pointers, and de-queuing frames makes the processes/processors alter the read pointers. Naturally, it is desired that this information is exchanged. Several methods and schemes exist.

In one situation, it is desired to not exchange this data too often in order to preserve bandwidth on the DMA bus for the data packet exchange. In this situation, the mirroring or synchronizing is initiated by the allocator 16. Each time a data packet is written in the storage 18, the allocator 16 may update the write pointer, whereby the (number of data frames or the fill level of) individual queues will seem, to the allocator 16, to grow, as the read pointers are not updated.

Naturally, updated write pointers may be exchanged once in a while, but this is preferred to not update these, until a size of a queue exceeds a predetermined limit. At this point, the allocator 16 will update the read pointers from the storage 18 or the

process(es)/processor(s) in order to obtain updated data on the actual sizes of the queues and thus of how busy the process(es)/processor(s) is/are. In one situation, the process(es)/processor(s) may, at the same time, receive updated write pointers. In this manner, the process(es)/processor(s) may starve, if they empty all queues before information that additional packets have been stored and are ready for analysis/dequeuing. This may be avoided by updating the write pointers at the processes/processors or in the storage 18, when updating them in the allocator 18. Then, the processes/processors have updated queue information and keep operating, as long as data packets are present.

Alternatively, the updating also of the read pointers may be more frequent, in order to keep the allocator 16 and the process(es)/processor(s) better "informed". This synchronization of the Write/Read pointers could be performed when the bus 32 is not busy, or e.g. when a maximum delay has passed since the last synchronization.

Naturally, the queues or storage 18 may be circular, and a particular space may be allocated to a queue if desired.

Naturally, if an adapter 12 back to back receives multiple data frames which relate to the same stream, the request circuit 28 will transmit a number of requests which the allocator 16 then will provide at the relevant positions in the RIFO queue. If the relevant adapter 12 is identified in each entry in the RIFO queue, the allocator 16 may identify multiple,

neighbouring entries in the RIFO which relate to the same adapter 12, and thus only revert to this adapters 12 transfer circuit 30 with one transmission identifying not only the queue (address data) but also the number of packets to be forwarded on the basis of this simple request.

Transmission of data from the storage 18 via an adapter 12

Naturally, data packets stored in one or more queues in the storage 18 may be de-queued, transmitted over the bus 32 and output via an adapter 12. As is the case when storing the data packets stored in the storage 18, this may be performed via DMA, whereby the adapter 12 directly reads the data packets in the storage 18 without intervention from e.g. a processor at the storage 18.

The scheme of de-queuing packets is as that described above for storing packets in the storage 18:

Data packets from a number of queues in the storage 18 may be output via the same adapter 12. These may be arbitrated using any desired scheme, such as round robin, priority or any other prioritization. In the adapter 12, any number of Tx ports or FIFOs may be provided for different flows, queues, priorities or the like, and packets from these may be output via a single PHY or via different PHYs.

In one situation, read/write pointers of a queue are stored in the storage 18 as is the case when storing data in the storage 18. In the same manner, the adapter 12 may mirror the read/write pointers and keep de-queuing data from the queue as long as data seems to be present. Mirroring may, as described above, take place at fixed maximum time intervals, when a queue seems to be too full or too empty, or the like.

The processes/processor may keep track of the Read and Write pointers and, as described above, determine whether the adapter 12 is so busy that data packets for the pertaining queue(s) should be forwarded to another queue and another adapter 12.

In another situation, a processor or process may define which data packets or addresses should be output via an adapter 12 and may forward an indication of such addresses to the adapter 12.

One manner is for the process or processor to copy such packets into a particular queue de- queued by the adapter using a particular set of read/write pointers updated by the process/processor and which is mirrored on to the adapter 12.

Another manner focuses on not copying data packets. In this situation, the data packets are maintained in the original queue, but another set of read/write pointers may be provided for use with the de-queuing of data packets. In fact, a single additional pointer is required, if the original read/write pointers of the queue are maintained. The additional pointer indicates where, in the queue, the process/processor has come to in the analysis and, thus, which of the addresses between the read and write pointer may be de-queued. This additional pointer is maintained by the processor/process and forwarded to or read by the adapter using e.g. DMA, and the pertaining adapter informs the processor/process or the controlling circuit 16, when an address has been de-queued.

Claims

1. An apparatus for receiving and forwarding data packets, the apparatus comprising a controlling unit and a plurality of physically separate data receiving elements, the controlling unit comprising : - a controller clock holding a controller time and being adapted to periodically increase or decrease the controller time, the controller clock being controllable by a periodic signal, means for outputting second information based on the periodic signal, each data receiving element comprising : first means for receiving or accessing a data packet, second means for receiving second information output by the controlling unit and deriving a periodic signal therefrom, means for determining a first point in time of receipt/access of the data packet, the determining means comprising a local clock, the local clock holding a local time and being adapted to periodically increase or decrease the local time, the local clock being controllable by the derived periodic signal, third means for outputting first information comprising the point in time, fourth means for outputting third information to the controlling unit based on the derived periodic signal, the outputting means of the controlling unit being adapted to output, as the second information, a second point in time, the data receiving elements each comprising means for setting the pertaining local time to the second point in time, received by the second receiving means, added a transmission delay determined by - the controlling unit transmitting a first signal to the second means of the data receiving element and logging a local point in time of transmittal of the first signal, the controlling unit receiving a signal from the fourth means of the data receiving element and logging a local time of receipt, and determining the transmission delay from the time of transmission and the time of receipt, or the data receiving element transmitting, from the fourth means thereof, a third signal to the controlling unit and logging a local point in time of transmittal of the third signal and the second means of the data receiving element receiving a fourth signal from the controlling unit and logging a local time of receipt and determining the transmission delay from the time of transmission and the time of receipt.

2. An apparatus according to claim 1, wherein : the data receiving elements further com means for receiving an address for storing at least part of the data packet, and means for facilitating storage of the at least part of the data packet at the address, the controlling unit or another unit comprising : means for receiving the first information and means for, for each piece of first information received, determining an address and returning the address to the receiving means of the pertaining data receiving element.

3. An assembly comprising an apparatus according to any of claims 1 and 2 and a storage comprising a plurality of addresses at which data may be stored, the facilitating means being adapted to store the at least parts of the data packet at the received address in the storage.

4. A method of operating an apparatus according to claim 1, the method comprising : each data receiving element: receiving or accessing a data packet, determining, from the local clock, a first point in time of receipt/access of the data packet, outputting first information comprising the first point in time, the controlling unit forwarding, to the receiving elements, the second information comprising a second point in time and being based on the periodic signal, the data receiving element: receiving the second information, deriving the periodic signal and the second point in time, periodically increasing/decreasing the local time on the basis of the derived periodic signal, outputting third information based on the derived periodic signal, setting the receiver time to the derived second point in time added a delay determined by: the controlling unit transmitting a first signal to the second means of the data receiving element and logging a local point in time of transmittal of the first signal, the second means of the data receiving element receiving the first signal and the fourth means of the data receiving element outputting a second signal, the controlling unit receiving the second signal from the fourth means of the data receiving element and logging a local time of receipt, and determining the transmission delay from the time of transmission and the time of receipt, and or the data receiving element transmitting, from the fourth means thereof, a third signal to the controlling unit and logging a local point in time of transmittal of the third signal, the controlling unit receiving the third signal and outputting a fourth signal to the second means of the data receiving element, the second means of the data receiving element receiving the fourth signal from the controlling unit and logging a local time of receipt and determining the transmission delay from the time of transmission and the time of receipt.

5. A method according to claim 4, wherein : the receiving elements further: receive an address for storing at least part of the data packet, and facilitate storage of the at least part of the data packet at the address, the controlling unit or another unit: receives the first information and for each piece of first information received, determines an address and returns the address to the receiving means of the pertaining data receiving element.

6. A method according to any of claims 4 and 5, wherein the facilitating step comprises storing the at least part of the data packet at the received address in a storage comprising a plurality of addresses at which data may be stored.