WO2012013061A1

WO2012013061A1 - Fuse structure and method for forming the same

Info

Publication number: WO2012013061A1
Application number: PCT/CN2011/073850
Authority: WO
Inventors: 毛剑宏
Original assignee: 上海丽恒光微电子科技有限公司
Priority date: 2010-07-30
Filing date: 2011-05-10
Publication date: 2012-02-02
Also published as: CN102347269B; CN102347269A

Abstract

A fuse structure and a method for forming the same are provided. The method comprises the following steps: providing a semiconductor substrate (20) with a circuit structure formed on the semiconductor substrate (20) and a metal interconnection layer (22) formed on the circuit structure; and forming a fuse (33') on the metal interconnection layer (22) with an interconnection structure formed between the fuse (33') and the metal interconnection layer (22), wherein the fuse material is selected from polycrystalline germanium-silicon, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium-silicon. Because the material of polycrystalline germanium-silicon, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium-silicon has a high resistance, the required fusing current is low and the circuit structure can not be easily damaged. The chip area is reduced because the fuse structure is stacked on the metal interconnection layer.

Description

Fuse structure and method of forming fuse structure

The present application claims priority to Chinese Patent Application No. 2010 1024 419 7.5, entitled "Fuse Structure and Method of Forming a Fuse Structure", filed on July 30, 2010, the entire contents of which are incorporated herein by reference. In this application.

Technical field

The present invention relates to the field of semiconductor technology, and in particular, to a method of forming a fuse structure.

Background technique

Semiconductor integrated circuits include fuse structures that are typically used in both circuit repair and memory output logic values. In the circuit repair, when the circuit is repaired, the fuse connected to the faulty circuit is blown, the faulty circuit structure is unavailable, and the faulty circuit is replaced with a redundant circuit. In terms of changing the output logic value of the memory, the logic value of the output is determined by the blown or not blown fuse.

There are several common fuse structures in the prior art. In the first fuse structure, the metal interconnection of the metal interconnection layer is directly used as a fuse, and when the circuit is repaired, the fuse is cut by the laser, so that the cost is high. The second fuse structure is one time programm (OTP), multiple time programm (ΜΤΡ) or electrically erasable programmable read-only memory (EEPROM). The fuse structure used in this type, the fuse structure and the OTP/MTP/EEPROM device are not stacked, which wastes the chip area, and the process is complicated, resulting in high cost. The third fuse structure is a polysilicon fuse structure, which uses a polysilicon gate in a CMOS (Complementary Metal Oxide Semiconductor) process as a fuse. Since the resistance of the polysilicon is large, the fuse current is small, and the fuse is not The related circuit structure is destroyed, but it occupies the COMS area, thus increasing the manufacturing cost of the semiconductor device.

There are a number of patents relating to fuses in the prior art, such as the fuses disclosed in Chinese Patent Application No. 200480011464 and the method of forming the same, and the semiconductor fuses disclosed in Chinese Patent Application No. 99108915. However, none of the disadvantages of the prior art described above have been solved.

Summary of the invention

The problem to be solved by the present invention is to provide a method for forming a fuse structure, which is performed in a CMOS back process, and the formed fuse structure is superimposed with a CMOS circuit, thereby saving chip area and reducing Cost; and, the process is single.

In order to solve the above problems, the present invention provides a method of forming a fuse structure, comprising: providing a semiconductor substrate on which a circuit structure is formed, on which a metal interconnection layer is formed;

Forming a fuse on the metal interconnect layer and an interconnect structure of the fuse and the metal interconnect layer, the fuse material being selected from the group consisting of polymorphic silicon, polycrystalline germanium, amorphous silicon, amorphous germanium or Amorphous silicon germanium.

Optionally, the forming an interconnect structure of the fuse fuse and the metal interconnect layer on the metal interconnect layer comprises:

Forming a first dielectric layer on the metal interconnect layer;

Forming a first plug in the first dielectric layer, the bottom of the first plug being in contact with an interconnection of the metal interconnect layer;

Forming a fuse layer on the first dielectric layer and the first plug, the material of the fuse layer being selected from the polymorphic silicon, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium;

Graphically forming the fuse layer to form a fuse, the fuse being in contact with the first plug;

Forming a second dielectric layer on the fuse and the first dielectric layer;

Forming a second plug in the first dielectric layer and the second dielectric layer, the second plug bottom being in contact with the interconnection of the metal interconnect layer;

A pad and an interconnect are formed on the second plug.

Optionally, the forming a fuse on the metal interconnect layer and the interconnect structure of the fuse and the metal interconnect layer include:

Forming a first dielectric layer on the metal interconnect layer;

Forming a first through hole in the first dielectric layer;

Depositing the fuse material, forming a first plug in the first via hole, forming a fuse layer on the first dielectric layer, and interconnecting the bottom of the first plug and the metal interconnect layer Contact

Forming a second dielectric layer on the fuse and the first dielectric layer;

Forming a second via hole in the first dielectric layer and the second dielectric layer, and forming a trench and an opening in the second dielectric layer;

Filling the second via, the trench, and the opening respectively form a second plug, an interconnect connecting the second plug, and a pad, the bottom of the second plug being in contact with the interconnect of the metal interconnect layer. Optionally, the forming a fuse on the metal interconnect layer and the interconnect structure of the fuse and the metal interconnect layer include:

Forming a first dielectric layer on the metal interconnect layer;

Forming a fuse layer on the first dielectric layer, the material of the fuse layer being selected from the polysilicon, polysilicon, amorphous silicon, amorphous germanium or amorphous silicon;

Graphically forming the fuse layer to form a fuse;

Forming a second dielectric layer on the fuse and the first dielectric layer;

Forming a first plug in the first dielectric layer, the bottom of the first plug is in contact with the fuse, and forming a second plug in the first dielectric layer and the second dielectric layer, the bottom of the second plug is The interconnect of the metal interconnect layer is in contact;

An interconnect line and a pad are formed on the second dielectric layer to connect the first plug and the second plug.

Forming a first dielectric layer on the metal interconnect layer;

Graphically forming the polymorphic silicon layer, the polymorph layer, the amorphous silicon layer, the amorphous stagger layer or the amorphous silicon layer to form a fuse;

Forming a second dielectric layer on the fuse and the first dielectric layer;

Forming a first via hole in the first dielectric layer, forming a second via hole in the first dielectric layer and the second dielectric layer, and forming a trench and an opening in the second dielectric layer;

Filling the first through hole, the second through hole, the groove, and the opening to form a first plug, a second plug, an interconnection, and a pad, respectively, the first plug bottom is in contact with the fuse, and the second plug A bottom is in contact with an interconnect of the metal interconnect layer, the interconnect and a pad connecting the first plug and the second plug.

Optionally, the method further includes: forming an opening on the second dielectric layer to expose the fuse. Optionally, the first dielectric layer and the second dielectric layer are silicon dioxide, silicon carbide, silicon nitride, silicon oxynitride or a combination thereof.

Optionally, the interconnect and the pad are an aluminum interconnect and an aluminum pad, the first plug, the first The second plug is a tungsten plug.

Optionally, the interconnect and the pad are copper interconnects and a bra, and the second plug is a copper plug.

Optionally, the interconnect and the pad are copper interconnects and a bra, and the first plug and the second plug are copper plugs.

The present invention also provides a fuse structure formed by the above method.

Compared with the prior art, the present invention has the following advantages:

A polycrystalline silicon fuse, a polysilicon fuse, an amorphous silicon fuse, an amorphous germanium fuse, or an amorphous germanium silicon fuse may be formed on the metal interconnect layer after forming the circuit structure and the metal interconnect layer. And an interconnection structure of the fuse and the metal interconnection layer. Due to the high resistance value of polycrystalline silicon, polycrystalline germanium, amorphous silicon, amorphous amorphous, and amorphous silicon, the polycrystalline silicon fuse, the polycrystalline silicon fuse, the amorphous silicon fuse, and the amorphous When a fuse or an amorphous silicon fuse is used, the required fuse current is small, and the related circuit structure is not damaged; Moreover, the fuse structure formed by the method is stacked on the metal interconnection layer, and does not occupy the chip area, so Save chip area and reduce manufacturing cost; and it forms a process sheet.

DRAWINGS

1 is a flow chart of forming a fuse structure of the present invention;

2 is a schematic cross-sectional structural view of a substrate provided by the present invention;

3a to 3i are schematic cross-sectional structural views showing a fuse structure according to a first embodiment of the present invention; and Figs. 4a to 4f are schematic cross-sectional views showing a fuse structure according to a second embodiment of the present invention; Figs. 5a to 5g are FIG. 6 is a schematic cross-sectional view showing the formation of a fuse structure according to a fourth embodiment of the present invention. FIG.

detailed description

In the prior art, there is a fuse structure using polysilicon as a fuse. However, since the deposition temperature of polysilicon is above 600 ° C, it must be formed before the CMOS back-end process, and in parallel with the CMOS circuit, so the fuse The structure will occupy the area of the chip and increase the cost. The inventors have repeatedly studied, and hope to find a fuse structure that can be formed on a CMOS circuit after the CMOS back-end process without occupying the chip area.

In a method of forming a fuse structure according to a specific embodiment of the present invention, after forming a circuit structure and a metal interconnection layer, a fuse and an interconnection structure of a multi-fuse and a metal interconnection layer are formed on the metal interconnection layer.

In order to enable those skilled in the art to better understand the spirit of the present invention, detailed description will be made with reference to the accompanying drawings. A method of forming a fuse structure in accordance with an embodiment of the present invention.

1 is a flow chart of forming a fuse structure according to the present invention. Referring to FIG. 1, a method for forming a fuse structure according to an embodiment of the present invention includes:

Step S1, providing a semiconductor substrate on which a circuit structure is formed, and a metal interconnection layer is formed on the circuit structure;

Step S2, forming a fuse on the metal interconnection layer and an interconnection structure of the fuse and the metal interconnection layer, wherein the material of the fuse is selected from the group consisting of polysilicon, polysilicon, amorphous silicon, Amorphous germanium or amorphous germanium silicon. law.

Referring to FIG. 1 and FIG. 2, step S1 is performed to provide a semiconductor substrate 20 on which a circuit structure is formed, on which a metal interconnection layer is formed: the semiconductor substrate 20 may It is monocrystalline silicon or silicon wrong; it can also be silicon-on-insulator (SOI); or it can also include other materials such as III-V compounds such as gallium arsenide. The semiconductor substrate 20 has a certain isolation structure, which may be shallow trench isolation (STI) or local field oxide isolation (LOCOS). A device layer 21 is formed on the semiconductor substrate, and a circuit structure is formed in the device layer 21. The specific circuit structure is not shown in the drawing. The circuit structure may be various CMOS circuit structures, such as EEPROM. Memory circuit structure. A metal interconnection layer 22 is formed on the device layer 21, and two interconnection lines 221, 222 are illustrated, which are merely illustrative, and the layout of the interconnection lines differs depending on the actual circuit configuration. The fuse structure of the present invention is performed at a back end of the semiconductor process, and the formed fuse is connected to an interconnection line in the metal interconnection layer, and is connected to the associated circuit structure through the interconnection line. The circuit structure and the improvement of the metal interconnection are not involved in the present invention, and the circuit structure and the metal interconnection in the present invention are common circuit structures and metal interconnection lines in the art, and will not be detailed here. Description.

After step S1 is performed, step S2 is performed to form a fuse on the metal interconnection layer and an interconnection structure of the fuse and the metal interconnection layer. In the first embodiment of the present invention, the forming a fuse on the metal interconnect layer and the interconnect structure of the fuse and the metal interconnect layer include:

Step S31, forming a first dielectric layer on the metal interconnect layer;

Step S32, forming a first plug in the first dielectric layer, the bottom of the first plug is in contact with the metal interconnection layer; Step S33, forming a fuse layer on the first dielectric layer and the first plug, wherein the material of the fuse layer is selected from the group consisting of polysilicon, polysilicon, amorphous silicon, amorphous germanium or amorphous Wrong silicon

Step S34, the fuse layer is patterned to form a fuse, the fuse is in contact with the first plug; Step S35, forming a second dielectric layer on the fuse and the first dielectric layer;

Step S36, forming a second plug in the first dielectric layer and the second dielectric layer, the bottom of the second plug contacting the metal interconnection layer;

Step S37, forming a pad and an interconnection on the second plug.

3a to 3h are schematic cross-sectional views showing the formation of a fuse structure according to a first embodiment of the present invention, and a method of forming a fuse structure of the first embodiment is described in detail in conjunction with Figs. 3a to 3h.

Referring to FIG. 3a, step S31 is performed to form a first dielectric layer 31 on the metal interconnect layer 22, and depositing a first dielectric layer 31 on the metal interconnect layer 22 by chemical vapor deposition, the first dielectric layer In other embodiments, the first dielectric layer may also be another dielectric layer that functions as an insulating barrier, such as silicon carbide, silicon nitride, silicon oxynitride, or silicon dioxide, silicon carbide, or nitrogen. Any combination of silicon and silicon oxynitride.

Referring to FIG. 3b, step S32 is performed to form a first plug 32 in the first dielectric layer 31. The bottom of the first plug 32 is in contact with the metal interconnect layer. The specific method for forming the first plug 32 is as follows: The first dielectric layer 31 is patterned by a etch and etch process to form a via, and the via is filled with metal to form a first plug 32. In this embodiment, the filled metal is tungsten and the first plug 32 is a tungsten plug. . This process of forming the first plug 32 is well known to those skilled in the art and will not be described in detail.

Referring to FIG. 3c, step S33 is performed to form a fuse layer 33 on the first dielectric layer 31 and the first plug 32. The material of the fuse layer is selected from the group consisting of polysilicon, polysilicon, and amorphous. Silicon, amorphous germanium or amorphous silicon, the fuse layer 33 has a thickness of 500 Å to 8000 Å, and the specific forming method is chemical phase deposition CVD in the field of semiconductor technology, such as PECVD, LPCVD, deposition temperature is 150 ° C~ 500 ° C.

Step S34, patterning the fuse layer 33 to form a fuse 33', a fuse 33' and the first plug

32 contact, referring to Fig. 3d, in this embodiment, the fuse layer is patterned by a photolithography, etching process to form a fuse 33'.

Referring to FIG. 3e, step S35 is performed, a second dielectric layer 34 is formed on the fuse 33' and the first dielectric layer 31, and a second is formed on the fuse 33' and the first dielectric layer 31 by chemical vapor deposition. The dielectric layer 34 is a silicon dioxide layer. In other embodiments, the second dielectric layer is also It is considered that other dielectric layers for insulating isolation, such as silicon carbide, silicon nitride, silicon oxynitride, may also be any combination of silicon dioxide, silicon carbide, silicon nitride, and silicon oxynitride.

Referring to FIG. 3f, step S36 is performed to form a second plug 35 in the first dielectric layer 31 and the second dielectric layer 34. The bottom of the second plug 35 and the interconnect 221 in the metal interconnect layer 22, The specific method of forming the second plug 35 is: forming a through hole in the first dielectric layer 31 and the second dielectric layer 34 by patterning the first dielectric layer 31 and the second dielectric layer 34 by a photolithography and etching process. The metal is filled in the via hole to form a second plug 35. In this embodiment, the filled metal is tungsten and the second plug 35 is a tungsten plug. This process of forming the second plug 35 is well known to those skilled in the art and will not be described in detail.

Referring to FIG. 3g, 3h, step S37 is performed, and a pad 37 and an interconnection line (not shown) are formed on the second plug 35, specifically: first formed in the second dielectric layer 34 and the second plug 35. A metal layer 36 is formed on the surface (refer to FIG. 3g). In this embodiment, the metal layer 36 is an aluminum (A1) layer, and the metal layer 36 is patterned by photolithography and etching processes to form a pad 37 (refer to Figure 3h) and the interconnect (not shown), refer to Figure 3h. The number of the second plugs 35 may be plural, wherein some of the second plugs 35 are connected to the bonding pads 37, and some of the second plugs 35 are connected to the interconnecting wires, and two of the two are schematically connected to the bonding pads 37. The second plug 35.

After the above steps are completed, the fuse structure of the first embodiment of the present invention has been formed, and then the fuse 33' needs to be exposed, so that when the fuse is blown, the molten metal can be evaporated without remaining on the chip. on. If the molten metal does not evaporate, the metal will likely reconnect after cooling, even if it is not connected together, and will remain in the chip, which will affect the performance of the chip.

Referring to FIG. 3i, after the fuse structure is formed, an opening 38 is formed on the second dielectric layer 34 by photolithography and plasma etching, and the fuse 33' is exposed, and a part of the fuse may be exposed, and all of the fuse may be exposed. wire.

Referring to FIG. 3i, a fuse structure stack of a first embodiment of the present invention is formed on a metal interconnection layer 22, the fuse structure including: a fuse 33', an interconnection structure of the fuse and the metal interconnection layer. Wherein, the interconnect structure comprises: a first plug 32 connecting the fuse 33' with the interconnect lines 221, 222 in the metal interconnect layer 22, interconnect lines and pads 37, interconnect lines and pads 37 A second plug 35 is connected to the interconnects 221, 222 in the metal interconnect layer 22.

In a second embodiment of the present invention, the forming a fuse on the metal interconnect layer and the interconnect structure of the fuse and the metal interconnect layer include: Step S41, forming a first dielectric layer on the metal interconnect layer;

Step S42, forming a first through hole in the first dielectric layer;

Step S43, depositing the fuse material, forming a first plug in the first through hole, forming a fuse layer on the first dielectric layer, and the bottom of the first plug and the metal interconnect layer Interconnect contact;

Step S44, the multi-fuse layer is patterned to form a fuse, the fuse is in contact with the first plug; step S45, forming a second dielectric layer on the fuse and the first dielectric layer;

Step S46, forming a second via hole in the first dielectric layer and the second dielectric layer, and forming a trench and an opening in the second dielectric layer;

Step S47, filling the second via hole, the trench and the opening respectively to form a second plug, an interconnect connecting the second plug, and a pad, and the bottom of the second plug is interconnected with the metal interconnect layer Line contact.

4a-4f are schematic cross-sectional views showing the formation of a fuse structure according to a second embodiment of the present invention, and a method of forming a fuse structure of the second embodiment is described in detail in conjunction with Figs. 4a to 4f.

Referring to FIG. 4a, step S41 is performed to form a first dielectric layer 41 on the metal interconnect layer 22, and depositing a first dielectric layer 41 on the metal interconnect layer 22 by chemical vapor deposition, the first dielectric layer In other embodiments, the first dielectric layer may also be another dielectric layer that functions as an insulating barrier, such as silicon carbide, silicon nitride, silicon oxynitride, or silicon dioxide, silicon carbide, or nitrogen. Any combination of silicon and silicon oxynitride.

After performing step S41, referring to FIG. 4b, performing step S42, forming a first via hole in the first dielectric layer 41; then performing step S43, depositing the fuse material, forming in the first via hole The first plug 42 forms a fuse layer 43 on the first dielectric layer 41, and the bottom of the first plug 42 is in contact with the interconnection lines 221, 222 of the metal interconnection layer. In the second embodiment, after the first via hole is formed, the fuse material is deposited by chemical phase deposition CVD, such as PECVD, LPCVD, deposition temperature in the range of 150 ° C to 500 ° C, and the fuse material is filled. a first plug 42 is formed in the first through hole, and a fuse layer 43 having a thickness of 500 Å to 8000 Å is formed on the first dielectric layer 41, and the fuse material is polycrystalline. Silicon germanium, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous silicon. In the second embodiment, the first plug 42 is a polycrystalline silicon, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous silicon plug.

After forming the fuse layer 43, referring to FIG. 4c, performing step S44, patterning the fuse layer 43 to form Fuse 43'. The fuse 43 is patterned by a photolithography, etching process to form a fuse 43'.

After the fuse 43' is formed, referring to Fig. 4d, step S45 is performed to form a second dielectric layer 44 on the fuse 43' and the first dielectric layer 41. A second dielectric layer 44 is formed on the fuse 43' and the first dielectric layer 41 by chemical vapor deposition. The second dielectric layer 44 is silicon dioxide. In other embodiments, the second dielectric layer may also be Other dielectric layers for insulating isolation, such as silicon carbide, silicon nitride, silicon oxynitride, may also be any combination of silicon dioxide, silicon carbide, silicon nitride, silicon oxynitride.

Thereafter, referring to FIG. 4e, step S46 is performed to form a second via hole in the first dielectric layer and the second dielectric layer, and a trench and an opening (not shown) are formed in the second dielectric layer; Step S47, filling the second via hole, the trench and the opening respectively to form a second plug 45, an interconnection line (not shown), and a pad 47, the bottom of the second plug 45 being interconnected with the metal The interconnects of the layers are in contact with each other, and the second vias are correspondingly formed with a second plug, and the trenches are correspondingly formed with interconnect lines, and the openings correspondingly form solder pads. In the second embodiment, a second plug 45, an interconnect (not shown), and a pad 47 are formed using a copper (Cu) process, a dual damascene process well known to those skilled in the art, and the second plug 45 is The copper plug, the pad 47 is a copper pad, and the interconnect is a copper interconnect (not shown). The number of the second plugs 45 is plural, wherein some of the second plugs 45 are connected to the pads 47, and some of the second plugs 45 are connected to the interconnecting wires. Two of the figures are shown schematically connected to the pads 47. The second plug 45.

After the above steps are completed, the fuse structure of the second embodiment of the present invention has been formed, and then the fuse 43' needs to be exposed, so that when the fuse is blown, the molten metal can be evaporated without remaining on the chip. on. If the molten metal does not evaporate, the metal will likely reconnect after cooling, even if it is not connected together, and will remain in the chip, which will affect the performance of the chip.

Referring to FIG. 4f, after the fuse structure is formed, an opening 48 is formed on the second dielectric layer 44 by photolithography and a plasma etching process, and the fuse 43' is exposed, and a part of the fuse may be exposed, and all of the fuse may be exposed. wire.

Referring to FIG. 4f, the fuse structure stack of the second embodiment of the present invention is formed on the metal interconnection layer 22, which is substantially the same as the fuse structure of the first embodiment. The pad 47 and the second plug 45 are of a unitary structure only due to the difference in the forming process.

In a third embodiment of the present invention, the forming a fuse on the metal interconnect layer and the interconnect structure of the fuse and the metal interconnect layer include:

Step S51, forming a first dielectric layer on the metal interconnect layer;

Step S52, forming a fuse layer on the first dielectric layer, the material of the fuse layer is selected from the Polycrystalline silicon, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous silicon;

Step S53, patterning the fuse layer to form a fuse;

Step S54, forming a second dielectric layer on the fuse and the first dielectric layer;

Step S55, forming a first plug in the first dielectric layer, the bottom of the first plug is in contact with the fuse, and forming a second plug in the first dielectric layer and the second dielectric layer, the second The bottom of the plug is in contact with the metal interconnect layer;

Step S56, forming interconnection lines and pads on the second dielectric layer, connecting the first plug and the second plug.

5a to 5g are schematic cross-sectional views showing the formation of a fuse structure according to a third embodiment of the present invention, and a method of forming a fuse structure of the third embodiment will be described in detail in conjunction with Figs. 5a to 5g.

Referring to FIG. 5a, step S51 is performed to form a first dielectric layer 51 on the metal interconnect layer 22, specifically: depositing a first dielectric layer 51 on the metal interconnect layer 22 by chemical vapor deposition CVD. The first dielectric layer 51 is a silicon dioxide layer. In other embodiments, the first dielectric layer may also be another dielectric layer that functions as an insulating barrier, such as silicon carbide, silicon nitride, silicon oxynitride, or dioxide. Any combination of silicon, silicon carbide, silicon nitride, silicon oxynitride.

Referring to FIG. 5b, step S52 is performed to form a fuse layer 52 on the first dielectric layer 51. The material of the fuse layer is selected from the group consisting of polycrystalline silicon, polycrystalline germanium, amorphous silicon, and amorphous germanium. Or amorphous silicon, which is formed by chemical vapor deposition CVD in the field of semiconductor technology, such as PECVD, LPCVD, deposition temperature in the range of 150 ° C ~ 500 ° C, deposition of thickness of 500 angstroms ~ 8000 angstroms of fuse Floor.

Referring to FIG. 5c, step S53 is performed to pattern the fuse layer 52 to form a fuse 52'. The fuse layer 52 is patterned by photolithography and etching to form a fuse 52'.

Referring to FIG. 5d, step S54 is performed to form a second dielectric layer 53 on the surface formed by the fuse 52' and the first dielectric layer 51, specifically: forming a second dielectric layer 53 by chemical vapor deposition CVD, the second The dielectric layer 53 is a silicon dioxide layer. In other embodiments, the second dielectric layer may also be another dielectric layer that functions as an insulating barrier, such as silicon carbide, silicon nitride, silicon oxynitride, or silicon dioxide. Any combination of silicon carbide, silicon nitride, silicon oxynitride.

Referring to FIG. 5e, step S55 is performed to form a first plug 54 in the first dielectric layer 51, the bottom of the first plug 54 is in contact with the fuse 52', in the first dielectric layer 51 and the second A second plug 55 is formed in the dielectric layer 53 , and an interconnection 222 between the bottom of the second plug 55 and the metal interconnection layer is The 221 contact is formed by: patterning the second dielectric layer 53 by a photolithography and etching process, forming a first via hole in the second dielectric layer 53; and patterning the photo by a photolithography and etching process The first dielectric layer 51 and the second dielectric layer 53 form a second through hole in the second dielectric layer 53 and the first dielectric layer 51, and the first through hole is filled with metal to form a first plug 54, and the bottom of the first plug 54 is The fuse 52' contacts, and the second via hole is filled with metal to form a second plug 55, and the second plug 55 is in contact with the interconnection lines 222, 221 in the metal interconnection layer. In this particular embodiment, the filled metal is tungsten and the first plug 54 and the second plug 55 are tungsten plugs.

Referring to FIG. 5f, step S56 is performed, an interconnection line (not shown) and a pad 57 are formed on the second dielectric layer 53, and the first plug 54 and the second plug 55 are connected. The specific forming method is Forming a metal layer on the second dielectric layer 53 by physical vapor deposition, the metal layer is an aluminum layer, and then etching the aluminum layer by photolithography and etching to form interconnect lines (not shown) and pads 57. The first plug 54 and the second plug 55 are connected. The number of the first plugs 54 and the second plugs 55 is plural, and the connection between the plurality of first plugs 54 and the second plugs 55 may be connected by pads 57 or interconnects (not shown), wherein Some first plugs 54 and second plugs 55 are connected by pads 57. Some first plugs 54 and second plugs 55 are connected by interconnecting wires. Only the first plug 54 and the second plug 55 are schematically shown in the drawing. Connected by a pad 57.

After the above steps are completed, the fuse structure of the third embodiment of the present invention has been formed, and then the fuse 52' needs to be exposed. Referring to FIG. 5g, after forming the fuse structure, the photolithography and plasma etching processes are used. The second dielectric layer 53 forms an opening 58 that exposes the fuse 52', which may expose a portion of the fuse and may also expose all of the fuse.

Referring to FIG. 5f, a fuse structure stack of a third embodiment of the present invention is formed on a metal interconnection layer 22, the fuse structure including: a fuse 52', an interconnection structure of the fuse and the metal interconnection layer. The interconnect structure includes: a first plug 54, a second plug 55, an interconnection line and a pad 57, the first plug 54 is connected to the fuse 52', and the second plug 55 is connected to the metal interconnect layer. The interconnects 221, 222 in 22 are connected, and the interconnects or pads 57 connect the first plug 54 and the second plug 55.

In a fourth embodiment of the present invention, the forming a fuse on the metal interconnect layer and the interconnect structure of the fuse and the metal interconnect layer include:

Step S61, forming a first dielectric layer on the metal interconnection layer;

Step S62, forming a fuse layer on the first dielectric layer, the material of the fuse layer is selected from the polysilicon, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous silicon; Step S63, patterning the fuse layer to form a fuse;

Step S64, forming a second dielectric layer on the fuse and the first dielectric layer;

Step S65, forming a first via hole in the first dielectric layer, forming a second via hole in the first dielectric layer and the second dielectric layer, and forming a trench and an opening in the second dielectric layer;

Step S66, filling the first through hole, the second through hole, the trench, and the opening to form a first plug, a second plug, an interconnection, and a pad, respectively, wherein the bottom of the first plug is in contact with the fuse, A second plug bottom is in contact with an interconnect of the metal interconnect layer, the interconnect and a pad connecting the first plug and the second plug.

6a-6c are schematic cross-sectional views showing the formation of a fuse structure according to a fourth embodiment of the present invention, and a method of forming a fuse structure of the fourth embodiment is described in detail in conjunction with Figs. 6a to 6c.

In the fourth embodiment, the step S61, the step S62, the step S63, and the step S64 are the same as the step S51, the step S52, the step S53, and the step S54 of the third embodiment, which are not described in detail. See the detailed description of the relevant steps in the third embodiment.

After the step S61, the step S62, the step S63, and the step S64 are performed to form the fuse 62', the second dielectric layer 63, and the first dielectric layer 61 (refer to FIG. 6a), referring to FIG. 6b, step S65 is performed. Forming a first through hole in the second dielectric layer 63, forming a second through hole in the first dielectric layer 61 and the second dielectric layer 63, forming a trench and an opening in the second dielectric layer (not shown) And step S66, filling the first through hole, the second through hole, the groove, and the opening to form a first plug 64, a second plug 65, an interconnection line, and a pad 67, respectively, the bottom of the first plug 64 In contact with the fuse 62', the bottom of the second plug 65 is in contact with the interconnecting lines 222, 221 of the metal interconnect layer, and the interconnect (not shown) and the pad 67 are connected to the first The first through hole correspondingly forms a first plug, the second through hole correspondingly forms a second plug, and the groove correspondingly forms an interconnecting wire, and the opening correspondingly forms a bonding pad. In the fourth embodiment, the first plug 64, the second plug 65, the interconnect (not shown), and the pad 67 are formed using a copper (Cu) process, that is, a dual damascene process well known to those skilled in the art. The first plug 64, the second plug 65 is a copper plug, the pad 67 is a copper pad, and the interconnect is a copper interconnect (not shown). The number of the first plug 64 and the second plug 65 is plural. The figure shows two first plugs 64, a second plug 65, and a plurality of first plugs 64 and a second plug 65. The connections are connected by pads 67 or interconnects (not shown), wherein some of the first plugs 64 and the second plugs 65 are connected by pads 67, and some of the first plugs 64 and the second plugs 65 are connected by interconnects. In the figure, only the first plug 64 and the second plug 65 are shown schematically connected by a bonding pad 67. After the above steps are completed, the fuse structure of the fourth embodiment of the present invention has been formed, and then the fuse 62' needs to be exposed, so that when the fuse is blown, the molten metal can be evaporated without remaining on the chip. on. If the molten metal does not evaporate, the metal will likely reconnect after cooling, even if it is not connected together, and will remain in the chip, which will affect the performance of the chip.

Referring to FIG. 6c, after the fuse structure is formed, an opening 68 is formed on the second dielectric layer 63 by using a photolithography/etching process and a plasma etching process, and the fuse 62' is exposed, and a part of the fuse may be exposed, or Expose all fuses.

Referring to Fig. 6c, a fuse structure stack of a fourth embodiment of the present invention is formed on the metal interconnection layer 22, which is substantially the same as the fuse structure of the third embodiment. The pad 67 is integral with the first plug 64 and the second plug 65 due to the difference in the forming process.

It should be noted that the fuse structure of the embodiment of the present invention is stacked on the metal interconnection layer, and the metal interconnection layer is not continuously formed on the fuse structure. In other embodiments, the fuse structure can continue to be stacked. Metal interconnect layer. In this case, the interconnect structure of the formed fuse and metal interconnect layer includes plugs and interconnect lines, excluding solder pads. Moreover, embodiments of the present invention expose the fuse from the opening. In other embodiments of the invention, the fuse may not be exposed but buried in the dielectric layer.

After forming the circuit structure and the metal interconnection layer, the present invention forms a polycrystalline silicon fuse, a polysilicon fuse, an amorphous silicon fuse, an amorphous germanium fuse or an amorphous silicon melt on the metal interconnect layer. Wire, fuse and metal interconnect layer interconnection structure. Due to the high resistance value of polycrystalline silicon, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous silicon, the polycrystalline silicon fuse, polycrystalline silicon fuse, amorphous silicon fuse, amorphous When the fuse or the amorphous silicon fuse is not damaged, the related circuit structure is not damaged, and the fuse structure formed by the method is stacked on the metal interconnection layer, which does not occupy the chip area, thereby saving chip area and reducing manufacturing cost. And it forms a process cartridge.

The present invention has been disclosed in the preferred embodiments as described above, but it is not intended to limit the invention, and the present invention may be utilized by the method and technical contents disclosed above without departing from the spirit and scope of the invention. The technical solutions make possible changes and modifications, and therefore, the scope of protection of the technical solutions of the present invention is not deviated from the present invention.

Claims

Rights request

A method of forming a fuse structure, comprising: providing a semiconductor substrate on which a circuit structure is formed, and a metal interconnection layer is formed on the circuit structure;

2. The method of forming a fuse structure according to claim 1, wherein the forming a fuse on the metal interconnection layer and the interconnection structure of the fuse and the metal interconnection layer comprises: Forming a first dielectric layer on the metal interconnect layer;

Forming a first plug in the first dielectric layer, the first plug bottom is in contact with an interconnection line of the metal interconnection layer; forming a fuse layer on the first dielectric layer and the first plug, The material of the fuse layer is selected from the group consisting of polycrystalline silicon, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium;

Graphically forming the fuse layer to form a fuse, the fuse being in contact with the first plug; forming a second dielectric layer on the fuse and the first dielectric layer; in the first dielectric layer and the second medium A second plug is formed in the layer, the second plug bottom is in contact with the interconnect of the metal interconnect layer; and a pad and an interconnect are formed on the second plug.

3. The method of forming a fuse structure according to claim 1, wherein the forming a fuse on the metal interconnection layer and the interconnection structure of the fuse and the metal interconnection layer comprises: Forming a first dielectric layer on the metal interconnect layer;

Forming a first through hole in the first dielectric layer;

Graphically forming the fuse layer to form a fuse, the fuse being in contact with the first plug; Forming a second dielectric layer on the fuse and the first dielectric layer; forming a second via hole in the first dielectric layer and the second dielectric layer, forming a trench and an opening in the second dielectric layer;

The second via, the trench, and the opening are filled to form a second plug, an interconnect connecting the second plug, and a pad, the bottom of the second plug being in contact with the interconnect of the metal interconnect layer.

4. The method of forming a fuse structure according to claim 1, wherein the forming a fuse on the metal interconnect layer and the interconnect structure of the fuse and the metal interconnect layer comprises:

Forming a first dielectric layer on the metal interconnect layer;

Graphically forming the fuse layer to form a fuse; forming a second dielectric layer on the fuse and the first dielectric layer; forming a first plug in the first dielectric layer, the first plug bottom and the a fuse contact, a second plug is formed in the first dielectric layer and the second dielectric layer, the bottom of the second plug is in contact with an interconnection line of the metal interconnection layer; and a mutual formation is formed on the second dielectric layer A wire and a bonding pad connect the first plug and the second plug.

5. The method of forming a fuse structure according to claim 1, wherein the forming a fuse on the metal interconnect layer and the interconnect structure of the fuse and the metal interconnect layer comprises:

Forming a first dielectric layer on the metal interconnect layer; forming a fuse layer on the first dielectric layer, the material of the fuse layer being selected from the polysilicon, polysilicon, amorphous silicon An amorphous germanium or amorphous silicon; patterning the fuse layer to form a fuse; forming a second dielectric layer on the fuse and the first dielectric layer; forming a first pass in the second dielectric layer a hole, a second through hole is formed in the first dielectric layer and the second dielectric layer, and a trench and an opening are formed in the second dielectric layer; Filling the first through hole, the second through hole, the groove, and the opening to form a first plug, a second plug, an interconnection, and a pad, respectively, the first plug bottom is in contact with the fuse, and the second plug A bottom is in contact with an interconnect of the metal interconnect layer, the interconnect and a pad connecting the first plug and the second plug.

The method of forming a fuse structure according to any one of claims 2 to 5, further comprising:

An opening is formed in the second dielectric layer to expose the fuse.

The method for forming a fuse structure according to any one of claims 2 to 5, wherein the first dielectric layer and the second dielectric layer are silicon dioxide, silicon carbide, silicon nitride, and oxynitride. Silicon or a combination thereof.

The method of forming a fuse structure according to claim 2 or 4, wherein the interconnect line and the pad are aluminum interconnect lines and an aluminum pad, and the first plug and the second plug are Tungsten plug.

9. The method of forming a fuse structure according to claim 3, wherein the interconnect line and the pad are copper interconnect lines and a bra pad, and the second plug is a copper plug.

The method of forming a fuse structure according to claim 5, wherein the interconnect line and the pad are copper interconnect lines and a bra pad, and the first plug and the second plug are copper plugs. .

A fuse structure formed by the method of forming a fuse structure according to any one of claims 1 to 10.