WO2010143597A1 - Method for manufacturing circuit board, circuit board manufactured by the method, and base substrate used for the circuit board - Google Patents

Method for manufacturing circuit board, circuit board manufactured by the method, and base substrate used for the circuit board Download PDF

Info

Publication number
WO2010143597A1
WO2010143597A1 PCT/JP2010/059569 JP2010059569W WO2010143597A1 WO 2010143597 A1 WO2010143597 A1 WO 2010143597A1 JP 2010059569 W JP2010059569 W JP 2010059569W WO 2010143597 A1 WO2010143597 A1 WO 2010143597A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit board
hole
sealing
circuit
board
Prior art date
Application number
PCT/JP2010/059569
Other languages
French (fr)
Japanese (ja)
Inventor
河浦茂裕
井田誠
Original Assignee
日本カーバイド工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本カーバイド工業株式会社 filed Critical 日本カーバイド工業株式会社
Priority to JP2011518522A priority Critical patent/JP5566383B2/en
Publication of WO2010143597A1 publication Critical patent/WO2010143597A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1377—Protective layers
    • H05K2203/1394—Covering open PTHs, e.g. by dry film resist or by metal disc
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections

Definitions

  • the present invention relates to a method for manufacturing a circuit board, a circuit board manufactured thereby, and a mother board for a circuit board used therefor.
  • a circuit board mother board having a plurality of circuit areas and capable of obtaining a plurality of circuit boards, a circuit board manufacturing method using the circuit mother board, and a circuit board manufacturing method using the circuit board mother board.
  • a circuit board manufacturing method capable of obtaining a circuit board in which castellation electrodes are appropriately exposed by a simple method, and a circuit board manufactured thereby, and The present invention relates to a circuit board mother board to be used.
  • circuit board is generally mounted on a mounting board in a state where electronic components are mounted.
  • the circuit board may have a castellation structure in order to appropriately solder the circuit board.
  • the castellation structure is a structure in which a concave portion is formed on the side surface of the substrate, and an electrode is formed on the wall surface of the concave portion, and this electrode is sometimes called a castellation electrode or simply castellation.
  • FIG. 1 is a cross-sectional view of a circuit board having a conventional castellation structure.
  • the circuit board 100 has a base 105 made of an insulating material.
  • the substrate 105 is provided with a wiring conductor 102 for connecting to the electronic component 101 on the front surface, and a wiring conductor 107 for connecting to the mounting substrate on which the circuit board 100 is mounted on the back surface.
  • the base body 105 is provided with through conductors (through holes, via holes, etc.) for connecting the wiring conductors 102 and 107 on the front surface and the back surface.
  • a castellation electrode 106 connected to the wiring conductor 107 on the back surface of the base 105 is provided on the side surface of the base 105.
  • the electronic component 101 installed on the base 105 is connected to the wiring conductor by a bonding wire or directly connected to the wiring conductor 102 as shown in FIG. Is hermetically protected.
  • circuit board 100 Since such a circuit board 100 is miniaturized as described above, in order to facilitate handling and increase productivity, a circuit board in which a large number of circuit areas are arranged vertically and horizontally and a large number of circuit boards can be obtained. It may be manufactured from a mother board. That is, in each circuit area of the circuit board mother board, after providing electronic components with wiring conductors and through conductors, divided into individual substrates along the dividing lines formed on the outer edge of each circuit area, Manufacturing circuit boards has been performed. When the circuit board has the castellation structure described above, a through hole is provided on a dividing line provided on the outer edge of each circuit area of the circuit board mother board, and the through hole is divided so that a caster is obtained. The formation of a ration electrode has been performed.
  • the sealing resin may enter the through hole and leak to the back surface of the circuit board mother board.
  • the sealing resin adheres to the inner wall surface of the through hole.
  • the castellation electrode of the circuit board is covered with the sealing resin, and the castellation electrode may not be properly exposed, so that proper soldering may not be performed.
  • the substrate has a multilayer structure as shown in FIG. 1, or a barrier layer is provided around the electronic component.
  • these methods are not preferable because the manufacturing process becomes complicated, and a simple method for preventing the sealing resin from leaking from the through hole is required.
  • the present invention provides a circuit board manufacturing method capable of obtaining a circuit board in which castellation electrodes are appropriately exposed by a simple method, a circuit board manufactured thereby, and a circuit used therefor
  • An object is to provide a mother board for a board.
  • a method for manufacturing a circuit board according to the present invention includes a preparation step of preparing a circuit board mother board having a plurality of circuit regions and a plurality of through holes, and an opening in each through hole.
  • the sealing composition is a glass composition
  • the glass paste is applied by applying a glass paste to the circuit board mother board. Further, it is preferable to fire the circuit board mother board.
  • the glass composition has high strength, according to such a circuit board mother board, when the circuit region is sealed with the sealing resin in the circuit sealing process, the sealing on the sealing composition is performed. Even if pressure is applied to the resin, the sealing resin can be prevented from entering the through hole. In addition, since the glass composition is brittle, it can be easily broken when the circuit board mother board is divided in the dividing step, and the circuit board can be easily manufactured. In addition, after dividing the glass composition, it is possible to produce a circuit board having a clean divided section and a good finish.
  • the sealing composition preferably has a thickness at a position in contact with an inner wall surface of the through hole larger than a thickness at a central portion in the radial direction of the through hole.
  • the sealing composition in the through hole has a thickest portion formed at a position in contact with the inner wall surface of the through hole.
  • the sealing composition in the through hole has a thinnest portion formed at a central portion in the radial direction of the through hole.
  • the sealing composition is easily divided at the central portion in the radial direction of the through hole, and the seal remaining on the circuit board.
  • the stopping composition can be made substantially the same for each circuit board, and a homogeneous circuit board can be obtained.
  • the circuit board mother board may be made of the ceramic.
  • the circuit board mother board may be a single-layer board.
  • circuit board of the present invention is manufactured by any one of the above-described circuit board manufacturing methods.
  • the castellation electrode can be appropriately exposed.
  • a circuit board mother board of the present invention has a plurality of circuit regions and a plurality of through holes, and is divided along the plurality of through holes. In each of the through holes, only one side of the opening is sealed with a sealing composition.
  • circuit board mother board since only one side of the opening in the through hole is sealed with the sealing composition, even when sealing a plurality of circuit regions with a sealing resin, It is possible to prevent the sealing resin from entering the through hole. And since the other side of the opening in the through hole is not sealed with the sealing composition, the wall surface is exposed. Therefore, by dividing the circuit board mother board along the plurality of through holes, a circuit board in which castellation electrodes are appropriately exposed can be obtained.
  • the sealing composition is preferably a glass composition.
  • the sealing resin penetrates into the through hole even when pressure is applied when the circuit area is sealed with the sealing resin. Can be prevented. Further, since the glass composition is brittle, according to such a circuit board mother board, it can be easily broken when the circuit board mother board is divided, and the circuit board can be easily manufactured. Can do. Further, after dividing the glass composition, the divided cross section is clean, and according to such a circuit board mother board, a circuit board having a good finish can be manufactured.
  • the sealing composition preferably has a thickness at a position in contact with an inner wall surface of the through hole larger than a thickness at a central portion in the radial direction of the through hole.
  • the contact area between the inner wall surface of the through hole and the sealing composition can be increased, and the sealing composition can be prevented from being unnecessarily peeled off. it can.
  • the sealing composition in the through hole has a thickest portion formed at a position in contact with the inner wall surface of the through hole.
  • the sealing composition can be most prevented from peeling off unnecessarily.
  • the sealing composition in the through hole has a thinnest part formed at the center in the radial direction of the through hole.
  • circuit board mother board when the circuit board mother board is divided, the sealing composition is easily divided at the central portion in the radial direction of the through hole, and the sealing composition remaining on the circuit board is reduced.
  • Each circuit board can be made substantially the same, and a uniform circuit board can be obtained.
  • dividing lines are formed along positions overlapping with the plurality of through holes.
  • circuit board mother board According to such a circuit board mother board, it is only necessary to divide the circuit board mother board along the dividing line, so that the circuit board mother board can be easily divided.
  • a dividing groove is formed on at least one surface along the dividing line.
  • the circuit board mother board can be easily divided by dividing the circuit board mother board along the dividing grooves.
  • the circuit board mother board may be made of ceramic.
  • the circuit board mother board may be a single-layer board.
  • a circuit board manufacturing method capable of obtaining a circuit board in which castellation electrodes are appropriately exposed by a simple method, and a circuit board manufactured thereby, and A mother board for a circuit board used therefor is provided.
  • FIG. 1 is a perspective view of a circuit board according to an embodiment of the present invention. It is a figure which shows the structure of the cross section in the surface which passes the castellation electrode of FIG. It is a side view in the vicinity of the castellation electrode of the circuit board of FIG. It is a figure which shows a mode that the electronic component was mounted in the circuit board and sealed with sealing resin. It is a figure which shows the mode of the castellation electrode with which the circuit board shown in FIG. 2 is mounted. It is a flowchart which shows the manufacturing method of a circuit board. It is a figure which shows the mode of the board
  • FIG. 2 is a perspective view of a circuit board manufactured by the circuit board mother board and the circuit board manufacturing method according to the present embodiment.
  • the circuit board 20 includes a substantially rectangular parallelepiped base 9, a circuit region 21 formed on one surface of the base 9, and a wiring conductor at least partially formed in the circuit region 21. 2, a castellation electrode 6 provided on the side surface of the substrate 9, a wiring conductor 7 formed on the other surface of the substrate 9, and a sealing composition 8 at least partially formed on the wiring conductor 2 And at least a sealing resin for sealing the circuit region 21 as a main configuration.
  • FIG. 3 is a diagram showing a cross-sectional structure in a plane passing through the castellation electrode 6 of FIG. 2 and 3, the sealing resin is omitted for easy understanding.
  • the base body 9 has a substantially rectangular parallelepiped shape as described above, and a plurality of a pair of side surfaces facing each other are cut into a substantially semicylindrical shape to form a recess.
  • a castellation electrode 6 is provided on the surface of each recess, and each castellation electrode 6 extends from one surface of the base 9 to the other surface along the recess. That is, the castellation electrode 6 has a shape in which the through hole is divided along the length direction of the hole, and has a concave shape with respect to the side surface of the base 9. Further, the castellation electrode 6 is connected to the wiring conductor 2 provided on one surface of the base 9, and is further connected to the wiring conductor 7 provided on the other surface of the base 9.
  • Each wiring conductor 2 connected to each castellation electrode 6 has a rectangular shape in which a part of the wiring conductor 2 is cut into an arc shape by a recess provided in the base 9 on one surface of the base 9. I am doing. Similarly, each of the wiring conductors 7 connected to the respective castellation electrodes 6 was partially cut into an arc shape by a recess provided in the base 9 on the other surface of the base 9. It has a rectangular shape.
  • the circuit region 21 is formed on one surface of the base 9, and at least a part of the wiring conductor 2 extends into the circuit region 21.
  • the circuit region 21 includes at least a wiring conductor 2 for connecting to an electronic component mounted on the circuit board 20, and further includes any of a wiring conductor, a through hole, and a via hole for connecting the circuit board and the mounting board. May have.
  • FIG. 4 is a side view in the vicinity of the castellation electrode 6 of the circuit board 20 of FIG.
  • a part of each wiring conductor 2 and a part of each castellation electrode 6 are covered with a sealing composition 8.
  • the sealing composition 8 is filled in the concave portions only on one surface side of each castellation electrode 6.
  • the sealing composition 8 which has entered the recess is the thinnest portion at the approximate center of the recess, and the thickness is a.
  • the sealing composition 8 is the thickest portion at the position in contact with the castellation electrode 6 and the thickness is b.
  • the sealing composition 8 has a thickness f on the wiring conductor 2.
  • FIG. 5 is a view showing a state in which the electronic component 1 is mounted on the circuit board 20 and sealed with the sealing resin 13.
  • the electronic component 1 is fixed on one surface of the base 9 by means (not shown), and is electrically connected to the wiring conductor 2 by a bonding wire 11.
  • the sealing resin 13 has a surface substantially parallel to the surface of the circuit board 20 formed in a substantially flat shape. The sealing resin 13 seals from the circuit region 21 of the circuit board 20 to the surface of the sealing composition 8.
  • FIG. 6 is a diagram showing a state of the castellation electrode on which the circuit board shown in FIG. 2 is mounted.
  • the circuit board 20 is disposed on the mounting board, and the terminals 12 of the mounting board, the wiring conductors 7 and the castellation electrodes 6 are connected by solder 15.
  • the solder may be sucked up to the wiring conductor 2 side of the circuit board 20 through the castellation electrode 6, but the solder 15 is used for the wiring of the circuit board 20 by the sealing composition 8. Reaching the conductor 2 is prevented. Therefore, according to such a circuit board 20, an unnecessary short circuit due to solder or the like is not required during mounting without having a complicated structure in which the base has a multilayer structure or a barrier layer is provided around the electronic component. Can be prevented.
  • FIG. 7 is a flowchart showing a method for manufacturing the circuit board 20.
  • the method of manufacturing the circuit board 20 includes a preparation step P1 for preparing a circuit board mother board having a plurality of circuit regions 21 and a plurality of through holes, and one of openings in each through hole.
  • Through-hole sealing step P2 for sealing only the side with the sealing composition 8
  • component placement step P3 for placing the electronic component 1 on the circuit region, and sealing each circuit region 21 with the sealing resin 13
  • a circuit sealing process P4 to be performed and a dividing process P5 for dividing the circuit board mother board along the plurality of through holes are provided as main processes.
  • the component placement step P3 is not necessary.
  • the preparation process P1 includes a substrate preparation process P1a, a drilling process P1b, and a conductor formation process P1c.
  • substrate preparation process P1a First, a substrate 31 serving as a base for a circuit board mother board is prepared. This substrate finally becomes the base 9 of the circuit board 20.
  • the material of the substrate 31 examples include materials used for general wiring substrates such as polyimide, glass epoxy, BT resin (registered trademark of Mitsubishi Gas Chemical Co., Ltd.), and ceramics.
  • substrate 31 it is preferable to use ceramics, such as an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, glass ceramics, from a durable point.
  • the thickness of the substrate 31 in the present invention is not particularly limited, but is preferably 100 ⁇ m to 5,000 ⁇ m in view of strength and circuit board size.
  • the substrate 31 may be either a single layer substrate or a multilayer substrate, but it is preferable to use a single layer substrate from the viewpoint that the manufacturing process can be simplified.
  • the substrate 31 is preferably provided with a dividing line L so that the dividing operation is facilitated in the subsequent dividing step P5.
  • the dividing line indicates a position where the circuit board mother board having the plurality of circuit areas 21 is divided into individual circuit areas in the dividing step P5.
  • a plurality of through holes 32 are formed in the prepared substrate 31 for forming a plurality of through holes.
  • the through hole 32 is opened on the dividing line L so that the center is located.
  • the through hole 32 can be formed in the substrate by punching, drilling, laser processing, or the like.
  • a part of substrate preparation process P1a and a part of drilling process P1b can be performed simultaneously.
  • the substrate 31 having a plurality of through holes 32 is formed by punching through holes in the green sheet before firing, and then firing the punched holes.
  • the sintered alumina substrate can be drilled with the through holes 32 by laser or drilling. In this way, a substrate 31 having a plurality of through holes 32 shown in FIG. 8 is obtained.
  • a conductor is formed around the through hole 32 on the side surface of the through hole 32 and the surface of the substrate 31 formed by the drilling step P1b.
  • the conductive material for forming the through hole and the wiring conductors 2 and 7 is not particularly limited, but tungsten (W), molybdenum (Mo), nickel (Ni), copper (Cu), silver (Ag), gold Metals such as (Au), palladium (Pd), and platinum (Pt) can be used.
  • the conductor can be formed by being deposited on the substrate 31 by plating, printing, vapor deposition, or the like.
  • the thickness of the conductor is preferably 1 to 30 ⁇ m.
  • a metal having excellent corrosion resistance such as Ni, Au, Pt or the like on the surface of the conductor to a thickness of about 1 to 20 ⁇ m.
  • the material of such a sealing composition is not particularly limited, and examples thereof include conductive materials such as metals, and insulating materials such as glass and insulating resin. Among them, insulating materials are used. It is particularly preferable to use a glass composition from the viewpoint of workability and durability.
  • a thermoplastic resin or a thermosetting resin may be used.
  • a thermoplastic resin is used as the sealing composition, the resin plasticized by heating is applied from one opening side of the through hole and then solidified by cooling to seal the through hole Can do.
  • a thermosetting resin is used as the sealing composition, an uncured resin is applied from one opening side of the through hole and then solidified by heating to seal the through hole. be able to.
  • the insulating resin When such an insulating resin is used as the sealing composition, the insulating resin is constant so that the insulating resin does not flow down to the opposite side of the substrate through the through hole when the insulating resin is applied. It adjusts so that it may have the following viscosity.
  • a glass paste containing glass powder, a binder, a solvent, etc. is applied from one opening side of the through hole, and then dried and solidified to seal the through hole. can do.
  • the glass paste can contain fillers such as silicon oxide and alumina.
  • FIG. 11 is a view showing a state of a cross section in the through hole of the circuit board mother board 30 of FIG. Specifically, FIGS. 11A to 11C show states in which the shape of the sealing composition 8 in the cross section of the through hole is different, and FIG. 11A shows the sealing composition 8. 11 (B) shows a state where the bottom surface of the sealing composition 8 is lowered, and FIG. 11 (C) shows a state where the sealing composition 8 is a through-hole. Shown off center.
  • the inner wall surface of the through hole 32 provided in the dividing line L and the substrate 31 ( The distance c that is farthest from the outer peripheral surface of the conductor of the through hole is preferably 50 to 300 ⁇ m. If the maximum distance between the dividing line L and the inner wall surface of the through hole 32 is 50 ⁇ m or more, the through hole 32 is prevented from being sealed with a conductor that forms a through hole in the conductor forming step P1c. If the through hole 32 is sealed with a conductor that forms a through hole, the through hole conductor may be peeled off from the substrate when the circuit board mother board 30 is divided in the subsequent division step P5. Absent. On the other hand, if the maximum distance between the dividing line L and the inner wall surface of the through hole is 300 ⁇ m or less, it is preferable because the through hole can be more appropriately sealed with the sealing composition 8 in the through hole sealing step P2.
  • the thinnest portion a of the sealing composition 8 in the through hole is preferably 5 to 500 ⁇ m thick. If the thinnest part a of the sealing composition 8 that seals the through hole is 5 ⁇ m or more, the sealing composition is applied when applying a sealing resin that hermetically protects electronic components and the like in the subsequent circuit sealing step P4. It is possible to appropriately prevent the thinnest part of the object 8 from breaking. On the other hand, if the thinnest part a of the sealing composition 8 for sealing the through hole is 500 ⁇ m or less, it is preferable because the circuit board mother board 30 can be easily divided in the subsequent dividing step P5.
  • the thinnest part a of the sealing composition 8 for sealing the through-hole is to divide the circuit board mother board 30 into each circuit area as shown in FIGS. In order to facilitate, it is preferable that it exists in the vicinity of the dividing line L, and it is more preferable that it exists on the dividing line.
  • the thickest portion b of the sealing composition 8 for sealing the through hole is preferably in the vicinity of the inner wall portion of the through hole. b is preferably present at a position in contact with the inner wall surface of the through hole. If the thickest part b of the sealing composition 8 is present at a position in contact with the inner wall surface of the through hole, the contact area between the sealing composition 8 and the inner wall surface of the through hole is increased. Adhesion with the inner wall surface of the hole can be increased, and the sealing composition 8 can be prevented from peeling off from the inner wall surface of the through-hole when the circuit board mother board 30 is divided in the subsequent dividing step P5. Can do.
  • the sealing composition 8 adhering in the through hole is 1% or more of the through hole in the depth direction, the sealing composition 8 and the inner wall surface of the through hole Adhesion can be sufficiently secured. Therefore, in the circuit sealing step P4, when applying a sealing resin that hermetically protects electronic components and the like, it is possible to more appropriately prevent the sealing composition 8 from dropping from the inner wall surface of the through hole. Furthermore, in the dividing step P5, it is possible to more appropriately prevent the sealing composition 8 from peeling from the inner wall surface of the through hole when the circuit board mother board 30 is divided. On the other hand, if the sealing composition 8 adhering in the through hole is 85% or less of the through hole in the depth direction, the castellation electrode 6 of the circuit board 20 is more sufficiently formed after the dividing step P5. Can be exposed to.
  • the sealing composition 8 is preferably attached to the inner wall surface of the 5 to 500 ⁇ m through hole in the depth direction from the end of the through hole. As shown in FIG. 2, if the sealing composition 8 filled in the through hole adheres to the opening from one side of the through hole by 5 ⁇ m or more, the sealing composition 8 and the inner wall surface of the through hole Adhesion can be sufficiently secured. Therefore, in the circuit sealing step P4, when applying a sealing resin that hermetically protects electronic components and the like, it is possible to more appropriately prevent the sealing composition from dropping from the inner wall surface of the through hole. In the dividing step P5, it is possible to more appropriately prevent the sealing composition 8 from being peeled off from the inner wall surface of the through hole when the circuit board mother board 30 is divided.
  • the caster of the circuit board 20 is obtained after the dividing step P5.
  • the exposure electrode 6 can be exposed more sufficiently.
  • the portion where the depth of the sealing composition 8 filled in the through hole is maximum is preferably in the vicinity of the inner wall portion of the through hole. Further, as shown in FIG. It is preferable that the portion where the depth of the sealing composition 8 filled in the hole is maximum coincides with the thickest portion b of the sealing composition 8 that seals the through hole. In this case, the adhesiveness between the sealing composition 8 and the inner wall surface of the through hole is increased, and the sealing composition 8 is peeled off from the inner wall portion of the through hole when the circuit board mother board 30 is divided in the dividing step P5. Can be prevented.
  • the sealing composition 8 for sealing the through holes is provided so as to cover a part of the wiring conductor 2 on the surface of the circuit board mother board 30. It is desirable. By covering a part of the wiring conductor 2 with the sealing composition 8, the adhesion between the sealing resin for sealing the circuit region 21 and the wiring conductor 2 is improved, and the sealing resin is prevented from peeling off. Can do. In particular, when the surface of the wiring conductor 2 is Au, the adhesiveness between the sealing resin and the wiring conductor 2 can be remarkably improved by covering a part of the wiring conductor 2 with the sealing composition 8.
  • Part placement process P3 when it is necessary to arrange an electronic component in the circuit area 21, the electronic component is arranged.
  • the terminal of the electronic component and the wiring conductor 2 are electrically connected.
  • the terminal of the electronic component and the wiring conductor 2 may be connected by wire bonding, and the terminal of the electronic component is placed on the wiring conductor 2 to form a conductive paste. You may connect with solder.
  • circuit sealing process P4 Next, the circuit region 21 is sealed with a sealing resin.
  • the resin used for the sealing resin include thermoplastic resins, thermosetting resins, and ultraviolet curable resins. Specifically, epoxy resins, silicone resins, polyolefin resins, polyamide resins, Examples thereof include resins such as polyimide resins and urethane resins.
  • the circuit area 21 is sealed by applying a thermoplastic resin that has been heated and plasticized to the circuit area 21, and then cooling and solidifying.
  • the circuit region 21 is sealed by applying an uncured thermosetting resin to the circuit region 21 and then solidifying by heating.
  • an ultraviolet curable resin which is a precursor of the ultraviolet curable resin, is applied to the circuit region 21 and then solidified by irradiation with ultraviolet rays, thereby sealing the circuit region 21. Do. Thus, a circuit board mother board in which the circuit region 21 is sealed with the sealing resin is obtained.
  • division process P5 Next, only one side of the through hole 32 of the through hole divides the circuit board mother board 30 sealed with the sealing composition 8.
  • the division may be divided into a plurality of circuit regions by laser or dicing so as to pass through the through holes.
  • the circuit board mother board 30 When the circuit board mother board 30 is divided, it may be divided along the dividing line L by laser or dicing as described above. Further, it is preferable that a dividing groove is formed along the dividing line L on at least one surface of the circuit board mother board 30.
  • the substrate 31 having the dividing grooves may be prepared in the substrate preparation step P1a.
  • a method of dividing in the case where the dividing grooves are provided in this way there is a method of breaking the circuit board mother board 30 along the provided dividing grooves.
  • the circuit board 20 shown in FIG. 2 is obtained by dividing the circuit board mother board 30 into the respective circuit boards 20.
  • Example 1 A circuit board for mounting electronic components was manufactured as follows. As a substrate, an alumina substrate (Hokuriku Ceramic Co., Ltd.) having V-shaped dividing grooves with a depth of 0.15 mm provided as dividing lines at intervals of 5 mm and having a through hole of ⁇ 0.3 mm formed on the dividing lines in advance. Manufactured: alumina purity 96%, thickness 0.5 mm, size 60 mm ⁇ 70 mm). A conductor paste (manufactured by Kyoto Elex, grade name “DD1130”) was applied by screen printing at a position where the wiring conductor and through-hole conductor of the alumina substrate were provided.
  • alumina substrate Hokuriku Ceramic Co., Ltd.
  • a conductor paste manufactured by Kyoto Elex, grade name “DD1130” was applied by screen printing at a position where the wiring conductor and through-hole conductor of the alumina substrate were provided.
  • the through-hole conductor was applied while sucking from the surface opposite to the surface to be printed of the substrate during screen printing.
  • the substrate is dried at a temperature of 50 ° C. for 10 minutes, and then fired by holding the substrate at a maximum temperature of 850 ° C. for 10 minutes to obtain a mother board for a circuit board having a silver wiring conductor having a thickness of 12 ⁇ m.
  • a substrate was produced.
  • a glass paste (made by Asahi Glass Co., grade name “AP5700”) is applied to the position where the sealing composition for the substrate is provided (including the position where the opening of the through hole is formed), and the temperature is 150 ° C. Dry for 20 minutes. Thereafter, the substrate was fired by raising the temperature and holding it at a maximum temperature of 850 ° C. for 10 minutes to obtain a mother board for circuit board on which a glass layer having a thickness of 35 ⁇ m was formed as a sealing composition.
  • the substrate was free of burrs, and the glass layer was almost split in the center of the through-hole and had good splitting ability. Met. Furthermore, when the divided cross section was observed with a microscope, it was confirmed that the through hole was sealed from one side by the glass layer.
  • Example 2 The ceramic plate used as the base was the same as in Example 1 except that a substrate having a thickness of 0.3 mm, a through-hole diameter of 0.2 mm, and a V-shaped dividing groove interval of 3 mm was used. Thus, a circuit board mother board was produced. When this substrate was divided into circuit substrates along the V-shaped dividing grooves, there was no burr on the substrate, and the glass also had good crack division at the center of the through hole.
  • an LED was mounted as an electronic component on the circuit board mother board produced in Example 1 and Example 2, and connected to the wiring conductor with a bonding wire.
  • the epoxy sealing resin was mold printed to seal the LED.
  • the mother board was divided for a circuit board along a V-shaped dividing groove, and the divided cross section was observed with a microscope. As a result, it was confirmed that no adhesion of the epoxy-based sealing resin was observed at the site serving as the castellation electrode, and leakage of the sealing resin was prevented by the glass layer. Furthermore, when the circuit board was soldered to the mounting board, a good solder fillet was formed.
  • a circuit board manufacturing method capable of obtaining a circuit board in which castellation electrodes are appropriately exposed by a simple method, a circuit board manufactured thereby, and a circuit used therefor A mother board for a substrate is provided.

Abstract

Provided is a method for manufacturing circuit boards, by which a circuit board having a castellation electrode suitably exposed therefrom can be obtained by a simple method. The circuit board manufactured by the method, and a base substrate for the circuit board are also provided. The base substrate (30) for the circuit board has a plurality of circuit regions and a plurality of through holes, and is divided along the through holes. Each through hole is sealed only on one side of the opening by means of a sealing composition (8). Therefore, even in the case of sealing the plurality of circuit regions by means of the sealing resin, the sealing resin is prevented from entering the through holes.

Description

回路基板の製造方法、及び、これにより製造される回路基板、及び、これに用いられる回路基板用母基板Circuit board manufacturing method, circuit board manufactured thereby, and mother board for circuit board used therefor
　本発明は、回路基板の製造方法、及び、これにより製造される回路基板、及び、これに用いられる回路基板用母基板に関する。具体的には、複数の回路領域を有し、複数の回路基板を得ることのできる回路基板用母基板、及び、この回路用母基板を用いる回路基板の製造方法、及び、これにより製造される回路基板に関し、さらに詳細には、簡便な方法によりキャスタレーション電極が適切に露出している回路基板を得ることができる回路基板の製造方法、及び、これにより製造される回路基板、及び、これに用いられる回路基板用母基板に関する。 The present invention relates to a method for manufacturing a circuit board, a circuit board manufactured thereby, and a mother board for a circuit board used therefor. Specifically, a circuit board mother board having a plurality of circuit areas and capable of obtaining a plurality of circuit boards, a circuit board manufacturing method using the circuit mother board, and a circuit board manufacturing method using the circuit board mother board. More specifically, a circuit board manufacturing method capable of obtaining a circuit board in which castellation electrodes are appropriately exposed by a simple method, and a circuit board manufactured thereby, and The present invention relates to a circuit board mother board to be used.
　近年、電子機器の小型化および高機能化に伴い電子部品の実装密度が高くなっている。このため、水晶振動子、トランジスタ、ＩＣ、ＬＥＤ等の電子部品を搭載する回路基板の小型化が要求されている。この回路基板は、一般的に電子部品が搭載された状態で、実装基板上に実装される。そして、このような回路基板の実装の際、回路基板が適切にはんだ付けされるために、回路基板は、キャスタレーション構造とされる場合がある。このキャスタレーション構造とは、基板の側面に凹部が形成されており、この凹部の壁面に電極が形成されている構造であり、この電極はキャスタレーション電極や、単にキャスタレーションと呼ばれることがある。 In recent years, the mounting density of electronic components has increased with the downsizing and higher functionality of electronic devices. For this reason, miniaturization of circuit boards on which electronic components such as crystal resonators, transistors, ICs, and LEDs are mounted is required. This circuit board is generally mounted on a mounting board in a state where electronic components are mounted. In mounting such a circuit board, the circuit board may have a castellation structure in order to appropriately solder the circuit board. The castellation structure is a structure in which a concave portion is formed on the side surface of the substrate, and an electrode is formed on the wall surface of the concave portion, and this electrode is sometimes called a castellation electrode or simply castellation.
　下記特許文献１には、このような回路基板の一例が記載されている。図１は、従来のキャスタレーション構造を有する回路基板の断面図である。図１に示すように、回路基板１００は、絶縁性材料からなる基体１０５を有する。そして、基体１０５は、その表面に電子部品１０１と接続するための配線導体１０２が設けられており、裏面には、回路基板１００が実装される実装基板と接続するための配線導体１０７が設けられている。また基体１０５には、表面と裏面の配線導体１０２、１０７を接続するための貫通導体（スルーホール、ビアホール等）が設けられている。さらに、基体１０５の側面には、基体１０５の裏面の配線導体１０７と接続されたキャスタレーション電極１０６が設けられている。なお、基体１０５上に設置された電子部品１０１は、ボンディングワイヤによって配線導体に接続されたり、図１に示すように配線導体１０２と直接接続されたりして、一般的に図示しない封止樹脂等により密閉保護される。 The following Patent Document 1 describes an example of such a circuit board. FIG. 1 is a cross-sectional view of a circuit board having a conventional castellation structure. As shown in FIG. 1, the circuit board 100 has a base 105 made of an insulating material. The substrate 105 is provided with a wiring conductor 102 for connecting to the electronic component 101 on the front surface, and a wiring conductor 107 for connecting to the mounting substrate on which the circuit board 100 is mounted on the back surface. ing. The base body 105 is provided with through conductors (through holes, via holes, etc.) for connecting the wiring conductors 102 and 107 on the front surface and the back surface. Further, a castellation electrode 106 connected to the wiring conductor 107 on the back surface of the base 105 is provided on the side surface of the base 105. The electronic component 101 installed on the base 105 is connected to the wiring conductor by a bonding wire or directly connected to the wiring conductor 102 as shown in FIG. Is hermetically protected.
　このような回路基板１００は、上述のように小型化されているので、その取り扱いを容易にし、生産性を高めるため、多数の回路領域が縦横に配列され、回路基板が多数個取りできる回路基板用母基板から製造される場合がある。すなわち、回路基板用母基板における各回路領域において、配線導体や貫通導体を設けて電子部品を搭載した後、各回路領域の外縁に形成された分割ラインに沿って個々の基体に分割して、回路基板を製造することが行われている。そして、回路基板が上述のキャスタレーション構造を有する場合には、回路基板用母基板の各回路領域の外縁に設けられた分割ライン上にスルーホールを設け、このスルーホールを分割することで、キャスタレーション電極を形成することが行われている。 Since such a circuit board 100 is miniaturized as described above, in order to facilitate handling and increase productivity, a circuit board in which a large number of circuit areas are arranged vertically and horizontally and a large number of circuit boards can be obtained. It may be manufactured from a mother board. That is, in each circuit area of the circuit board mother board, after providing electronic components with wiring conductors and through conductors, divided into individual substrates along the dividing lines formed on the outer edge of each circuit area, Manufacturing circuit boards has been performed. When the circuit board has the castellation structure described above, a through hole is provided on a dividing line provided on the outer edge of each circuit area of the circuit board mother board, and the through hole is divided so that a caster is obtained. The formation of a ration electrode has been performed.
特開２００５－１２３５６４号公報JP 2005-123564 A
　キャスタレーション構造を有する回路基板上において、上述のように回路領域や、回路領域上の電子部品を封止樹脂等により封止する場合、回路基板用母基板の分割前に樹脂封止を行い、その後回路基板用母基板を分割すれば、電子部品の搭載や樹脂封止が容易であり、回路基板の生産効率が上がる。しかし、この方法では、回路領域や電子部品を樹脂封止する際に、封止樹脂がスルーホールに侵入して、回路基板用母基板の裏面にまで漏出する虞がある。このように封止用樹脂がスルーホールに侵入し、回路基板用母基板の裏面にまで漏出すると、スルーホールの内壁面に封止樹脂が付着する。従って、回路基板用母基板の分割後に、回路基板のキャスタレーション電極が封止樹脂に覆われてしまい、キャスタレーション電極が適切に露出せずに、適切なはんだ付けができない虞がある。このような封止樹脂がスルーホールに侵入することを防止するため、図１のように基体を多層構造にしたり、電子部品の周囲にバリア層を設けることが行われている。しかし、これらの方法は製造工程が複雑となり好ましくなく、スルーホールから封止樹脂が漏出することを防止する簡便な方法が求められている。 On the circuit board having a castellation structure, when sealing the circuit area and the electronic component on the circuit area with a sealing resin or the like as described above, performing resin sealing before dividing the circuit board mother board, Then, if the mother board for circuit boards is divided, electronic components can be easily mounted and resin sealing can be performed, and the production efficiency of circuit boards can be improved. However, in this method, when the circuit region or the electronic component is resin-sealed, the sealing resin may enter the through hole and leak to the back surface of the circuit board mother board. When the sealing resin enters the through hole in this way and leaks to the back surface of the circuit board mother board, the sealing resin adheres to the inner wall surface of the through hole. Therefore, after the mother board for circuit board is divided, the castellation electrode of the circuit board is covered with the sealing resin, and the castellation electrode may not be properly exposed, so that proper soldering may not be performed. In order to prevent such sealing resin from penetrating into the through-hole, the substrate has a multilayer structure as shown in FIG. 1, or a barrier layer is provided around the electronic component. However, these methods are not preferable because the manufacturing process becomes complicated, and a simple method for preventing the sealing resin from leaking from the through hole is required.
　そこで、本発明は、簡便な方法によりキャスタレーション電極が適切に露出している回路基板を得ることができる回路基板の製造方法、及び、これにより製造される回路基板、及び、これに用いられる回路基板用母基板を提供することを目的とする。 Therefore, the present invention provides a circuit board manufacturing method capable of obtaining a circuit board in which castellation electrodes are appropriately exposed by a simple method, a circuit board manufactured thereby, and a circuit used therefor An object is to provide a mother board for a board.
　上記課題を解決するため、本発明の回路基板の製造方法は、複数の回路領域、及び、複数のスルーホールを有する回路基板用母基板を準備する準備工程と、それぞれの前記スルーホールにおける開口の一方側のみを、封止組成物により封止するスルーホール封止工程と、それぞれの前記回路領域を封止樹脂により封止する回路封止工程と、前記複数のスルーホールに沿って前記母基板を分割する分割工程と、を備えることを特徴とするものである。 In order to solve the above problems, a method for manufacturing a circuit board according to the present invention includes a preparation step of preparing a circuit board mother board having a plurality of circuit regions and a plurality of through holes, and an opening in each through hole. A through hole sealing step of sealing only one side with a sealing composition; a circuit sealing step of sealing each of the circuit regions with a sealing resin; and the mother substrate along the plurality of through holes And a dividing step of dividing.
　このような回路基板の製造方法によれば、スルーホールにおける開口の一方側のみが、封止組成物により封止されているため、それぞれの回路領域を封止樹脂により封止するときに、封止樹脂がスルーホールに侵入することを防止することができる。そして、スルーホールにおける開口の他方側は、封止組成物により封止されていないため、壁面が露出している。従って、キャスタレーション電極が適切に露出している回路基板を得ることができる。 According to such a method of manufacturing a circuit board, since only one side of the opening in the through hole is sealed with the sealing composition, when sealing each circuit region with the sealing resin, sealing is performed. It is possible to prevent the stop resin from entering the through hole. And since the other side of the opening in the through hole is not sealed with the sealing composition, the wall surface is exposed. Therefore, it is possible to obtain a circuit board in which castellation electrodes are appropriately exposed.
　また、上記回路基板の製造方法において、前記封止組成物がガラス組成物であり、前記スルーホール封止工程において、前記回路基板用母基板にガラスペーストを塗布して、前記ガラスペーストが塗布された前記回路基板用母基板を焼成することが好ましい。 Further, in the method for manufacturing a circuit board, the sealing composition is a glass composition, and in the through-hole sealing step, the glass paste is applied by applying a glass paste to the circuit board mother board. Further, it is preferable to fire the circuit board mother board.
　ガラス組成物は、高い強度を有するため、このような回路基板用母基板によれば、回路封止工程において、回路領域を封止樹脂により封止するときに、封止組成物上の封止樹脂に圧力がかかっても封止樹脂がスルーホール内に侵入することを防止することができる。また、ガラス組成物は、脆性であるため、分割工程において、回路基板用母基板を分割するときに容易に破断することができ、容易に回路基板を製造することができる。また、ガラス組成物を分割した後において、分割断面がきれいであり、仕上がりの良い回路基板を製造することができる。 Since the glass composition has high strength, according to such a circuit board mother board, when the circuit region is sealed with the sealing resin in the circuit sealing process, the sealing on the sealing composition is performed. Even if pressure is applied to the resin, the sealing resin can be prevented from entering the through hole. In addition, since the glass composition is brittle, it can be easily broken when the circuit board mother board is divided in the dividing step, and the circuit board can be easily manufactured. In addition, after dividing the glass composition, it is possible to produce a circuit board having a clean divided section and a good finish.
　また、上記回路基板の製造方法において、前記封止組成物は、前記スルーホールの内壁面と接する位置における厚さが、前記スルーホールの径方向の中心部における厚さよりも大きいことが好ましい。 In the method for manufacturing a circuit board, the sealing composition preferably has a thickness at a position in contact with an inner wall surface of the through hole larger than a thickness at a central portion in the radial direction of the through hole.
　このような回路基板の製造によれば、スルーホールの内壁面と封止組成物との接触面積を大きくすることができるので、分割工程において、封止組成物が不要に剥離してしまうことを防止することができる。 According to the manufacture of such a circuit board, since the contact area between the inner wall surface of the through hole and the sealing composition can be increased, the sealing composition is unnecessarily peeled off in the dividing step. Can be prevented.
　さらに、上記回路基板の製造方法において、前記スルーホール内の前記封止組成物は、前記スルーホールの内壁面に接する位置において最厚部が形成されていることが好ましい。 Furthermore, in the method for manufacturing a circuit board, it is preferable that the sealing composition in the through hole has a thickest portion formed at a position in contact with the inner wall surface of the through hole.
　このような回路基板の製造によれば、分割工程において、封止組成物が不要に剥離してしまうことを最も防止することができる。 According to the manufacture of such a circuit board, it is possible to most prevent the sealing composition from being unnecessarily peeled off in the dividing step.
　また、上記回路基板の製造方法において、前記スルーホール内の前記封止組成物は、前記スルーホールの径方向における中心部において、最薄部が形成されていることが好ましい。 In the method for manufacturing a circuit board, it is preferable that the sealing composition in the through hole has a thinnest portion formed at a central portion in the radial direction of the through hole.
　このような回路基板用母基板によれば、分割工程において、回路基板用母基板を分割するときに、封止組成物がスルーホールの径方向における中心部で分割され易く、回路基板に残る封止組成物をそれぞれの回路基板で略同様にすることができ、均質な回路基板を得ることができる。 According to such a circuit board mother board, in the dividing step, when the circuit board mother board is divided, the sealing composition is easily divided at the central portion in the radial direction of the through hole, and the seal remaining on the circuit board. The stopping composition can be made substantially the same for each circuit board, and a homogeneous circuit board can be obtained.
　また、上記回路基板の製造方法において、回路基板用母基板が前記セラミックからなることとしても良い。 In the above circuit board manufacturing method, the circuit board mother board may be made of the ceramic.
　また、上記回路基板の製造方法において、前記回路基板用母基板が単層基板からなることとしても良い。 In the method for manufacturing a circuit board, the circuit board mother board may be a single-layer board.
　さらに本発明の回路用基板は、上記回路基板の製造方法のいずれかにより製造されることを特徴とするものである。 Further, the circuit board of the present invention is manufactured by any one of the above-described circuit board manufacturing methods.
　このような回路基板によれば、キャスタレーション電極を適切に露出させることができる。 According to such a circuit board, the castellation electrode can be appropriately exposed.
　また、上記課題を解決するため、本発明の回路基板用母基板は、複数の回路領域、及び、複数のスルーホールを有し、前記複数のスルーホールに沿って分割される回路基板用母基板であって、それぞれ前記スルーホールは、開口の一方側のみが、封止組成物により封止されていることを特徴とするものである。 In order to solve the above problems, a circuit board mother board of the present invention has a plurality of circuit regions and a plurality of through holes, and is divided along the plurality of through holes. In each of the through holes, only one side of the opening is sealed with a sealing composition.
　このような回路基板用母基板によれば、スルーホールにおける開口の一方側のみが、封止組成物により封止されているため、複数の回路領域を封止樹脂により封止する場合においても、封止樹脂がスルーホールに侵入することを防止することができる。そして、スルーホールにおける開口の他方側は、封止組成物により封止されていないため、壁面が露出している。従って、回路基板用母基板を複数のスルーホールに沿って分割することにより、キャスタレーション電極が適切に露出している回路基板を得ることができる。 According to such a circuit board mother board, since only one side of the opening in the through hole is sealed with the sealing composition, even when sealing a plurality of circuit regions with a sealing resin, It is possible to prevent the sealing resin from entering the through hole. And since the other side of the opening in the through hole is not sealed with the sealing composition, the wall surface is exposed. Therefore, by dividing the circuit board mother board along the plurality of through holes, a circuit board in which castellation electrodes are appropriately exposed can be obtained.
　また、上記回路基板用母基板において、前記封止組成物がガラス組成物であることが好ましい。 In the above mother board for circuit board, the sealing composition is preferably a glass composition.
　ガラス組成物は、高い強度を有するため、このような回路基板用母基板によれば、回路領域を封止樹脂により封止するときに、圧力が掛かっても封止樹脂がスルーホール内に侵入することを防止することができる。また、ガラス組成物は、脆性であるため、このような回路基板用母基板によれば、回路基板用母基板を分割するときに容易に破断することができ、容易に回路基板を製造することができる。また、ガラス組成物を分割した後において、分割断面がきれいであり、このような回路基板用母基板によれば、仕上がりの良い回路基板を製造することができる。 Since the glass composition has high strength, according to such a circuit board mother board, the sealing resin penetrates into the through hole even when pressure is applied when the circuit area is sealed with the sealing resin. Can be prevented. Further, since the glass composition is brittle, according to such a circuit board mother board, it can be easily broken when the circuit board mother board is divided, and the circuit board can be easily manufactured. Can do. Further, after dividing the glass composition, the divided cross section is clean, and according to such a circuit board mother board, a circuit board having a good finish can be manufactured.
　また、上記回路基板用母基板において、前記封止組成物は、前記スルーホールの内壁面に接する位置における厚さが、前記スルーホールの径方向の中心部における厚さよりも大きいことが好ましい。 In the circuit board mother board, the sealing composition preferably has a thickness at a position in contact with an inner wall surface of the through hole larger than a thickness at a central portion in the radial direction of the through hole.
　このような回路基板用母基板によれば、スルーホールの内壁面と封止組成物との接触面積を大きくすることができ、封止組成物が不要に剥離してしまうことを防止することができる。 According to such a circuit board mother board, the contact area between the inner wall surface of the through hole and the sealing composition can be increased, and the sealing composition can be prevented from being unnecessarily peeled off. it can.
　また、上記回路基板用母基板において、前記スルーホール内の前記封止組成物は、前記スルーホールの内壁面に接する位置において最厚部が形成されていることが好ましい。 In the mother board for circuit board, it is preferable that the sealing composition in the through hole has a thickest portion formed at a position in contact with the inner wall surface of the through hole.
　このような回路基板用母基板によれば、封止組成物が不要に剥離してしまうことを最も防止することができる。 According to such a circuit board mother board, the sealing composition can be most prevented from peeling off unnecessarily.
　また、上記回路基板用母基板において、前記スルーホール内の前記封止組成物は、前記スルーホールの径方向における中心部において、最薄部が形成されていることが好ましい。 In the above circuit board mother board, it is preferable that the sealing composition in the through hole has a thinnest part formed at the center in the radial direction of the through hole.
　このような回路基板用母基板によれば、回路基板用母基板を分割するときに、封止組成物がスルーホールの径方向における中心部で分割され易く、回路基板に残る封止組成物をそれぞれの回路基板で略同様にすることができ、均質な回路基板を得ることができる。 According to such a circuit board mother board, when the circuit board mother board is divided, the sealing composition is easily divided at the central portion in the radial direction of the through hole, and the sealing composition remaining on the circuit board is reduced. Each circuit board can be made substantially the same, and a uniform circuit board can be obtained.
　また、上記回路基板用母基板において、前記複数のスルーホールと重なる位置に沿って、分割ラインが形成されていることが好ましい。 In the mother board for circuit boards, it is preferable that dividing lines are formed along positions overlapping with the plurality of through holes.
　このような回路基板用母基板によれば、分割ラインに沿って回路基板用母基板を分割すれば良いので、回路基板用母基板の分割作業が容易である。 According to such a circuit board mother board, it is only necessary to divide the circuit board mother board along the dividing line, so that the circuit board mother board can be easily divided.
　さらに、上記回路基板用母基板において、少なくとも一方の面に前記分割ラインに沿って分割溝が形成されていることが好ましい。 Furthermore, in the above-mentioned mother board for circuit boards, it is preferable that a dividing groove is formed on at least one surface along the dividing line.
　このような回路基板用母基板によれば、分割溝に沿って回路基板用母基板を割ることで、容易に回路基板用母基板の分割作業を行うことができる。 According to such a circuit board mother board, the circuit board mother board can be easily divided by dividing the circuit board mother board along the dividing grooves.
　また、上記回路基板用母基板が、セラミックからなることとしても良い。 The circuit board mother board may be made of ceramic.
　また、上記回路基板用母基板が、単層基板からなることとしても良い。 Also, the circuit board mother board may be a single-layer board.
　以上説明したように、本発明によれば、簡便な方法によりキャスタレーション電極が適切に露出している回路基板を得ることができる回路基板の製造方法、及び、これにより製造される回路基板、及び、これに用いられる回路基板用母基板が提供される。 As described above, according to the present invention, a circuit board manufacturing method capable of obtaining a circuit board in which castellation electrodes are appropriately exposed by a simple method, and a circuit board manufactured thereby, and A mother board for a circuit board used therefor is provided.
従来の回路基板の概略図である。It is the schematic of the conventional circuit board. 本発明の実施形態に係る回路基板の斜視図である。1 is a perspective view of a circuit board according to an embodiment of the present invention. 図２のキャスタレーション電極を通る面における断面の構造を示す図である。It is a figure which shows the structure of the cross section in the surface which passes the castellation electrode of FIG. 図２の回路基板のキャスタレーション電極の付近における側面図である。It is a side view in the vicinity of the castellation electrode of the circuit board of FIG. 回路基板に電子部品が搭載されて封止樹脂により封止された様子を示す図である。It is a figure which shows a mode that the electronic component was mounted in the circuit board and sealed with sealing resin. 図２に示す回路基板が実装されているキャスタレーション電極の様子を示す図である。It is a figure which shows the mode of the castellation electrode with which the circuit board shown in FIG. 2 is mounted. 回路基板の製造方法を示すフローチャートである。It is a flowchart which shows the manufacturing method of a circuit board. 孔あけ工程後の基板の様子を示す図である。It is a figure which shows the mode of the board | substrate after a drilling process. 導体形成工程後の回路基板用母基板の様子を示す図である。It is a figure which shows the mode of the motherboard for circuit boards after a conductor formation process. スルーホール封止工程後の回路基板用母基板の様子を示す図である。It is a figure which shows the mode of the motherboard for circuit boards after a through-hole sealing process. 回路基板用母基板のスルーホールにおける断面の様子を示す図である。It is a figure which shows the mode of the cross section in the through hole of the motherboard for circuit boards.
　以下、本発明に係る回路基板の製造方法、及び、これにより製造される回路基板、及び、これに用いられる回路基板用母基板の好適な実施形態について図面を参照しながら詳細に説明する。 Hereinafter, preferred embodiments of a method for producing a circuit board according to the present invention, a circuit board produced thereby, and a mother board for a circuit board used therefor will be described in detail with reference to the drawings.
　図２は、本実施形態に係る回路基板用母基板、及び、回路基板の製造方法により製造される回路基板の斜視図である。図２に示すように、本回路基板２０は、略直方体形状の基体９と、基体９の一方側の面に形成される回路領域２１と、回路領域２１に少なくとも一部が形成される配線導体２と、基体９の側面に設けられるキャスタレーション電極６と、基体９の他方側の面に形成される配線導体７と、配線導体２上に少なくとも一部が形成される封止組成物８と、少なくとも回路領域２１を封止する封止樹脂とを主な構成として備える。また、図３は、図２のキャスタレーション電極６を通る面における断面の構造を示す図である。なお、図２、図３において、封止樹脂は、理解の容易のため省略している。 FIG. 2 is a perspective view of a circuit board manufactured by the circuit board mother board and the circuit board manufacturing method according to the present embodiment. As shown in FIG. 2, the circuit board 20 includes a substantially rectangular parallelepiped base 9, a circuit region 21 formed on one surface of the base 9, and a wiring conductor at least partially formed in the circuit region 21. 2, a castellation electrode 6 provided on the side surface of the substrate 9, a wiring conductor 7 formed on the other surface of the substrate 9, and a sealing composition 8 at least partially formed on the wiring conductor 2 And at least a sealing resin for sealing the circuit region 21 as a main configuration. FIG. 3 is a diagram showing a cross-sectional structure in a plane passing through the castellation electrode 6 of FIG. 2 and 3, the sealing resin is omitted for easy understanding.
　基体９は、上述のように略直方体の形状をしており、互いに対向する一対の側面が複数個所略半円筒状に削られて凹部が形成されている。そして、それぞれ凹部の表面にキャスタレーション電極６が設けられており、それぞれのキャスタレーション電極６は、凹部に沿って、基体９の一方の表面から他方の表面まで延在している。つまり、キャスタレーション電極６は、スルーホールを孔の長さ方向に沿って分割した形状をしており、基体９の側面に対して、凹状の形状をしている。さらに、キャスタレーション電極６は、基体９の一方の面上に設けられる配線導体２と接続されており、さらに基体９の他方の面上に設けられる配線導体７とも接続されている。また、それぞれのキャスタレーション電極６と接続されているそれぞれの配線導体２は、基体９の一方の面上において、一部が基体９に設けられた凹部により円弧形に削られた矩形の形状をしている。同様に、それぞれのキャスタレーション電極６と接続されているぞれそれの配線導体７は、基体９の他方の面上において、一部が基体９に設けられた凹部により円弧形に削られた矩形の形状をしている。 The base body 9 has a substantially rectangular parallelepiped shape as described above, and a plurality of a pair of side surfaces facing each other are cut into a substantially semicylindrical shape to form a recess. A castellation electrode 6 is provided on the surface of each recess, and each castellation electrode 6 extends from one surface of the base 9 to the other surface along the recess. That is, the castellation electrode 6 has a shape in which the through hole is divided along the length direction of the hole, and has a concave shape with respect to the side surface of the base 9. Further, the castellation electrode 6 is connected to the wiring conductor 2 provided on one surface of the base 9, and is further connected to the wiring conductor 7 provided on the other surface of the base 9. Each wiring conductor 2 connected to each castellation electrode 6 has a rectangular shape in which a part of the wiring conductor 2 is cut into an arc shape by a recess provided in the base 9 on one surface of the base 9. I am doing. Similarly, each of the wiring conductors 7 connected to the respective castellation electrodes 6 was partially cut into an arc shape by a recess provided in the base 9 on the other surface of the base 9. It has a rectangular shape.
　また、上述のように基体９の一方の面には回路領域２１が形成されており、配線導体２の少なくとも１部は、この回路領域２１内まで延在している。回路領域２１は、少なくとも、回路基板２０に搭載する電子部品と接続するための配線導体２を有し、さらに回路基板と実装基板とを接続するための配線導体、スルーホール、ビアホールの何れかを有する場合がある。 Further, as described above, the circuit region 21 is formed on one surface of the base 9, and at least a part of the wiring conductor 2 extends into the circuit region 21. The circuit region 21 includes at least a wiring conductor 2 for connecting to an electronic component mounted on the circuit board 20, and further includes any of a wiring conductor, a through hole, and a via hole for connecting the circuit board and the mounting board. May have.
　図４は、図２の回路基板２０のキャスタレーション電極６の付近における側面図である。図２～図４に示すように、それぞれの配線導体２の一部と、それぞれのキャスタレーション電極６の一部は、封止組成物８により被覆されており、封止組成物８は、それぞれの配線導体２の表面から、それぞれのキャスタレーション電極６の凹部まで入り込んでいる。つまり、封止組成物８は、それぞれのキャスタレーション電極６における一方の表面側のみの凹部に充填されている。また、図４に示すように、凹部に入り込んでいる封止組成物８は、凹部の略中心において、最薄部とされており、厚さがａとされている。また、封止組成物８は、キャスタレーション電極６と接する位置において、最厚部とされており、厚さがｂとされている。また、封止組成物８は、配線導体２上においては、厚さがｆとされている。 FIG. 4 is a side view in the vicinity of the castellation electrode 6 of the circuit board 20 of FIG. As shown in FIGS. 2 to 4, a part of each wiring conductor 2 and a part of each castellation electrode 6 are covered with a sealing composition 8. From the surface of the wiring conductor 2 to the concave portion of each castellation electrode 6. That is, the sealing composition 8 is filled in the concave portions only on one surface side of each castellation electrode 6. Moreover, as shown in FIG. 4, the sealing composition 8 which has entered the recess is the thinnest portion at the approximate center of the recess, and the thickness is a. Further, the sealing composition 8 is the thickest portion at the position in contact with the castellation electrode 6 and the thickness is b. The sealing composition 8 has a thickness f on the wiring conductor 2.
　図５は、このような回路基板２０に電子部品１が搭載されて封止樹脂１３により封止された様子を示す図である。図５に示すように、電子部品１は、図示しない手段により基体９の一方の面上に固定されており、ボンディングワイヤ１１により配線導体２と電気的に接続されている。また、封止樹脂１３は、回路基板２０の表面と平行な表面が略平面状に形成されている。そして封止樹脂１３は、回路基板２０の回路領域２１から封止組成物８の表面まで封止している。 FIG. 5 is a view showing a state in which the electronic component 1 is mounted on the circuit board 20 and sealed with the sealing resin 13. As shown in FIG. 5, the electronic component 1 is fixed on one surface of the base 9 by means (not shown), and is electrically connected to the wiring conductor 2 by a bonding wire 11. Further, the sealing resin 13 has a surface substantially parallel to the surface of the circuit board 20 formed in a substantially flat shape. The sealing resin 13 seals from the circuit region 21 of the circuit board 20 to the surface of the sealing composition 8.
　図６は、図２に示す回路基板が実装されているキャスタレーション電極の様子を示す図である。図６に示すように、回路基板２０が実装基板上に配置されて、実装基板の端子１２と、配線導体７及びキャスタレーション電極６とがはんだ１５により接続されている。このはんだ付けを行う場合、キャスタレーション電極６を伝ってはんだが回路基板２０の配線導体２側に吸いあがってくる場合があるが、はんだ１５は、封止組成物８により、回路基板２０の配線導体２まで到達することが防止される。従って、このような回路基板２０によれば、基体を多層構造にしたり、電子部品の周囲にバリア層を設けるといった複雑な構成にすることをせずとも、実装時において、はんだによる不要な短絡等を防止することができる。 FIG. 6 is a diagram showing a state of the castellation electrode on which the circuit board shown in FIG. 2 is mounted. As shown in FIG. 6, the circuit board 20 is disposed on the mounting board, and the terminals 12 of the mounting board, the wiring conductors 7 and the castellation electrodes 6 are connected by solder 15. When performing this soldering, the solder may be sucked up to the wiring conductor 2 side of the circuit board 20 through the castellation electrode 6, but the solder 15 is used for the wiring of the circuit board 20 by the sealing composition 8. Reaching the conductor 2 is prevented. Therefore, according to such a circuit board 20, an unnecessary short circuit due to solder or the like is not required during mounting without having a complicated structure in which the base has a multilayer structure or a barrier layer is provided around the electronic component. Can be prevented.
　次に、このような回路基板２０を製造する製造方法について説明する。なお、以下の説明においては、図５に示すように電子部品１が回路基板２０に搭載されている場合について説明する。図７は、回路基板２０の製造方法を示すフローチャートである。 Next, a manufacturing method for manufacturing such a circuit board 20 will be described. In the following description, the case where the electronic component 1 is mounted on the circuit board 20 as shown in FIG. 5 will be described. FIG. 7 is a flowchart showing a method for manufacturing the circuit board 20.
　図７に示すように、回路基板２０の製造方法は、複数の回路領域２１、及び、複数のスルーホールを有する回路基板用母基板を準備する準備工程Ｐ１と、それぞれのスルーホールにおける開口の一方側のみを、封止組成物８により封止するスルーホール封止工程Ｐ２と、電子部品１を回路領域上に配置する部品配置工程Ｐ３と、それぞれの回路領域２１を封止樹脂１３により封止する回路封止工程Ｐ４と、複数のスルーホールに沿って回路基板用母基板を分割する分割工程Ｐ５とを主な工程として備える。 As shown in FIG. 7, the method of manufacturing the circuit board 20 includes a preparation step P1 for preparing a circuit board mother board having a plurality of circuit regions 21 and a plurality of through holes, and one of openings in each through hole. Through-hole sealing step P2 for sealing only the side with the sealing composition 8, component placement step P3 for placing the electronic component 1 on the circuit region, and sealing each circuit region 21 with the sealing resin 13 A circuit sealing process P4 to be performed and a dividing process P5 for dividing the circuit board mother board along the plurality of through holes are provided as main processes.
　なお、電子部品として機能する回路が回路基板２０の回路領域２１に形成されており、電子部品１を搭載する必要がない場合には、部品配置工程Ｐ３は不要である。 In addition, when the circuit which functions as an electronic component is formed in the circuit region 21 of the circuit board 20 and it is not necessary to mount the electronic component 1, the component placement step P3 is not necessary.
　（準備工程Ｐ１）
　準備工程Ｐ１は、基板準備工程Ｐ１ａと、孔あけ工程Ｐ１ｂと、導体形成工程Ｐ１ｃとを備える。 (Preparation process P1)
The preparation process P1 includes a substrate preparation process P1a, a drilling process P1b, and a conductor formation process P1c.
　（基板準備工程Ｐ１ａ）
　まず、回路基板用母基板の基となる基板３１を準備する。この基板は、最終的に回路基板２０の基体９となるものである。 (Substrate preparation process P1a)
First, a substrate 31 serving as a base for a circuit board mother board is prepared. This substrate finally becomes the base 9 of the circuit board 20.
　基板３１の材料としては、ポリイミド、ガラスエポキシ、ＢＴレジン（三菱瓦斯化学株式会社の登録商標）、セラミック等の一般的な配線基板に用いる材料を挙げることができる。また、この基板３１としては、耐久性の点から酸化アルミニウム質焼結体、窒化アルミニウム質焼結体、ムライト質焼結体、ガラスセラミックス等のセラミックを用いることが好ましい。また、本発明における基板３１の厚さは、特に限定されないが、強度、回路基板のサイズを考慮すると、１００μｍ～５，０００μｍであることが好ましい。また、基板３１は、単層基板、多層基板の何れであっても良いが、製造工程を簡略化できる点から単層基板を用いることが好ましい。 Examples of the material of the substrate 31 include materials used for general wiring substrates such as polyimide, glass epoxy, BT resin (registered trademark of Mitsubishi Gas Chemical Co., Ltd.), and ceramics. Moreover, as this board | substrate 31, it is preferable to use ceramics, such as an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, glass ceramics, from a durable point. In addition, the thickness of the substrate 31 in the present invention is not particularly limited, but is preferably 100 μm to 5,000 μm in view of strength and circuit board size. The substrate 31 may be either a single layer substrate or a multilayer substrate, but it is preferable to use a single layer substrate from the viewpoint that the manufacturing process can be simplified.
　なお、基板３１には、後の分割工程Ｐ５において、分割作業が容易となるように、分割ラインＬが設けられていることが好ましい。この分割ラインとは、分割工程Ｐ５において、複数の回路領域２１を有する回路基板用母基板を個々の回路領域に分割する位置を示すものである。 The substrate 31 is preferably provided with a dividing line L so that the dividing operation is facilitated in the subsequent dividing step P5. The dividing line indicates a position where the circuit board mother board having the plurality of circuit areas 21 is divided into individual circuit areas in the dividing step P5.
　（孔あけ工程Ｐ１ｂ）
　次に準備した基板３１に複数のスルーホールを形成するための複数の貫通孔３２をあける。貫通孔３２は、分割ラインＬ上に中心が位置するようにあけられる。この貫通孔３２は、基板に、パンチング、ドリル、レーザー加工等によって穿つことができる。また、基板準備工程Ｐ１ａの一部と孔あけ工程Ｐ１ｂの一部とを同時に行うことができる。例えば、基板３１としてアルミナ基板を用いる場合、焼成前のグリーシートにパンチング加工によって、貫通孔を穿ち、その後焼成することで、複数の貫通孔３２を有する基板３１とされる。一方、基板準備工程Ｐ１ａの一部と孔あけ工程Ｐ１ｂの一部とを同時に行わない場合には、焼成後のアルミナ基板にレーザーやドリル加工によって、貫通孔３２と穿つことができる。こうして、図８に示す複数の貫通孔３２が開けられた基板３１を得る。 (Drilling process P1b)
Next, a plurality of through holes 32 are formed in the prepared substrate 31 for forming a plurality of through holes. The through hole 32 is opened on the dividing line L so that the center is located. The through hole 32 can be formed in the substrate by punching, drilling, laser processing, or the like. Moreover, a part of substrate preparation process P1a and a part of drilling process P1b can be performed simultaneously. For example, when an alumina substrate is used as the substrate 31, the substrate 31 having a plurality of through holes 32 is formed by punching through holes in the green sheet before firing, and then firing the punched holes. On the other hand, when part of the substrate preparation process P1a and part of the drilling process P1b are not performed at the same time, the sintered alumina substrate can be drilled with the through holes 32 by laser or drilling. In this way, a substrate 31 having a plurality of through holes 32 shown in FIG. 8 is obtained.
　（導体形成工程Ｐ１ｃ）
　次に、孔あけ工程Ｐ１ｂにより形成された貫通孔３２の側面、及び、基板３１の表面における貫通孔３２の周囲に導体を形成する。この導体の形成によりスルーホール、及び、スルーホールと接続されている配線導体２、及び、配線導体７が形成される。スルーホール及び配線導体２、７を形成するための導電性材料としては、特に制限されないが、タングステン（Ｗ）、モリブデン（Ｍｏ）、ニッケル（Ｎｉ）、銅（Ｃｕ）、銀（Ａｇ）、金（Ａｕ）、パラジウム（Ｐｄ）、白金（Ｐｔ）等の金属を使用することができる。また、この導体は、メッキ、印刷、蒸着等によって基板３１上に被着させて形成することができる。さらに導体の厚さは１～３０μｍであることが好ましい。また、導体の酸化腐食を防止するために、導体の表面にＮｉ、Ａｕ、Ｐｔ等の耐食性に優れる金属を１～２０μｍ程度の厚みに被着させることが好ましい。こうして図９に示すように、配線導体２、及び、スルーホールが形成された回路基板用母基板３０を得る。 (Conductor formation process P1c)
Next, a conductor is formed around the through hole 32 on the side surface of the through hole 32 and the surface of the substrate 31 formed by the drilling step P1b. Through the formation of the conductor, the through hole, the wiring conductor 2 connected to the through hole, and the wiring conductor 7 are formed. The conductive material for forming the through hole and the wiring conductors 2 and 7 is not particularly limited, but tungsten (W), molybdenum (Mo), nickel (Ni), copper (Cu), silver (Ag), gold Metals such as (Au), palladium (Pd), and platinum (Pt) can be used. The conductor can be formed by being deposited on the substrate 31 by plating, printing, vapor deposition, or the like. Further, the thickness of the conductor is preferably 1 to 30 μm. In order to prevent oxidative corrosion of the conductor, it is preferable to deposit a metal having excellent corrosion resistance such as Ni, Au, Pt or the like on the surface of the conductor to a thickness of about 1 to 20 μm. Thus, as shown in FIG. 9, the wiring board 2 and the circuit board mother board 30 in which the through holes are formed are obtained.
　（スルーホール封止工程Ｐ２）
　次に封止組成物により、スルーホールにおける開口の一方側のみを封止する。スルーホール封止工程Ｐ２においては、封止組成物をスルーホールにおける開口の一方側に配置・固定することにより行うことができる。 (Through hole sealing process P2)
Next, only one side of the opening in the through hole is sealed with the sealing composition. In the through hole sealing step P2, the sealing composition can be arranged and fixed on one side of the opening in the through hole.
　このような封止組成物の材料としては、特に限定されないが、金属等の導電性材料や、ガラス、絶縁性樹脂等の絶縁性材料等を挙げることができ、中でも、絶縁性材料を用いることが好ましく、作業性および耐久性の点からガラス組成物を用いることが特に好ましい。封止組成物として、絶縁性樹脂を用いる場合、例えば、熱可塑性樹脂や熱硬化性樹脂を用いれば良い。封止組成物として、熱可塑性樹脂を用いる場合は、加熱して可塑化した樹脂をスルーホールにおける一方の開口側から塗布して、その後冷却することで固化させて、スルーホールを封止することができる。また、封止組成物として、熱硬化性樹脂を用いる場合は、未硬化状態の樹脂をスルーホールにおける一方の開口側から塗布して、その後加熱することで固化させて、スルーホールを封止することができる。なお、封止組成物としてこのような絶縁性樹脂を用いる場合には、絶縁性樹脂を塗布するときに、スルーホールを通じて基板の反対側まで絶縁性樹脂が流れ落ちないように、絶縁性樹脂が一定の粘度を有するように調整しておく。さらに、封止組成物としてガラス組成物を用いる場合、ガラス粉末、バインダー、溶剤等を含むガラスペーストをスルーホールにおける一方の開口側から塗布して、その後乾燥固化させることにより、スルーホールを封止することができる。なお、ガラスペーストには、酸化ケイ素、アルミナ等の充填剤を含有させることができる。また、基板３１が耐熱性を有する場合においては、ガラスペーストを塗布後に焼成することが好ましい。このように焼成を行うことで、ガラス組成物が基板に強固に固定される。こうして、図１０に示す、スルーホールが封止組成物８で封止された回路基板用母基板３０を得る。 The material of such a sealing composition is not particularly limited, and examples thereof include conductive materials such as metals, and insulating materials such as glass and insulating resin. Among them, insulating materials are used. It is particularly preferable to use a glass composition from the viewpoint of workability and durability. When an insulating resin is used as the sealing composition, for example, a thermoplastic resin or a thermosetting resin may be used. When a thermoplastic resin is used as the sealing composition, the resin plasticized by heating is applied from one opening side of the through hole and then solidified by cooling to seal the through hole Can do. Further, when a thermosetting resin is used as the sealing composition, an uncured resin is applied from one opening side of the through hole and then solidified by heating to seal the through hole. be able to. When such an insulating resin is used as the sealing composition, the insulating resin is constant so that the insulating resin does not flow down to the opposite side of the substrate through the through hole when the insulating resin is applied. It adjusts so that it may have the following viscosity. Furthermore, when using a glass composition as the sealing composition, a glass paste containing glass powder, a binder, a solvent, etc. is applied from one opening side of the through hole, and then dried and solidified to seal the through hole. can do. The glass paste can contain fillers such as silicon oxide and alumina. Further, when the substrate 31 has heat resistance, it is preferable to bake after applying the glass paste. By firing in this way, the glass composition is firmly fixed to the substrate. In this way, the circuit board mother board 30 shown in FIG. 10 in which the through holes are sealed with the sealing composition 8 is obtained.
　図１１は、図１０の回路基板用母基板３０のスルーホールにおける断面の様子を示す図である。具体的には、図１１の（Ａ）～（Ｃ）は、スルーホールの断面における封止組成物８の形状が異なる状態を示しており、図１１の（Ａ）は、封止組成物８の底面が上がっている様子を示し、図１１の（Ｂ）は、封止組成物８の底面が下がっている様子を示し、図１１の（Ｃ）は、封止組成物８がスルーホールの中心からずれている様子を示す。 FIG. 11 is a view showing a state of a cross section in the through hole of the circuit board mother board 30 of FIG. Specifically, FIGS. 11A to 11C show states in which the shape of the sealing composition 8 in the cross section of the through hole is different, and FIG. 11A shows the sealing composition 8. 11 (B) shows a state where the bottom surface of the sealing composition 8 is lowered, and FIG. 11 (C) shows a state where the sealing composition 8 is a through-hole. Shown off center.
　図１１の（Ａ）に示すように、分割ラインＬに沿って設けられ封止組成物８で封止されたスルーホールにおいて、分割ラインＬと基板３１に設けられた貫通孔３２の内壁面（スルーホールの導体の外周面）とが最も離れている距離ｃは、５０～３００μｍであることが好ましい。分割ラインＬと貫通孔３２の内壁面との最大距離が５０μｍ以上であれば、導体形成工程Ｐ１ｃにおいて、貫通孔３２がスルーホールを形成する導体で密閉されることが抑制される。仮に、貫通孔３２がスルーホールを形成する導体で密閉されてしまうと、後の分割工程Ｐ５において、回路基板用母基板３０を分割する時にスルーホールの導体が、基板から剥離することがあり好ましくない。一方、分割ラインＬとスルーホール内壁面との最大距離が３００μｍ以下であれば、スルーホール封止工程Ｐ２において、封止組成物８でスルーホールをより適切に封止できるので好ましい。 As shown in FIG. 11A, in the through hole provided along the dividing line L and sealed with the sealing composition 8, the inner wall surface of the through hole 32 provided in the dividing line L and the substrate 31 ( The distance c that is farthest from the outer peripheral surface of the conductor of the through hole is preferably 50 to 300 μm. If the maximum distance between the dividing line L and the inner wall surface of the through hole 32 is 50 μm or more, the through hole 32 is prevented from being sealed with a conductor that forms a through hole in the conductor forming step P1c. If the through hole 32 is sealed with a conductor that forms a through hole, the through hole conductor may be peeled off from the substrate when the circuit board mother board 30 is divided in the subsequent division step P5. Absent. On the other hand, if the maximum distance between the dividing line L and the inner wall surface of the through hole is 300 μm or less, it is preferable because the through hole can be more appropriately sealed with the sealing composition 8 in the through hole sealing step P2.
　また、図１１の（Ａ）～（Ｃ）に示すように、スルーホール内における封止組成物８の最薄部ａは、５～５００μｍの厚さであることが好ましい。スルーホールを封止する封止組成物８の最薄部ａが５μｍ以上であれば、後の回路封止工程Ｐ４において、電子部品等を密閉保護する封止樹脂を塗布する際、封止組成物８の最薄部が破断することを適切に防止することができる。一方、スルーホールを封止する封止組成物８の最薄部ａが５００μｍを以下であれば、後の分割工程Ｐ５において、回路基板用母基板３０の分割が容易であるので好ましい。 Further, as shown in FIGS. 11A to 11C, the thinnest portion a of the sealing composition 8 in the through hole is preferably 5 to 500 μm thick. If the thinnest part a of the sealing composition 8 that seals the through hole is 5 μm or more, the sealing composition is applied when applying a sealing resin that hermetically protects electronic components and the like in the subsequent circuit sealing step P4. It is possible to appropriately prevent the thinnest part of the object 8 from breaking. On the other hand, if the thinnest part a of the sealing composition 8 for sealing the through hole is 500 μm or less, it is preferable because the circuit board mother board 30 can be easily divided in the subsequent dividing step P5.
　また、スルーホールを封止する封止組成物８の最薄部ａは、図１１の（Ａ）、（Ｂ）に示すように、回路基板用母基板３０を各回路領域に分割することを容易にするため、分割ラインＬ付近に存在することが好ましく、分割ライン上に存在することがより好ましい。 Further, the thinnest part a of the sealing composition 8 for sealing the through-hole is to divide the circuit board mother board 30 into each circuit area as shown in FIGS. In order to facilitate, it is preferable that it exists in the vicinity of the dividing line L, and it is more preferable that it exists on the dividing line.
　図１１の（Ａ）～（Ｃ）に示すように、スルーホールを封止する封止組成物８の最厚部ｂは、スルーホールの内壁部付近にあることが好ましく、特に、最厚部ｂは、スルーホールの内壁面に接する位置に存在することが好ましい。封止組成物８の最厚部ｂがスルーホールの内壁面に接する位置に存在すれば、封止組成物８とスルーホールの内壁面との接触面積が大きくなり、封止組成物８とスルーホールの内壁面との密着性を高くすることができ、後の分割工程Ｐ５において、回路基板用母基板３０の分割時に封止組成物８がスルーホールの内壁面から剥離することを防止することができる。 As shown in FIGS. 11A to 11C, the thickest portion b of the sealing composition 8 for sealing the through hole is preferably in the vicinity of the inner wall portion of the through hole. b is preferably present at a position in contact with the inner wall surface of the through hole. If the thickest part b of the sealing composition 8 is present at a position in contact with the inner wall surface of the through hole, the contact area between the sealing composition 8 and the inner wall surface of the through hole is increased. Adhesion with the inner wall surface of the hole can be increased, and the sealing composition 8 can be prevented from peeling off from the inner wall surface of the through-hole when the circuit board mother board 30 is divided in the subsequent dividing step P5. Can do.
　また、封止組成物８は、スルーホールの深さ方向において１～８５％付着していることが好ましい。図１１に示すように、スルーホール内に付着している封止組成物８が、深さ方向において、スルーホールの１％以上であれば、封止組成物８とスルーホールの内壁面との密着性を十分確保することができる。従って、回路封止工程Ｐ４において、電子部品等を密閉保護する封止樹脂を塗布するときに、スルーホールの内壁面から封止組成物８が脱落することをより適切に防止することができ、さらに、分割工程Ｐ５において、回路基板用母基板３０の分割時に、封止組成物８がスルーホール内壁面から剥離することをより適切に防止することができる。一方、スルーホール内に付着している封止組成物８が、深さ方向において、スルーホールの８５％以下であれば、分割工程Ｐ５の後において、回路基板２０のキャスタレーション電極６をより十分に露出させることができる。 Moreover, it is preferable that 1 to 85% of the sealing composition 8 adheres in the depth direction of the through hole. As shown in FIG. 11, if the sealing composition 8 adhering in the through hole is 1% or more of the through hole in the depth direction, the sealing composition 8 and the inner wall surface of the through hole Adhesion can be sufficiently secured. Therefore, in the circuit sealing step P4, when applying a sealing resin that hermetically protects electronic components and the like, it is possible to more appropriately prevent the sealing composition 8 from dropping from the inner wall surface of the through hole. Furthermore, in the dividing step P5, it is possible to more appropriately prevent the sealing composition 8 from peeling from the inner wall surface of the through hole when the circuit board mother board 30 is divided. On the other hand, if the sealing composition 8 adhering in the through hole is 85% or less of the through hole in the depth direction, the castellation electrode 6 of the circuit board 20 is more sufficiently formed after the dividing step P5. Can be exposed to.
　また、封止組成物８は、スルーホールの端部から、深さ方向において、５～５００μｍスルーホールの内壁面に付着していることが好ましい。図２に示すように、スルーホール内に充填された封止組成物８が、スルーホールの一方側の開口から５μｍ以上付着していれば、封止組成物８とスルーホールの内壁面との密着性を十分確保することができる。従って、回路封止工程Ｐ４において、電子部品等を密閉保護する封止樹脂を塗布するときに、スルーホールの内壁面から封止組成物が脱落することをより適切に防止することができ、さらに、分割工程Ｐ５において、回路基板用母基板３０の分割時に、封止組成物８がスルーホール内壁面から剥離することをより適切に防止することができる。一方、スルーホール内に侵入した封止組成物８がスルーホールの内壁面に付着する深さが、スルーホールの端部から５００μｍ以下であれば、分割工程Ｐ５の後において、回路基板２０のキャスタレーション電極６をより十分に露出させることができる。 The sealing composition 8 is preferably attached to the inner wall surface of the 5 to 500 μm through hole in the depth direction from the end of the through hole. As shown in FIG. 2, if the sealing composition 8 filled in the through hole adheres to the opening from one side of the through hole by 5 μm or more, the sealing composition 8 and the inner wall surface of the through hole Adhesion can be sufficiently secured. Therefore, in the circuit sealing step P4, when applying a sealing resin that hermetically protects electronic components and the like, it is possible to more appropriately prevent the sealing composition from dropping from the inner wall surface of the through hole. In the dividing step P5, it is possible to more appropriately prevent the sealing composition 8 from being peeled off from the inner wall surface of the through hole when the circuit board mother board 30 is divided. On the other hand, if the depth at which the sealing composition 8 that has entered the through hole adheres to the inner wall surface of the through hole is 500 μm or less from the end of the through hole, the caster of the circuit board 20 is obtained after the dividing step P5. The exposure electrode 6 can be exposed more sufficiently.
　また、スルーホール内に充填された封止組成物８の深さが最大となる部分は、スルーホールの内壁部付近にあることが好ましく、さらに、図１１の（Ａ）に示すように、スルーホール内に充填された封止組成物８の深さが最大となる部分は、スルーホールを封止する封止組成物８の最厚部ｂと一致することが好ましい。この場合、封止組成物８とスルーホール内壁面との密着性が高くなり、分割工程Ｐ５における回路基板用母基板３０の分割時に封止組成物８がスルーホールの内壁部から剥離することを防止することができる。 Further, the portion where the depth of the sealing composition 8 filled in the through hole is maximum is preferably in the vicinity of the inner wall portion of the through hole. Further, as shown in FIG. It is preferable that the portion where the depth of the sealing composition 8 filled in the hole is maximum coincides with the thickest portion b of the sealing composition 8 that seals the through hole. In this case, the adhesiveness between the sealing composition 8 and the inner wall surface of the through hole is increased, and the sealing composition 8 is peeled off from the inner wall portion of the through hole when the circuit board mother board 30 is divided in the dividing step P5. Can be prevented.
　また、スルーホールを封止する封止組成物８は、図１１の（Ａ）～（Ｃ）に示すように、回路基板用母基板３０の表面の配線導体２の一部分を被覆するように設けることが望ましい。配線導体２の一部分を封止組成物８で被覆することにより、回路領域２１を封止する封止樹脂と配線導体２との密着性が向上し、封止樹脂が剥離することを抑制することができる。特に、配線導体２の表面がＡｕの場合、配線導体２の一部分を封止組成物８で被覆することにより、封止樹脂と配線導体２との密着性を著しく向上させることができる。 Further, as shown in FIGS. 11A to 11C, the sealing composition 8 for sealing the through holes is provided so as to cover a part of the wiring conductor 2 on the surface of the circuit board mother board 30. It is desirable. By covering a part of the wiring conductor 2 with the sealing composition 8, the adhesion between the sealing resin for sealing the circuit region 21 and the wiring conductor 2 is improved, and the sealing resin is prevented from peeling off. Can do. In particular, when the surface of the wiring conductor 2 is Au, the adhesiveness between the sealing resin and the wiring conductor 2 can be remarkably improved by covering a part of the wiring conductor 2 with the sealing composition 8.
　（部品配置工程Ｐ３）
　次に、回路領域２１に電子部品を配置する必要がある場合には、電子部品を配置する。電子部品の配置においては、電子部品を回路領域２１に配置した後、電子部品の端子と配線導体２とを電気的に接続する。この電気的な接続には、図５に示すようにワイヤーボンディングにより、電子部品の端子と配線導体２とを接続しても良く、配線導体２上に電子部品の端子を配置して導電性ペーストやはんだで接続しても良い。 (Part placement process P3)
Next, when it is necessary to arrange an electronic component in the circuit area 21, the electronic component is arranged. In the arrangement of the electronic component, after the electronic component is arranged in the circuit region 21, the terminal of the electronic component and the wiring conductor 2 are electrically connected. For this electrical connection, as shown in FIG. 5, the terminal of the electronic component and the wiring conductor 2 may be connected by wire bonding, and the terminal of the electronic component is placed on the wiring conductor 2 to form a conductive paste. You may connect with solder.
　（回路封止工程Ｐ４）
　次に、回路領域２１を封止樹脂により封止する。封止樹脂に用いる樹脂としては、熱可塑性樹脂や、熱硬化性樹脂や、紫外線硬化樹脂を挙げることができ、具体的には、エポキシ系樹脂、シリコーン系樹脂、ポリオレフィン系樹脂、ポリアミド系樹脂、ポリイミド系樹脂、ウレタン系樹脂等の樹脂を挙げることができる。熱可塑性樹脂により封止を行う場合には、回路領域２１に、加熱されて可塑化した熱可塑性樹脂を塗布して、その後冷却・固化することにより回路領域２１の封止を行う。熱硬化性樹脂により封止を行う場合には、未硬化状態の熱硬化性樹脂を回路領域２１に塗布して、その後、加熱して固化することにより回路領域２１の封止を行う。紫外線硬化樹脂を用いる場合には、紫外線硬化樹脂の前駆体である紫外線硬化性樹脂をを回路領域２１に塗布して、その後、紫外線を照射して固化することにより、回路領域２１の封止を行う。こうして、回路領域２１が封止樹脂により封止された状態の回路基板用母基板を得る。 (Circuit sealing process P4)
Next, the circuit region 21 is sealed with a sealing resin. Examples of the resin used for the sealing resin include thermoplastic resins, thermosetting resins, and ultraviolet curable resins. Specifically, epoxy resins, silicone resins, polyolefin resins, polyamide resins, Examples thereof include resins such as polyimide resins and urethane resins. When sealing with a thermoplastic resin, the circuit area 21 is sealed by applying a thermoplastic resin that has been heated and plasticized to the circuit area 21, and then cooling and solidifying. In the case of sealing with a thermosetting resin, the circuit region 21 is sealed by applying an uncured thermosetting resin to the circuit region 21 and then solidifying by heating. In the case of using an ultraviolet curable resin, an ultraviolet curable resin, which is a precursor of the ultraviolet curable resin, is applied to the circuit region 21 and then solidified by irradiation with ultraviolet rays, thereby sealing the circuit region 21. Do. Thus, a circuit board mother board in which the circuit region 21 is sealed with the sealing resin is obtained.
　（分割工程Ｐ５）
　次に、スルーホールの貫通孔３２の一方側のみが、封止組成物８により封止された回路基板用母基板３０を分割する。分割は、スルーホールを通るようにして、レーザーやダイシングにより、複数の回路領域に分割すれば良い。上述のように、分割工程Ｐ５を容易にするため、準備工程Ｐ１おいて準備する基板の少なくとも一方の面に、分割ラインを設けておくことが好ましい。回路基板用母基板３０を分割する際には、この分割ラインＬに沿って、上述のようにレーザーまたはダイシングによって分割すれば良い。さらに回路基板用母基板３０の少なくとも一方の面に分割ラインＬに沿って分割溝が形成されていることが好ましい。このように分割溝を設ける場合は、基板準備工程Ｐ１ａにおいて、分割溝を有する基板３１を準備すれば良い。このように分割溝が設けられている場合の分割する方法としては、設けられた分割溝に沿って回路基板用母基板３０を破断することが挙げられる。 (Division process P5)
Next, only one side of the through hole 32 of the through hole divides the circuit board mother board 30 sealed with the sealing composition 8. The division may be divided into a plurality of circuit regions by laser or dicing so as to pass through the through holes. As described above, in order to facilitate the division step P5, it is preferable to provide a division line on at least one surface of the substrate prepared in the preparation step P1. When the circuit board mother board 30 is divided, it may be divided along the dividing line L by laser or dicing as described above. Further, it is preferable that a dividing groove is formed along the dividing line L on at least one surface of the circuit board mother board 30. In the case where the dividing grooves are provided in this way, the substrate 31 having the dividing grooves may be prepared in the substrate preparation step P1a. As a method of dividing in the case where the dividing grooves are provided in this way, there is a method of breaking the circuit board mother board 30 along the provided dividing grooves.
　こうして、回路基板用母基板３０をそれぞれの回路基板２０に分割することにより、図２に示す回路基板２０を得る。 In this way, the circuit board 20 shown in FIG. 2 is obtained by dividing the circuit board mother board 30 into the respective circuit boards 20.
　以下、本発明における複数の回路領域２１を有する多数個取りの回路基板用母基板、およびその回路基板用母基板から得られた回路基板の実施例を示すが、本発明は下記実施例に何ら限定されるものではない。 Hereinafter, examples of a multi-chip circuit board mother board having a plurality of circuit regions 21 in the present invention and circuit boards obtained from the circuit board mother board will be described. The present invention is not limited to the following examples. It is not limited.
　（実施例１）
　電子部品を搭載するための回路基板を次のようにして製造した。基板として、分割ラインとして５ｍｍの間隔で深さ０．１５ｍｍのＶ字型の分割溝が設けられ、さらに、この分割ライン上に予めΦ０．３ｍｍの貫通孔が形成されたアルミナ基板（北陸セラミック社製：アルミナ純度９６％、厚さ０．５ｍｍ、大きさ６０ｍｍ×７０ｍｍ）を準備した。このアルミナ基板の配線導体とスルーホール導体を設ける位置に、導体ペースト（京都エレックス社製、グレード名「ＤＤ１１３０」）をスクリーン印刷にて塗布した。この時、スルーホール導体は、スクリーン印刷時において、基板の印刷する面と反対側の面から吸引しながら塗布した。印刷終了後、基板を５０℃の温度で１０分間乾燥し、その後、基板を最高温度８５０℃で１０分間保持することにより焼成して、厚さ１２μｍの銀系の配線導体を有する回路基板用母基板を作製した。 Example 1
A circuit board for mounting electronic components was manufactured as follows. As a substrate, an alumina substrate (Hokuriku Ceramic Co., Ltd.) having V-shaped dividing grooves with a depth of 0.15 mm provided as dividing lines at intervals of 5 mm and having a through hole of Φ0.3 mm formed on the dividing lines in advance. Manufactured: alumina purity 96%, thickness 0.5 mm, size 60 mm × 70 mm). A conductor paste (manufactured by Kyoto Elex, grade name “DD1130”) was applied by screen printing at a position where the wiring conductor and through-hole conductor of the alumina substrate were provided. At this time, the through-hole conductor was applied while sucking from the surface opposite to the surface to be printed of the substrate during screen printing. After the printing is completed, the substrate is dried at a temperature of 50 ° C. for 10 minutes, and then fired by holding the substrate at a maximum temperature of 850 ° C. for 10 minutes to obtain a mother board for a circuit board having a silver wiring conductor having a thickness of 12 μm. A substrate was produced.
　次いで、上記基板の封止組成物を設ける位置（スルーホールの開口が形成されている位置を含む）にガラスペースト（旭硝子株式会社製、グレード名「ＡＰ５７００」）を塗布し、１５０℃の温度で２０分間乾燥させた。その後、昇温して最高温度８５０℃で１０分間保持することにより焼成して、封止組成物として厚さ３５μｍのガラス層が形成された回路基板用母基板を得た。 Next, a glass paste (made by Asahi Glass Co., grade name “AP5700”) is applied to the position where the sealing composition for the substrate is provided (including the position where the opening of the through hole is formed), and the temperature is 150 ° C. Dry for 20 minutes. Thereafter, the substrate was fired by raising the temperature and holding it at a maximum temperature of 850 ° C. for 10 minutes to obtain a mother board for circuit board on which a glass layer having a thickness of 35 μm was formed as a sealing composition.
　次に、得られた回路基板用母基板を、Ｖ字型の分割溝に沿って、それぞれ回路基板に分割したところ、基板にバリもなくガラス層もスルーホールのほぼ中央で割れ分割性は良好であった。さらに、分割断面を顕微鏡で観察したところ、ガラス層によりスルーホールが片側から封止されていることが確認できた。 Next, when the obtained circuit board mother board was divided into circuit boards along the V-shaped dividing grooves, the substrate was free of burrs, and the glass layer was almost split in the center of the through-hole and had good splitting ability. Met. Furthermore, when the divided cross section was observed with a microscope, it was confirmed that the through hole was sealed from one side by the glass layer.
　本実施例における回路基板用母基板において、得られた回路基板の各部位を複数個所測定したところ、図４の各部位に相当する部分のサイズは以下の通りであった。
ａ：０．１２～０．１６ｍｍ
ｂ：０．３０～０．１６ｍｍ
ｃ：０．１４５ｍｍ（２ｃ：０．２９０ｍｍ）
ｅ：０．５０ｍｍ
ｆ：０．０３～０．０３５ｍｍ In the circuit board mother board of this example, when a plurality of portions of the obtained circuit board were measured, the sizes of the portions corresponding to the respective portions in FIG. 4 were as follows.
a: 0.12 to 0.16 mm
b: 0.30 to 0.16 mm
c: 0.145 mm (2c: 0.290 mm)
e: 0.50 mm
f: 0.03 to 0.035 mm
　（実施例２）
　基体となるセラミック板を、厚さを０．３ｍｍとし、貫通孔の直径を０．２ｍｍとし、Ｖ字型の分割溝の間隔が３ｍｍである基板を用いたこと以外は実施例１と同様にして回路基板用母基板を作製した。この基板をＶ字型の分割溝に沿って回路基板に分割したところ、基板にバリもなくガラスもスルーホールのほぼ中央で割れ分割性は良好であった。 (Example 2)
The ceramic plate used as the base was the same as in Example 1 except that a substrate having a thickness of 0.3 mm, a through-hole diameter of 0.2 mm, and a V-shaped dividing groove interval of 3 mm was used. Thus, a circuit board mother board was produced. When this substrate was divided into circuit substrates along the V-shaped dividing grooves, there was no burr on the substrate, and the glass also had good crack division at the center of the through hole.
　本実施例における回路基板用母基板において、得られた回路基板の各部位を複数個所測定したところ、図４の各部位に相当する部分のサイズは以下の通りであった。
ａ：０．１０～０．１３ｍｍ
ｂ：０．１７～０．１９ｍｍ
ｃ：０．１０５ｍｍ（２ｃ：０．２１０ｍｍ）
ｅ：０．３１ｍｍ
ｆ：０．０３～０．０３５ｍｍ In the circuit board mother board of this example, when a plurality of portions of the obtained circuit board were measured, the sizes of the portions corresponding to the respective portions in FIG. 4 were as follows.
a: 0.10 to 0.13 mm
b: 0.17 to 0.19 mm
c: 0.105 mm (2c: 0.210 mm)
e: 0.31 mm
f: 0.03 to 0.035 mm
　次に、実施例１、実施例２で作製した回路基板用母基板に、電子部品としてＬＥＤを搭載しボンディングワイヤで配線導体と接続した。次いで、エポキシ系封止樹脂をモールド印刷してＬＥＤを封止した。この母基板をＶ字型の分割溝に沿って回路基板用に分割し、分割断面を顕微鏡で観察した。その結果、キャスタレーション電極となる部位にエポキシ系封止樹脂の付着は認められず、ガラス層によって封止樹脂の漏出が防止されていることが確認された。さらに、回路基板を実装基板へはんだ付けしたところ、良好なはんだフィレットが形成された。 Next, an LED was mounted as an electronic component on the circuit board mother board produced in Example 1 and Example 2, and connected to the wiring conductor with a bonding wire. Next, the epoxy sealing resin was mold printed to seal the LED. The mother board was divided for a circuit board along a V-shaped dividing groove, and the divided cross section was observed with a microscope. As a result, it was confirmed that no adhesion of the epoxy-based sealing resin was observed at the site serving as the castellation electrode, and leakage of the sealing resin was prevented by the glass layer. Furthermore, when the circuit board was soldered to the mounting board, a good solder fillet was formed.
　以上より、実施例１、実施例２の回路基板用母基板では、キャスタレーション電極が適切に露出している回路基板を得られることが分かった。 From the above, it was found that the circuit boards with the castellation electrodes appropriately exposed can be obtained from the circuit board motherboards of Example 1 and Example 2.
　本発明によれば、簡便な方法によりキャスタレーション電極が適切に露出している回路基板を得ることができる回路基板の製造方法、及び、これにより製造される回路基板、及び、これに用いられる回路基板用母基板が提供される。 According to the present invention, a circuit board manufacturing method capable of obtaining a circuit board in which castellation electrodes are appropriately exposed by a simple method, a circuit board manufactured thereby, and a circuit used therefor A mother board for a substrate is provided.
　１・・・電子部品
　２・・・配線導体
　６・・・キャスタレーション電極
　７・・・配線導体
　８・・・封止組成物
　９・・・基体
　１１・・・ボンディングワイヤ
　１２・・・端子
　１３・・・封止樹脂
　１５・・・はんだ
　２０・・・回路基板
　２１・・・回路領域
　３０・・・回路基板用母基板
　３１・・・基板
　３２・・・貫通孔
　１００・・・回路基板
　１０１・・・電子部品
　１０２・・・配線導体
　１０５・・・基体
　１０６・・・キャスタレーション電極
　１０７・・・配線導体
　Ｌ・・・分割ライン
　Ｐ１・・・準備工程
　Ｐ１ａ・・・基板準備工程
　Ｐ１ｂ・・・孔あけ工程
　Ｐ１ｃ・・・導体形成工程
　Ｐ２・・・スルーホール封止工程
　Ｐ３・・・部品配置工程
　Ｐ４・・・回路封止工程
　Ｐ５・・・分割工程
  DESCRIPTION OF SYMBOLS 1 ... Electronic component 2 ... Wiring conductor 6 ... Castoration electrode 7 ... Wiring conductor 8 ... Sealing composition 9 ... Base | substrate 11 ... Bonding wire 12 ... Terminal 13 ... Sealing resin 15 ... Solder 20 ... Circuit board 21 ... Circuit area 30 ... Mother board for circuit board 31 ... Substrate 32 ... Through hole 100 ... Circuit board 101 ... Electronic components 102 ... Wiring conductor 105 ... Substrate 106 ... Castellation electrode 107 ... Wiring conductor L ... Division line P1 ... Preparation process P1a ... Board preparation process P1b・ ・ Punching process P1c ・ ・ ・ Conductor forming process P2 ・ ・ ・ Through hole sealing process P3 ・ ・ ・ Part placement process P4 ・ ・ ・ Circuit sealing process P5 ・ ・ ・ Division process

Claims (17)

  1. 　複数の回路領域、及び、複数のスルーホールを有する回路基板用母基板を準備する準備工程と、
    　それぞれの前記スルーホールにおける開口の一方側のみを、封止組成物により封止するスルーホール封止工程と、
    　それぞれの前記回路領域を封止樹脂により封止する回路封止工程と、
    　前記複数のスルーホールに沿って前記母基板を分割する分割工程と、
    を備えることを特徴とする回路基板の製造方法。     Preparing a circuit board mother board having a plurality of circuit regions and a plurality of through holes; and
    A through hole sealing step of sealing only one side of the opening in each through hole with a sealing composition;
    A circuit sealing step of sealing each of the circuit regions with a sealing resin;
    A dividing step of dividing the mother board along the plurality of through holes;
    A method of manufacturing a circuit board, comprising:
  2. 　前記封止組成物がガラス組成物であり、前記スルーホール封止工程において、前記回路基板用母基板にガラスペーストを塗布して、前記ガラスペーストが塗布された前記回路基板用母基板を焼成することを特徴とする請求項１に記載の回路基板の製造方法。 The sealing composition is a glass composition, and in the through-hole sealing step, a glass paste is applied to the circuit board mother substrate, and the circuit board mother substrate coated with the glass paste is baked. The method for manufacturing a circuit board according to claim 1.
  3. 　前記封止組成物は、前記スルーホールの内壁面に接する位置における厚さが、前記スルーホールの径方向の中心部における厚さよりも大きいことを特徴とする請求項１または２に記載の回路基板の製造方法。 3. The circuit board according to claim 1, wherein a thickness of the sealing composition at a position in contact with an inner wall surface of the through hole is larger than a thickness at a central portion in a radial direction of the through hole. Manufacturing method.
  4. 　前記スルーホール内の前記封止組成物は、前記スルーホールの内壁面に接する位置において最厚部が形成されていることを特徴とする請求項１～３のいずれか１項に記載の回路基板の製造方法。 The circuit board according to any one of claims 1 to 3, wherein the sealing composition in the through hole has a thickest portion formed at a position in contact with an inner wall surface of the through hole. Manufacturing method.
  5. 　前記スルーホール内の前記封止組成物は、前記スルーホールの径方向における中心部において、最薄部が形成されていることを特徴とする請求項３または４に記載の回路基板の製造方法。 The method for manufacturing a circuit board according to claim 3 or 4, wherein the sealing composition in the through hole has a thinnest portion formed at a central portion in a radial direction of the through hole.
  6. 　前記回路基板用母基板がセラミックからなることを特徴とする請求項１～５のいずれか１項に記載の回路基板の製造方法。 6. The circuit board manufacturing method according to claim 1, wherein the circuit board mother board is made of ceramic.
  7. 　前記回路基板用母基板が単層基板からなることを特徴とする請求項１～６のいずれか１項に記載の回路基板の製造方法。 The method for manufacturing a circuit board according to any one of claims 1 to 6, wherein the mother board for a circuit board comprises a single-layer board.
  8. 　請求項１～７のいずれか１項に記載の回路基板の製造方法により製造されることを特徴とする回路基板。 A circuit board manufactured by the method for manufacturing a circuit board according to any one of claims 1 to 7.
  9. 　複数の回路領域、及び、複数のスルーホールを有し、前記複数のスルーホールに沿って分割される回路基板用母基板であって、
    　それぞれの前記スルーホールは、開口の一方側のみが、封止組成物により封止されている
    ことを特徴とする回路基板用母基板。     A circuit board mother board having a plurality of circuit regions and a plurality of through holes, and being divided along the plurality of through holes,
    Each of the through holes is a circuit board motherboard, wherein only one side of the opening is sealed with a sealing composition.
  10. 　前記封止組成物がガラス組成物であることを特徴とする請求項９に記載の回路基板用母基板。 10. The circuit board mother board according to claim 9, wherein the sealing composition is a glass composition.
  11. 　前記封止組成物は、前記スルーホールの内壁面に接する位置における厚さが、前記スルーホールの径方向の中心部における厚さよりも大きいことを特徴とする請求項９または１０に記載の回路基板用母基板。 11. The circuit board according to claim 9, wherein a thickness of the sealing composition at a position in contact with an inner wall surface of the through hole is larger than a thickness at a central portion in a radial direction of the through hole. Mother board.
  12. 　前記スルーホール内の前記封止組成物は、前記スルーホールの内壁面に接する位置において最厚部が形成されていることを特徴とする請求項９～１１のいずれか１項に記載の回路基板用母基板。 The circuit board according to any one of claims 9 to 11, wherein the sealing composition in the through hole has a thickest portion formed at a position in contact with an inner wall surface of the through hole. Mother board.
  13. 　前記スルーホール内の前記封止組成物は、前記スルーホールの径方向における中心部において、最薄部が形成されていることを特徴とする請求項１１または１２に記載の回路基板用母基板。 13. The mother board for a circuit board according to claim 11 or 12, wherein the sealing composition in the through hole has a thinnest portion formed at a central portion in a radial direction of the through hole.
  14. 　前記複数のスルーホールと重なる位置に沿って、分割ラインが形成れていることを特徴とする請求項９～１３のいずれか１項に記載の回路基板用母基板。 The circuit board mother board according to any one of claims 9 to 13, wherein a dividing line is formed along a position overlapping with the plurality of through holes.
  15. 　少なくとも一方の面に前記分割ラインに沿って分割溝が形成されていることを特徴とする請求項１４に記載の回路基板用母基板。 15. The mother board for circuit boards according to claim 14, wherein a dividing groove is formed along at least one surface along the dividing line.
  16. 　セラミックからなることを特徴とする請求項８～１５のいずれか１項に記載の回路基板用母基板。 The circuit board mother board according to any one of claims 8 to 15, wherein the board is made of ceramic.
  17. 　単層基板からなることを特徴とする請求項８～１６のいずれか１項に記載の回路基板用母基板。 The circuit board mother board according to any one of claims 8 to 16, wherein the board is a single-layer board.
PCT/JP2010/059569 2009-06-08 2010-06-06 Method for manufacturing circuit board, circuit board manufactured by the method, and base substrate used for the circuit board WO2010143597A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011518522A JP5566383B2 (en) 2009-06-08 2010-06-06 Circuit board manufacturing method, circuit board manufactured thereby, and mother board for circuit board used therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009137383 2009-06-08
JP2009-137383 2009-06-08

Publications (1)

Publication Number Publication Date
WO2010143597A1 true WO2010143597A1 (en) 2010-12-16

Family

ID=43308852

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2010/059569 WO2010143597A1 (en) 2009-06-08 2010-06-06 Method for manufacturing circuit board, circuit board manufactured by the method, and base substrate used for the circuit board

Country Status (3)

Country Link
JP (1) JP5566383B2 (en)
TW (1) TW201112895A (en)
WO (1) WO2010143597A1 (en)

Cited By (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2478421A (en) * 2010-03-02 2011-09-07 Validity Sensors Inc Electrostatic discharge protection substrate for fingerprint scanner
US8077935B2 (en) 2004-04-23 2011-12-13 Validity Sensors, Inc. Methods and apparatus for acquiring a swiped fingerprint image
US8107212B2 (en) 2007-04-30 2012-01-31 Validity Sensors, Inc. Apparatus and method for protecting fingerprint sensing circuitry from electrostatic discharge
US8116540B2 (en) 2008-04-04 2012-02-14 Validity Sensors, Inc. Apparatus and method for reducing noise in fingerprint sensing circuits
US8131026B2 (en) 2004-04-16 2012-03-06 Validity Sensors, Inc. Method and apparatus for fingerprint image reconstruction
US8165355B2 (en) 2006-09-11 2012-04-24 Validity Sensors, Inc. Method and apparatus for fingerprint motion tracking using an in-line array for use in navigation applications
US8175345B2 (en) 2004-04-16 2012-05-08 Validity Sensors, Inc. Unitized ergonomic two-dimensional fingerprint motion tracking device and method
US8204281B2 (en) 2007-12-14 2012-06-19 Validity Sensors, Inc. System and method to remove artifacts from fingerprint sensor scans
US8224044B2 (en) 2004-10-04 2012-07-17 Validity Sensors, Inc. Fingerprint sensing assemblies and methods of making
US8229184B2 (en) 2004-04-16 2012-07-24 Validity Sensors, Inc. Method and algorithm for accurate finger motion tracking
US8278946B2 (en) 2009-01-15 2012-10-02 Validity Sensors, Inc. Apparatus and method for detecting finger activity on a fingerprint sensor
US8276816B2 (en) 2007-12-14 2012-10-02 Validity Sensors, Inc. Smart card system with ergonomic fingerprint sensor and method of using
US8290150B2 (en) 2007-05-11 2012-10-16 Validity Sensors, Inc. Method and system for electronically securing an electronic device using physically unclonable functions
US8358815B2 (en) 2004-04-16 2013-01-22 Validity Sensors, Inc. Method and apparatus for two-dimensional finger motion tracking and control
US8374407B2 (en) 2009-01-28 2013-02-12 Validity Sensors, Inc. Live finger detection
US8391568B2 (en) 2008-11-10 2013-03-05 Validity Sensors, Inc. System and method for improved scanning of fingerprint edges
US8447077B2 (en) 2006-09-11 2013-05-21 Validity Sensors, Inc. Method and apparatus for fingerprint motion tracking using an in-line array
JP2013120840A (en) * 2011-12-07 2013-06-17 Shin Etsu Chem Co Ltd Laminated substrate
US8538097B2 (en) 2011-01-26 2013-09-17 Validity Sensors, Inc. User input utilizing dual line scanner apparatus and method
US8594393B2 (en) 2011-01-26 2013-11-26 Validity Sensors System for and method of image reconstruction with dual line scanner using line counts
US8600122B2 (en) 2009-01-15 2013-12-03 Validity Sensors, Inc. Apparatus and method for culling substantially redundant data in fingerprint sensing circuits
US8698594B2 (en) 2008-07-22 2014-04-15 Synaptics Incorporated System, device and method for securing a user device component by authenticating the user of a biometric sensor by performance of a replication of a portion of an authentication process performed at a remote computing device
US8866347B2 (en) 2010-01-15 2014-10-21 Idex Asa Biometric image sensing
JP2014220287A (en) * 2013-05-02 2014-11-20 アルプス電気株式会社 Resin sealed product and method of manufacturing resin sealed product
US9001040B2 (en) 2010-06-02 2015-04-07 Synaptics Incorporated Integrated fingerprint sensor and navigation device
US9137438B2 (en) 2012-03-27 2015-09-15 Synaptics Incorporated Biometric object sensor and method
US9152838B2 (en) 2012-03-29 2015-10-06 Synaptics Incorporated Fingerprint sensor packagings and methods
US9195877B2 (en) 2011-12-23 2015-11-24 Synaptics Incorporated Methods and devices for capacitive image sensing
US9251329B2 (en) 2012-03-27 2016-02-02 Synaptics Incorporated Button depress wakeup and wakeup strategy
US9268991B2 (en) 2012-03-27 2016-02-23 Synaptics Incorporated Method of and system for enrolling and matching biometric data
US9274553B2 (en) 2009-10-30 2016-03-01 Synaptics Incorporated Fingerprint sensor and integratable electronic display
US9336428B2 (en) 2009-10-30 2016-05-10 Synaptics Incorporated Integrated fingerprint sensor and display
US9406580B2 (en) 2011-03-16 2016-08-02 Synaptics Incorporated Packaging for fingerprint sensors and methods of manufacture
US9600704B2 (en) 2010-01-15 2017-03-21 Idex Asa Electronic imager using an impedance sensor grid array and method of making
US9600709B2 (en) 2012-03-28 2017-03-21 Synaptics Incorporated Methods and systems for enrolling biometric data
US9665762B2 (en) 2013-01-11 2017-05-30 Synaptics Incorporated Tiered wakeup strategy
US9666635B2 (en) 2010-02-19 2017-05-30 Synaptics Incorporated Fingerprint sensing circuit
JPWO2016098628A1 (en) * 2014-12-17 2017-07-06 株式会社村田製作所 Multilayer ceramic electronic component and manufacturing method thereof
US9785299B2 (en) 2012-01-03 2017-10-10 Synaptics Incorporated Structures and manufacturing methods for glass covered electronic devices
US9798917B2 (en) 2012-04-10 2017-10-24 Idex Asa Biometric sensing
US10043052B2 (en) 2011-10-27 2018-08-07 Synaptics Incorporated Electronic device packages and methods

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210144302A (en) 2020-05-22 2021-11-30 삼성전자주식회사 A semiconductor package and a method for manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000133658A (en) * 1998-10-27 2000-05-12 Matsushita Electric Ind Co Ltd Manufacture of electronic component
JP2001068799A (en) * 1999-08-30 2001-03-16 Kyocera Corp Multi-element ceramic wiring board
JP2002026046A (en) * 2000-07-11 2002-01-25 Murata Mfg Co Ltd Electronic part device, substrate therefor and manufacturing method thereof
JP2002324870A (en) * 2001-04-24 2002-11-08 Kyocera Corp Method for manufacturing batch-process ceramic wiring board
JP2003110247A (en) * 2001-09-28 2003-04-11 Kyocera Corp Multilayer circuit board and manufacturing method thereof
JP2005322832A (en) * 2004-05-11 2005-11-17 Hitachi Aic Inc Wiring board and chip-type electronic component using the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000133658A (en) * 1998-10-27 2000-05-12 Matsushita Electric Ind Co Ltd Manufacture of electronic component
JP2001068799A (en) * 1999-08-30 2001-03-16 Kyocera Corp Multi-element ceramic wiring board
JP2002026046A (en) * 2000-07-11 2002-01-25 Murata Mfg Co Ltd Electronic part device, substrate therefor and manufacturing method thereof
JP2002324870A (en) * 2001-04-24 2002-11-08 Kyocera Corp Method for manufacturing batch-process ceramic wiring board
JP2003110247A (en) * 2001-09-28 2003-04-11 Kyocera Corp Multilayer circuit board and manufacturing method thereof
JP2005322832A (en) * 2004-05-11 2005-11-17 Hitachi Aic Inc Wiring board and chip-type electronic component using the same

Cited By (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8229184B2 (en) 2004-04-16 2012-07-24 Validity Sensors, Inc. Method and algorithm for accurate finger motion tracking
US8358815B2 (en) 2004-04-16 2013-01-22 Validity Sensors, Inc. Method and apparatus for two-dimensional finger motion tracking and control
US8315444B2 (en) 2004-04-16 2012-11-20 Validity Sensors, Inc. Unitized ergonomic two-dimensional fingerprint motion tracking device and method
US8131026B2 (en) 2004-04-16 2012-03-06 Validity Sensors, Inc. Method and apparatus for fingerprint image reconstruction
US8811688B2 (en) 2004-04-16 2014-08-19 Synaptics Incorporated Method and apparatus for fingerprint image reconstruction
US8175345B2 (en) 2004-04-16 2012-05-08 Validity Sensors, Inc. Unitized ergonomic two-dimensional fingerprint motion tracking device and method
US8077935B2 (en) 2004-04-23 2011-12-13 Validity Sensors, Inc. Methods and apparatus for acquiring a swiped fingerprint image
US8224044B2 (en) 2004-10-04 2012-07-17 Validity Sensors, Inc. Fingerprint sensing assemblies and methods of making
US8867799B2 (en) 2004-10-04 2014-10-21 Synaptics Incorporated Fingerprint sensing assemblies and methods of making
US8447077B2 (en) 2006-09-11 2013-05-21 Validity Sensors, Inc. Method and apparatus for fingerprint motion tracking using an in-line array
US8165355B2 (en) 2006-09-11 2012-04-24 Validity Sensors, Inc. Method and apparatus for fingerprint motion tracking using an in-line array for use in navigation applications
US8693736B2 (en) 2006-09-11 2014-04-08 Synaptics Incorporated System for determining the motion of a fingerprint surface with respect to a sensor surface
US8107212B2 (en) 2007-04-30 2012-01-31 Validity Sensors, Inc. Apparatus and method for protecting fingerprint sensing circuitry from electrostatic discharge
US8290150B2 (en) 2007-05-11 2012-10-16 Validity Sensors, Inc. Method and system for electronically securing an electronic device using physically unclonable functions
US8204281B2 (en) 2007-12-14 2012-06-19 Validity Sensors, Inc. System and method to remove artifacts from fingerprint sensor scans
US8276816B2 (en) 2007-12-14 2012-10-02 Validity Sensors, Inc. Smart card system with ergonomic fingerprint sensor and method of using
US8787632B2 (en) 2008-04-04 2014-07-22 Synaptics Incorporated Apparatus and method for reducing noise in fingerprint sensing circuits
US8520913B2 (en) 2008-04-04 2013-08-27 Validity Sensors, Inc. Apparatus and method for reducing noise in fingerprint sensing circuits
US8116540B2 (en) 2008-04-04 2012-02-14 Validity Sensors, Inc. Apparatus and method for reducing noise in fingerprint sensing circuits
US8698594B2 (en) 2008-07-22 2014-04-15 Synaptics Incorporated System, device and method for securing a user device component by authenticating the user of a biometric sensor by performance of a replication of a portion of an authentication process performed at a remote computing device
US8391568B2 (en) 2008-11-10 2013-03-05 Validity Sensors, Inc. System and method for improved scanning of fingerprint edges
US8593160B2 (en) 2009-01-15 2013-11-26 Validity Sensors, Inc. Apparatus and method for finger activity on a fingerprint sensor
US8600122B2 (en) 2009-01-15 2013-12-03 Validity Sensors, Inc. Apparatus and method for culling substantially redundant data in fingerprint sensing circuits
US8278946B2 (en) 2009-01-15 2012-10-02 Validity Sensors, Inc. Apparatus and method for detecting finger activity on a fingerprint sensor
US8374407B2 (en) 2009-01-28 2013-02-12 Validity Sensors, Inc. Live finger detection
US9274553B2 (en) 2009-10-30 2016-03-01 Synaptics Incorporated Fingerprint sensor and integratable electronic display
US9336428B2 (en) 2009-10-30 2016-05-10 Synaptics Incorporated Integrated fingerprint sensor and display
US9268988B2 (en) 2010-01-15 2016-02-23 Idex Asa Biometric image sensing
US10115001B2 (en) 2010-01-15 2018-10-30 Idex Asa Biometric image sensing
US8866347B2 (en) 2010-01-15 2014-10-21 Idex Asa Biometric image sensing
US9659208B2 (en) 2010-01-15 2017-05-23 Idex Asa Biometric image sensing
US9600704B2 (en) 2010-01-15 2017-03-21 Idex Asa Electronic imager using an impedance sensor grid array and method of making
US10592719B2 (en) 2010-01-15 2020-03-17 Idex Biometrics Asa Biometric image sensing
US11080504B2 (en) 2010-01-15 2021-08-03 Idex Biometrics Asa Biometric image sensing
US9666635B2 (en) 2010-02-19 2017-05-30 Synaptics Incorporated Fingerprint sensing circuit
US8716613B2 (en) 2010-03-02 2014-05-06 Synaptics Incoporated Apparatus and method for electrostatic discharge protection
GB2478421A (en) * 2010-03-02 2011-09-07 Validity Sensors Inc Electrostatic discharge protection substrate for fingerprint scanner
US9001040B2 (en) 2010-06-02 2015-04-07 Synaptics Incorporated Integrated fingerprint sensor and navigation device
US8929619B2 (en) 2011-01-26 2015-01-06 Synaptics Incorporated System and method of image reconstruction with dual line scanner using line counts
US8811723B2 (en) 2011-01-26 2014-08-19 Synaptics Incorporated User input utilizing dual line scanner apparatus and method
US8538097B2 (en) 2011-01-26 2013-09-17 Validity Sensors, Inc. User input utilizing dual line scanner apparatus and method
US8594393B2 (en) 2011-01-26 2013-11-26 Validity Sensors System for and method of image reconstruction with dual line scanner using line counts
US10636717B2 (en) 2011-03-16 2020-04-28 Amkor Technology, Inc. Packaging for fingerprint sensors and methods of manufacture
US9406580B2 (en) 2011-03-16 2016-08-02 Synaptics Incorporated Packaging for fingerprint sensors and methods of manufacture
USRE47890E1 (en) 2011-03-16 2020-03-03 Amkor Technology, Inc. Packaging for fingerprint sensors and methods of manufacture
US10043052B2 (en) 2011-10-27 2018-08-07 Synaptics Incorporated Electronic device packages and methods
JP2013120840A (en) * 2011-12-07 2013-06-17 Shin Etsu Chem Co Ltd Laminated substrate
US9195877B2 (en) 2011-12-23 2015-11-24 Synaptics Incorporated Methods and devices for capacitive image sensing
US9785299B2 (en) 2012-01-03 2017-10-10 Synaptics Incorporated Structures and manufacturing methods for glass covered electronic devices
US9268991B2 (en) 2012-03-27 2016-02-23 Synaptics Incorporated Method of and system for enrolling and matching biometric data
US9251329B2 (en) 2012-03-27 2016-02-02 Synaptics Incorporated Button depress wakeup and wakeup strategy
US9824200B2 (en) 2012-03-27 2017-11-21 Synaptics Incorporated Wakeup strategy using a biometric sensor
US9137438B2 (en) 2012-03-27 2015-09-15 Synaptics Incorporated Biometric object sensor and method
US9697411B2 (en) 2012-03-27 2017-07-04 Synaptics Incorporated Biometric object sensor and method
US10346699B2 (en) 2012-03-28 2019-07-09 Synaptics Incorporated Methods and systems for enrolling biometric data
US9600709B2 (en) 2012-03-28 2017-03-21 Synaptics Incorporated Methods and systems for enrolling biometric data
US9152838B2 (en) 2012-03-29 2015-10-06 Synaptics Incorporated Fingerprint sensor packagings and methods
US10088939B2 (en) 2012-04-10 2018-10-02 Idex Asa Biometric sensing
US10114497B2 (en) 2012-04-10 2018-10-30 Idex Asa Biometric sensing
US10101851B2 (en) 2012-04-10 2018-10-16 Idex Asa Display with integrated touch screen and fingerprint sensor
US9798917B2 (en) 2012-04-10 2017-10-24 Idex Asa Biometric sensing
US9665762B2 (en) 2013-01-11 2017-05-30 Synaptics Incorporated Tiered wakeup strategy
JP2014220287A (en) * 2013-05-02 2014-11-20 アルプス電気株式会社 Resin sealed product and method of manufacturing resin sealed product
JPWO2016098628A1 (en) * 2014-12-17 2017-07-06 株式会社村田製作所 Multilayer ceramic electronic component and manufacturing method thereof

Also Published As

Publication number Publication date
JPWO2010143597A1 (en) 2012-11-22
TW201112895A (en) 2011-04-01
JP5566383B2 (en) 2014-08-06

Similar Documents

Publication Publication Date Title
JP5566383B2 (en) Circuit board manufacturing method, circuit board manufactured thereby, and mother board for circuit board used therefor
JP4659421B2 (en) Manufacturing method of light emitting element storage package
US9596747B2 (en) Wiring substrate and electronic device
JP6267803B2 (en) Wiring board, electronic device and electronic module
JP2008205265A (en) Electronic-component mounting substrate
JP5383407B2 (en) Multi-wiring board
JP4272550B2 (en) Multiple wiring board
JP4388410B2 (en) Multiple wiring board
JP4712065B2 (en) Multi-cavity wiring board, wiring board, and multi-cavity wiring board and method of manufacturing wiring board
JP6374293B2 (en) Wiring board, electronic device and electronic module
JP2013115123A (en) Wiring board and manufacturing method therefor
JP2013115244A (en) Substrate for mounting electronic component, electronic device, and manufacturing method of substrate for mounting electronic component
JP5409066B2 (en) Electronic component storage package
JP2011176020A (en) Multi-piece wiring board and method of manufacturing the same
JP2005019749A (en) Wiring board and multiple wiring board
JP2005285865A (en) Multiple wiring board
JP3798992B2 (en) Multi-cavity ceramic wiring board
JP2008177334A (en) Electronic component mounting board
JP2003163442A (en) Ceramic wiring board
JP2010010360A (en) Electronic device, and method of manufacturing electronic device
JP2007201274A (en) Multiple patterning wiring board
JP2003078237A (en) Ceramic wiring board
JP2006074059A (en) Semiconductor device
JP2004023051A (en) Multi-wiring board
JPH08125080A (en) Semiconductor device and manufacture thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10786128

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2011518522

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10786128

Country of ref document: EP

Kind code of ref document: A1