WO2009135226A3 - Clock gating system and method - Google Patents

Clock gating system and method Download PDF

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Publication number
WO2009135226A3
WO2009135226A3 PCT/US2009/043913 US2009043913W WO2009135226A3 WO 2009135226 A3 WO2009135226 A3 WO 2009135226A3 US 2009043913 W US2009043913 W US 2009043913W WO 2009135226 A3 WO2009135226 A3 WO 2009135226A3
Authority
WO
WIPO (PCT)
Prior art keywords
input
enable node
internal enable
clock signal
clock gating
Prior art date
Application number
PCT/US2009/043913
Other languages
French (fr)
Other versions
WO2009135226A2 (en
Inventor
Martin Saint-Laurent
Bassam Jamil Mohd
Paul Bassett
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Priority to EP09740028.7A priority Critical patent/EP2286314B1/en
Priority to KR1020107026818A priority patent/KR101252698B1/en
Priority to CN200980114920.3A priority patent/CN102016749B/en
Priority to JP2011507719A priority patent/JP5199458B2/en
Publication of WO2009135226A2 publication Critical patent/WO2009135226A2/en
Publication of WO2009135226A3 publication Critical patent/WO2009135226A3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom

Abstract

A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that is responsive to a gated clock signal and is coupled to the internal enable node to selectively hold a logical voltage level at the internal enable node. The system further includes a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.
PCT/US2009/043913 2008-04-29 2009-05-14 Clock gating system and method WO2009135226A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP09740028.7A EP2286314B1 (en) 2008-04-29 2009-05-14 Clock gating system and method
KR1020107026818A KR101252698B1 (en) 2009-04-29 2009-05-14 Clock gating system and method
CN200980114920.3A CN102016749B (en) 2009-04-29 2009-05-14 Clock gating system and method
JP2011507719A JP5199458B2 (en) 2008-04-29 2009-05-14 Clock gating system and method

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US4866108P 2008-04-29 2008-04-29
US61/048,661 2008-04-29
US12/431,992 2009-04-29
US12/431,992 US7902878B2 (en) 2008-04-29 2009-04-29 Clock gating system and method

Publications (2)

Publication Number Publication Date
WO2009135226A2 WO2009135226A2 (en) 2009-11-05
WO2009135226A3 true WO2009135226A3 (en) 2010-09-10

Family

ID=41214380

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2009/043913 WO2009135226A2 (en) 2008-04-29 2009-05-14 Clock gating system and method

Country Status (4)

Country Link
US (1) US7902878B2 (en)
EP (2) EP2286314B1 (en)
JP (1) JP5199458B2 (en)
WO (1) WO2009135226A2 (en)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7844843B2 (en) * 2008-12-22 2010-11-30 International Business Machines Corporation Implementing power savings in HSS clock-gating circuit
US8159009B2 (en) * 2009-11-19 2012-04-17 Qualcomm Incorporated Semiconductor device having strain material
US8397238B2 (en) * 2009-12-08 2013-03-12 Qualcomm Incorporated Thread allocation and clock cycle adjustment in an interleaved multi-threaded processor
KR101354286B1 (en) 2009-12-18 2014-01-23 후지쯔 가부시끼가이샤 Latch circuit and clock control circuit
US8380904B2 (en) * 2010-03-09 2013-02-19 Qualcomm Incorporated Interconnect coupled to master device via at least two different bidirectional connections
US9385308B2 (en) 2010-03-26 2016-07-05 Qualcomm Incorporated Perpendicular magnetic tunnel junction structure
US8493109B2 (en) * 2010-03-31 2013-07-23 Qualcomm Incorporated System and method to control a power on reset signal
US8547736B2 (en) * 2010-08-03 2013-10-01 Qualcomm Incorporated Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction
US8892924B2 (en) * 2011-05-31 2014-11-18 Intel Corporation Reducing power consumption of uncore circuitry of a processor
US8890573B2 (en) * 2012-09-07 2014-11-18 Nvidia Corporation Clock gating latch, method of operation thereof and integrated circuit employing the same
CN104769841B (en) 2012-09-19 2018-11-13 高通股份有限公司 For reducing the clock gating circuit of dynamic power
US8975949B2 (en) 2013-03-14 2015-03-10 Samsung Electronics Co., Ltd. Integrated clock gater (ICG) using clock cascode complimentary switch logic
US9176522B1 (en) 2014-05-02 2015-11-03 Freescale Semiconductor, Inc. Dual-edge gated clock signal generator
TWI565331B (en) * 2014-07-21 2017-01-01 鑫創科技股份有限公司 Microphone system and microphone control method
KR102204597B1 (en) * 2014-11-19 2021-01-19 삼성전자주식회사 Semiconductor device
US9577635B2 (en) 2015-01-15 2017-02-21 Qualcomm Incorporated Clock-gating cell with low area, low power, and low setup time
US10230373B2 (en) 2015-04-27 2019-03-12 Samsung Electronics Co., Ltd. Clock gating circuit
KR102261300B1 (en) 2015-06-22 2021-06-09 삼성전자주식회사 Clock gating circuit operating at high speed
US10141916B2 (en) 2015-09-01 2018-11-27 Samsung Electronics Co., Ltd. High-speed flip-flop semiconductor device
US10581410B2 (en) 2015-09-10 2020-03-03 Samsung Electronics Co., Ltd High speed domino-based flip flop
US9564897B1 (en) 2015-10-06 2017-02-07 Samsung Electronics Co., Ltd Apparatus for low power high speed integrated clock gating cell
US9755618B1 (en) 2016-03-04 2017-09-05 Qualcomm Incorporated Low-area low clock-power flip-flop
US9940992B2 (en) * 2016-03-30 2018-04-10 Qualcomm Incorporated Leakage-aware activation control of a delayed keeper circuit for a dynamic read operation in a memory bit cell
CN107300948A (en) 2016-04-14 2017-10-27 飞思卡尔半导体公司 Integrated circuit with multidigit clock gating unit
KR102465497B1 (en) 2016-04-28 2022-11-09 삼성전자주식회사 Semiconductor circuit
US10177765B2 (en) * 2016-08-23 2019-01-08 Intel Corporation Integrated clock gate circuit with embedded NOR
US9742408B1 (en) 2016-09-23 2017-08-22 International Business Machines Corporation Dynamic decode circuit with active glitch control
CN106371549A (en) * 2016-09-28 2017-02-01 深圳市博巨兴实业发展有限公司 Ultra-low power consumption clock control method applied to MCU (Micro-programmed Control Unit) system
US9953687B1 (en) 2016-10-21 2018-04-24 Advanced Micro Devices, Inc. Pseudo-dynamic circuit for multi-voltage timing interlocks
US9979381B1 (en) 2016-10-28 2018-05-22 Qualcomm Incorporated Semi-data gated flop with low clock power/low internal power with minimal area overhead
US10049726B1 (en) 2017-02-03 2018-08-14 Advanced Micro Devices, Inc. Contention-free dynamic logic
US20180226968A1 (en) * 2017-02-05 2018-08-09 Advanced Micro Devices, Inc. Contention-Free Dynamic Logic
KR102446164B1 (en) 2017-12-26 2022-09-22 삼성전자주식회사 Integrated circuit including signal-load cell and method of designing the same
US10374604B1 (en) 2018-08-12 2019-08-06 International Business Machines Corporation Dynamic decode circuit low power application
US10784864B1 (en) 2019-03-13 2020-09-22 Samsung Electronics Co., Ltd. Low power integrated clock gating system and method
KR20210037927A (en) 2019-09-30 2021-04-07 삼성전자주식회사 Integrated clock gating cell and integrated circuit including the same
US11190186B2 (en) 2020-04-08 2021-11-30 Samsung Electronics Co., Ltd. Clock gating cell with low power and integrated circuit including the same
US11223351B1 (en) * 2021-01-29 2022-01-11 Xilinx, Inc. Activity-aware clock gating for switches
US11526650B1 (en) * 2021-03-31 2022-12-13 Cadence Design Systems, Inc. Switching power aware driver resizing by considering net activity in buffering algorithm
US20230179206A1 (en) * 2021-12-07 2023-06-08 Mediatek Inc. Clock gating cells

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6133762A (en) * 1997-03-31 2000-10-17 Texas Instruments Incorporated Family of logic circuits emploting mosfets of differing thershold voltages
US6552572B1 (en) * 2001-10-24 2003-04-22 Lsi Logic Corporation Clock gating cell for use in a cell library
US20040237054A1 (en) * 2003-05-21 2004-11-25 Tsai Cheng Mao System and method for performing intellectual property merge
WO2005036422A1 (en) * 2003-09-16 2005-04-21 Pdf Solutions, Inc. Integrated circuit design to optimize manufacturability
GB2420034A (en) * 2004-11-05 2006-05-10 Samsung Electronics Co Ltd A clock gating circuit for reducing power consumption in flip-flops

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5598112A (en) * 1995-05-26 1997-01-28 National Semiconductor Corporation Circuit for generating a demand-based gated clock
US5822700A (en) 1996-04-18 1998-10-13 Telefonaktiebolaget L M Ericsson Flow control of short message service messages in a cellular telephone network
JP3528413B2 (en) * 1996-04-19 2004-05-17 ソニー株式会社 Function clock generation circuit, and D-type flip-flop with enable function using the same and storage circuit
DE19629899C1 (en) 1996-07-24 1997-08-21 Nokia Mobile Phones Ltd Time division duplex mobile communication method
US5936449A (en) 1997-09-08 1999-08-10 Winbond Electronics Corporation Dynamic CMOS register with a self-tracking clock
SE519211C2 (en) 1997-10-14 2003-01-28 Ericsson Telefon Ab L M Methods for initiating reconfiguration of a cell for the number of signaling channels in relation to the number of traffic channels
US6204695B1 (en) * 1999-06-18 2001-03-20 Xilinx, Inc. Clock-gating circuit for reducing power consumption
DE10007602A1 (en) 2000-02-18 2001-08-30 Siemens Ag Transferring packet data information in radio communications system - involves transmitting identification information separated from associated data packet over same or specially dedicated channel
TW465188B (en) * 2001-01-02 2001-11-21 Faraday Tech Corp Clock gate buffer circuit
TW530481B (en) * 2001-10-19 2003-05-01 Primax Electronics Ltd Anti-abrasion flat flexible cable structure
KR100811043B1 (en) 2001-11-16 2008-03-06 엘지전자 주식회사 method for controlling transmission power of SCH and HI in mobile communication
CN101790244B (en) 2002-05-01 2013-08-14 美商内数位科技公司 Method for transferring service data and wireless communication system and nodes B and RNC
US7068080B1 (en) * 2003-01-17 2006-06-27 Xilinx, Inc. Method and apparatus for reducing power consumption within a logic device
US7109776B2 (en) * 2004-09-23 2006-09-19 Intel Corporation Gating for dual edge-triggered clocking
US7323909B2 (en) * 2005-07-29 2008-01-29 Sequence Design, Inc. Automatic extension of clock gating technique to fine-grained power gating
JP2007329586A (en) * 2006-06-06 2007-12-20 Sanyo Electric Co Ltd Semiconductor integrated circuit device, and design apparatus and design method thereof
US7587686B1 (en) * 2006-08-01 2009-09-08 Altera Corporation Clock gating in a structured ASIC
JP4711915B2 (en) * 2006-09-04 2011-06-29 東芝メモリシステムズ株式会社 Electronic circuit
US7639057B1 (en) * 2006-12-07 2009-12-29 Marvell International Ltd. Clock gater system
US7724058B2 (en) * 2007-10-31 2010-05-25 Qualcomm Incorporated Latch structure and self-adjusting pulse generator using the latch

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6133762A (en) * 1997-03-31 2000-10-17 Texas Instruments Incorporated Family of logic circuits emploting mosfets of differing thershold voltages
US6552572B1 (en) * 2001-10-24 2003-04-22 Lsi Logic Corporation Clock gating cell for use in a cell library
US20040237054A1 (en) * 2003-05-21 2004-11-25 Tsai Cheng Mao System and method for performing intellectual property merge
WO2005036422A1 (en) * 2003-09-16 2005-04-21 Pdf Solutions, Inc. Integrated circuit design to optimize manufacturability
GB2420034A (en) * 2004-11-05 2006-05-10 Samsung Electronics Co Ltd A clock gating circuit for reducing power consumption in flip-flops

Also Published As

Publication number Publication date
EP2620833A1 (en) 2013-07-31
EP2286314B1 (en) 2014-08-27
EP2286314A2 (en) 2011-02-23
EP2620833B1 (en) 2015-09-02
JP5199458B2 (en) 2013-05-15
US7902878B2 (en) 2011-03-08
JP2011526091A (en) 2011-09-29
WO2009135226A2 (en) 2009-11-05
US20090267649A1 (en) 2009-10-29

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