WO2009087109A1

WO2009087109A1 - Dynamic electronic synapse device

Info

Publication number: WO2009087109A1
Application number: PCT/EP2009/000091
Authority: WO
Inventors: Liam Mcdaid; Peter Kelly
Original assignee: University Of Ulster
Priority date: 2008-01-10
Filing date: 2009-01-09
Publication date: 2009-07-16
Also published as: GB0800391D0

Abstract

An electronic synapse device comprising a substrate formed from semiconductor material and a plurality of inputs including a first input for receiving a weighting signal and a second input for receiving a signal from a pre-synaptic neuron device. An insulating layer is provided between the inputs and the semiconductor material. The device has an output, the second input being located between the first input and the output. An electrical charge storage region is provided in the substrate substantially in register with the first input. The device also includes an electrical charge source that is operable to transfer electrical charge into said electrical charge storage region.

Description

Dynamic Electronic Synapse Device

Field of the Invention

The present invention relates to electronic synapse devices.

Background to the Invention

International PCT patent application WO 2006/103109 discloses an electronic synapse device. The characteristics of the output signal of the synapse are dependent on the quantity of charge that is present in an inversion layer whenever an input signal, typically in the form of a spike, is received. The charge in the inversion layer is replenished by a thermally generated current.

A problem with the synapse device of WO 2006/103109 is that the charge in the inversion layer does not replenish quickly enough to allow the device to adequately accommodate certain types of input signal.

It would be desirable, therefore, to provide a small and efficient hardware implementation of a synapse that overcomes the problem outlined above.

Summary of the Invention

Accordingly, a first aspect of the invention provides an electronic synapse device comprising: a substrate formed from semiconductor material; a plurality of inputs including a first input for receiving a weighting signal, and a second input for receiving a signal from a pre-synaptic neuron device; an insulating layer provided between said inputs and said semiconductor material; and an output, the second input being located between said first input and said output, and wherein an electrical charge storage region is provided in the substrate substantially in register with said first input, the device further including an electrical charge source that is operable to transfer electrical charge into said electrical charge storage region.

In the preferred embodiment, the device includes a third input for receiving a first control signal, the first input being located between said second and third inputs, and the electrical charge source being operable to transfer electrical charge into said electrical charge storage region by application of said first control signal to said third input.

The electrical charge source is preferably provided in said substrate, conveniently by providing a first doped region in the substrate to create a semiconductor junction (e.g. a p-n junction or n-p junction as applicable) in the substrate with an oppositely doped first transfer region in the substrate. The preferred arrangement is such that said first transfer region is located between said first doped region and said charge storage region, and substantially in register with said third input. The first doped region is electrically connected to a reference potential, typically electrical ground, and the biasing of the junction is controllable by said first control signal. Hence, the first control signal controls in use the transfer of charge from the electrical charge source to the electrical charge storage region, conveniently via said first transfer region.

Optionally, the device includes a fourth input for receiving a second control signal, the fourth input being located between said first input and said output. A second transfer region is provided in said substrate substantially in register with said fourth input, the arrangement being such that charge is transferable from said charge storage region to said output via said second transfer region under the control of said second control signal.

In preferred embodiments, the device may be said to comprise a first transistor wherein the source is provided by said electrical charge source, the drain is provided by said electrical charge storage region, and the gate is provided by said first input. In particularly preferred embodiments, a second transistor is located adjacent said first transistor, wherein the source of the second transistor is provided by said electrical charge storage region, the drain is provided by the region of the substrate substantially in register with the second input, and the gate is provided by said fourth input.

Conveniently, the device is implemented using MOS (metal oxide semiconductor) technology (including all equivalent technologies, e.g. where the traditionally metal gate components are formed from non-metallic material, e.g. polysilicon), although alternative implementation technologies that allow charge storage and transfer may be used.

During operation of the preferred device, upon application of said weighting signal to said first input, a quantity of charge accumulates in said charge storage region, and, upon application of said pre-synaptic signal to said second input, said charge is transferred to the region of said substrate that is substantially in register with said second input whereupon said charge causes an output signal to be generated at said output.

Conveniently, the output comprises a charge collector. The charge collector may comprise a region of said substrate doped to create a p-n or n-p junction in said substrate adjacent a region of said substrate that is substantially in register with said second input. The p-n or n-p junction is biased to attract charge which accumulates in said substrate as a result of application of said weighting signal to said first input. In a typical embodiment, where the substrate comprises p-type semiconductor material and said doped region comprises N+ type semiconductor material, the resulting p-n junction is reverse biased in use. Biasing of the junction may be achieved by applying suitable voltage levels to the output of the device and to one or both of the input terminals, e.g. the first input terminal. The weighting signal applied, during use, to said first input is typically at a fixed level during each operational cycle of the synapse device. This causes a fixed or finite quantity of charge to accumulate in the region of the first input, which is then transferred to the region of the second input and ultimately to the output upon receipt of the pre-synaptic signal at the second input. It is preferred, however, that the level of said weighting signal is adjustable between operational cycles. This allows different quantities of charge to be accumulated and so the output of the device is adjusted accordingly. The signal applied, during use, to said second input conveniently comprises a clocking signal, for example, a spike signal, a pulse signal or a step signal.

In the preferred embodiment, the first and second inputs, the insulating layer and the substrate together form a first capacitor structure and a second capacitor structure. The capacitor structures preferably each comprise a respective MOS capacitor.

A second aspect of the invention provides an electronic neural structure comprising a pre-synaptic neuron device and a post-synaptic neuron device in communication with one another by means of an electronic synapse device of the first aspect of the invention.

In a typical embodiment, the pre-synaptic neuron device provides, in use, a presynaptic signal to said second input of the synapse device, and said synapse device provides a corresponding weighted output signal to said post-synaptic neuron device via the output of the synapse device, said neural structure further including, or being co-operable with, means for applying said weighting signal to said first input, and means for applying said first control signal to said third input. The neural structure may also include, or be co-operable with means for applying said first control signal to said fourth input. A third aspect of the invention provides an electronic neural network comprising at least one electronic neural structure according to the second aspect of the invention.

A fourth aspect of the invention provides a method of emulating the operation of a synapse using an electronic synapse device according to the first aspect of the invention, the method comprising causing a quantity of charge to accumulate in said substrate in the region of said first input by application of a weighting signal to said first input; and causing said charge to be transferred to said output by application of an input signal to said second input.

In preferred embodiments, the device includes, or is associated with, means for applying a biasing signal to said first input such that a quantity of charge is created in said substrate in register with, or in the region of, said first input, and wherein, upon application of an input signal to said second input, said charge is transferred to said output to create an output signal.

The biasing signal applied to the first input serves as the weighting signal which determines the amount of charge that is created and so determines the weight that the electronic synapse applies to a received signal from a pre-synaptic neuron structure. The second input receives, during use, signals from a pre-synaptic neuron. Typically, signals received at the second input take the form of a train of pulses, e.g. spikes.

The output signal, which during use may be supplied to a post synaptic neuron structure, typically takes the form of a trains of transient or spike signals and as such is comparable in shape to output signals from biological synapses. The magnitude of the output signal is determined by the amount of charge that is created and is thus dependent on the level of the weighting signal to the first input. In the preferred embodiment, said charge accumulates in an inversion layer adjacent the interface of the substrate and the insulating layer, in register with, or in the region of, the first input.

Further advantageous aspects of the invention will become apparent to those ordinarily skilled in the art upon review of the following description of a specific embodiment and with reference to the accompanying drawings.

Brief Description of the Drawings

An embodiment of the invention is now described by way of example and with reference to the accompanying drawings in which:

Figure Ia shows a representation of a feed forward neural network;

Figure Ib shows an enlarged view of part of the network of Figure Ia;

Figure 2 shows a representation of a neuron to neuron structure with synaptic junction;

Figure 3 shows a schematic view of a preferred electronic synapse device embodying the invention; and

Figure 4 shows a schematic view of an alternative electronic synapse device embodying the invention.

Detailed Description of the Drawings

A typical feed-forward neural network is shown in Figure Ia, generally indicated as 10. The network 10 comprises a plurality of neurons 12, each neuron 12 in one layer, e.g. the input layer (on the left hand side of Figure Ia), is connected to every neuron 12 in the next layer via a synapse 14 and so on: the network 10 could have many layers. For clarity only a few synapses 14 are shown in Figure Ia. Figure Ib shows one neuron 12 of the network 10 to highlight that for every neuron 12 there may be many synapses 14. Each synapse 14 forms a connecting node in a pathway between neurons 12, as shown in Figure Ia.

With reference to Figure 2, an artificial model for a biological synapse is now described. Figure 2 shows a fragment of a neural network consisting of two point neurons (A and B) with an intermediate synapse or synaptic junction 14.

Neuron A outputs a spike S, which forms the input to the synaptic junction 14. At the junction 14 the spike S is transmitted to the output neuron B, its magnitude having been weighted according to a weight value W_AB- The output of the synapse 14, known as the Post Synaptic Potential (PSP), resembles a transient function where the rise time constant and fall time constant are significantly different from each other. From an electronic perspective, this behaviour can be caused by a loading effect associated with the post-synaptic membrane time constant. Therefore, it is accurate to assume that in the absence of this loading effect, the output of a synapse is essentially another spike whose magnitude is modulated by a weight WA_B provided at a weight input (i.e. it behaves essentially as an analogue multiplier).

Figure 3 presents a schematic view of a device, generally indicated as 20, for implementing a synapse in hardware, in this case electronically, the device 20 embodying the invention in a preferred form. The device 20 comprises a substrate

22 of semiconductor material which, in the illustrated embodiment, comprises p- type semiconductor material. Any conventional semiconductor material, for example silicon or gallium arsenide, may be used. An electrically insulating layer 24 is provided adjacent, or on, the substrate 22, typically in the form of an oxide layer, e.g. a silicon dioxide layer. A first input terminal, or electrode, 26, typically formed from metal, for example aluminium, is provided adjacent, or on, the insulator layer 24 such that the insulator layer 24 is located between the electrode 26 and the substrate 22. The first electrode 26 serves as a first input gate and may be implemented in any convenient manner. A second input terminal, or electrode, 28, typically formed from metal, for example aluminium, is provided adjacent, or on, the insulator layer 24 such that the insulator layer 24 is located between the electrode 28 and the substrate 22. The second electrode 28 serves as a second input gate.

The substrate 22 is tied to a reference potential, typically electrical ground (shown as element 25 in Figure 3), distal the insulator layer 24. Normally, a contact layer (not shown) is provided at the surface 23 of the substrate 22 for making a connection to ground, or other reference potential.

The device 20 includes an output 30 which includes an output terminal 27. In the preferred embodiment, the output comprises a charge collector (or charge drain) that is provided in the substrate 22 by appropriate doping of the semiconductor material. The resulting semiconductor junction 31 is appropriately biased, in this example reverse biased, during use. In the present example, this is achieved by doping the substrate 22 in the region of the output 30 to create an N+ region 33 and a p-n junction 31. Hence, any electrons arriving at the junction 31 are collected and output at terminal 27. In the present example, the collector is an electron collector and so collects electrons from the substrate 22. In alternative embodiments (not illustrated) where the substrate is an n-type substrate and region 33 is doped such that junction 31 is an n-p junction, the collector is a hole collector, i.e. a collector of positive charge. As well as providing an output signal, the terminal 29 may be used to apply an appropriate biasing voltage for the junction 31.

As will be seen from the following description, during use a quantity of electrical charge is stored in the substrate 22 at the junction with the insulator layer 24 and substantially in register with (or beneath as shown in Figure 3) the first gate electrode 26 when the substrate 22 is appropriately biased which, in the preferred embodiment, depends on the level of voltage applied to the first gate electrode 26. By applying an input signal, typically a voltage signal comprising for example a spike, pulse or step voltage, to the second gate electrode 28, the stored charge is released as is described in more detail below.

During use, a voltage Vw is applied to the first gate 26 in order to bias the substrate 22 such that a depletion layer 40 is formed in the substrate 22 in register with (beneath as viewed in Figure 3) the first gate 26, and such that an inversion layer 42 is created in substrate 22 in register with (or beneath) the first gate 26 substantially at the semiconductor-insulator interface. In this embodiment, the inversion layer 42 comprises a quantity of charge Qw in the form of electrons (negative charge), the amount of which depends on the level of the voltage Vw applied to the first gate 26. In an alternative embodiment where the substrate comprises n-type semiconductor material the charge may be comprised of holes, i.e. positive charge. The voltage Vw, which in the present example comprises a positive voltage with respect to ground, may be referred to as a weight voltage. In comparison with the synapse model of Figure 2, the gate input 26 of the device 20 serves as the weight input for the synapse 14, the applied voltage Vw corresponding to the weight W_AB- The voltage Vw may be applied by any suitable means and may be fixed or variable. The voltage Vw may be stored, for application to the gate 26, using any suitable means, e.g. stored on a floating gate. In the preferred embodiment, the device 20 includes, or is connectable to, means for biasing the device 20 via the first gate 26 in order to create the desired charge Qw. The biasing means preferably takes the form of means for applying a voltage to the first gate 26. By way of example, a memory device (not shown), or a programmable memory device, may be used to provide the voltage Vw. There are a number of alternative approaches to storing weight voltages, including nonvolatile memory-like structures, for example with dual gate operation, which may be connected to the device 20 for this purpose. The level of voltage applied to gate 26 may be varied depending on the required operation of the device 20 (i.e. depending on the required weight W_AB), although normally the voltage applied to the first gate 26 is fixed during use so that a known, finite quantity of charge builds up in the inversion layer 42.

The second gate 28 serves as an input for receiving a pre-synaptic signal, i.e. a signal from a device (not shown) acting as a pre-synaptic neuron (for example neuron A in Figure 2). The pre-synaptic signal is such that, in a quiescent state, the charge Qw remains in the inversion layer 42. However, when the pre-synaptic signal adopts an active state, it biases the substrate 22 such that a region in register with, or in the region of (beneath as viewed in Figure 3), the second gate 28 is driven into depletion. In the present embodiment, it is assumed that the presynaptic signal takes the form of a train of pulses, typically in the form of spikes, as indicated in Figure 3 by the numeral 29. In the present embodiment, the active state of the pre-synaptic signal involves the application of a voltage, in this example a positive voltage, to the second gate 28 in order cause depletion in the substrate 22 at the second gate 28.

During use, when the pre-synaptic signal is in its quiescent state, a finite quantity of charge Qw is stored in the inversion layer 42 as a result of the weight voltage Vw- When a pulse, or other pre-synaptic signal, is transmitted to the second gate 28 by a pre-synaptic neuron device, the semiconductor material beneath the gate 28 is driven into deep depletion. This causes the charge Qw to drift laterally from the region of the first gate 26 towards the second gate 28, and in particular towards the depleted region beneath the second gate 28, and subsequently to the output 30 whereupon the charge Qw gives rise to an output signal from the output terminal 27. The output signal serves as a post synaptic signal for a post synaptic neuron device (e.g. neuron B in Figure 2).

It is not essential for the pre-synaptic neuron device to generate spikes to "clock" the gate 28. A simple voltage step, or train of pulses, is suitable as the presynaptic input to gate 28. It will be understood from the foregoing that the charge packet Qw₅ which contains a finite amount of charge determined by the voltage Vw on the first electrode 26, results in a transient "spike" signal or current at the output 30, provided that the second gate 28 is sufficiently close to the first gate 26 to cause the charge Qw to drift, as described above, upon application of a pre-synaptic signal to the gate 28. By adjusting the voltage Vw, different levels of charge Qw can be stored and hence synaptic plasticity is achieved.

The respective portions of the device 20 that are in register with the first and second gates 26, 28 may, in the preferred embodiment, be said to comprise a respective MOS (metal oxide semiconductor) capacitor (indicated as Cl and C2 on Figure 3), sharing a common substrate 22, insulator layer 24 and reference terminal (in this case electrical ground).

The device 20 includes a charge source 50. In the preferred embodiment, the charge source 50 is provided in the substrate 22 by appropriate doping of the semiconductor material. The resulting semiconductor junction 51 is appropriately biased, in this example forward biased, during use. In the present example, the substrate 22 is doped in a region beyond the first gate 26 with respect to the second gate 28 to create an N+ region 53 and a p-n junction 51. Hence, when the junction 51 is appropriately biased, electrons flow from the source 50 to the inversion layer 42. In alternative embodiments (not illustrated) where the substrate is an n-type substrate and region 53 is doped such that junction 51 is an n-p junction, the charge source is a source of positive charge.

The charge source 50 is connected to a reference potential, conveniently electrical ground 25. In order to provide an appropriate and controllable bias to the junction 51, a third input terminal, or electrode, 54, typically formed from metal, for example aluminium, is provided adjacent, or on, the insulator layer 24 such that the insulator layer 24 is located between the electrode 54 and the substrate 22. The electrode 54 serves as a third input gate and, in preferred embodiments, comprises a floating gate. The electrode 54 (which hereinafter is referred to as the third gate) is located between the charge source 50 and the first gate 26 and substantially in register with (above as viewed in Figure 3) a region of the substrate 22 that lies between the charge source 50 and the depletion layer 40.

In use, a biasing signal, typically in the form of a voltage signal Vχi, is applied to the third gate 54 (by any suitable means - not shown) in order to bias the junction 51 and to cause charge (in the form of electrons in the present example) to be transferred from the charge source 50 to the inversion layer 42 via a charge transfer region of the substrate 22 that is located between the charge source 50 and the region beneath the first input 26. The quantity of charge that flows from the source 50 to the inversion layer 42 is controllable by adjusting the voltage signal V_T1. Hence, the charge Q_w in the inversion layer 42 can be replenished as required under the control of signal Vj₁. This is particularly advantageous in cases where the pre-synaptic signal applied to the second gate 28 comprises a train of spikes, or similar, since there is no reliance on thermally generated current to replenish the charge Q_w.

Optionally, a fourth input terminal, or electrode, 56, typically formed from metal, for example aluminium, is provided adjacent, or on, the insulator layer 24 such that the insulator layer 24 is located between the electrode 56 and the substrate 22. The electrode 56 serves as a fourth input gate and, in preferred embodiments, comprises a floating gate. The electrode 56 (which hereinafter is referred to as the fourth gate) is located between the first gate 26 and the second gate 28. In use, a control signal, typically in the form of a voltage signal Vχ₂, is applied to the fourth gate 56 (by any suitable means - not shown) in order to control the flow of charge from the inversion layer 42 to the output 30 via a charge transfer region of the substrate 22 that is located between the region beneath the first input 26 and the output region 33. The quantity of charge that flows from the inversion layer 42 is controllable by adjusting the voltage signal Vχ₂. The third gate 54 may, in the preferred embodiment, be said to form part, i.e. the gate input, of a transistor (in particular a MOSFET), the source and drain of the transistor being provided respectively by the charge source 50 and the region of the device 20 in register with the first gate 26. This transistor is indicated as Tl in Figure 3. The fourth gate 56 may, in the preferred embodiment, be said to form part, i.e. the gate input, of a second transistor (in particular a MOSFET), the source and drain of the transistor being provided respectively by the region of the device 20 in register with the first gate 26, and by the region of the device 20 in register with the second gate 28. This transistor is indicated as T2 in Figure 3. Vχi and Vχ₂ respectively provide controlling voltages for the transistors Tl, T2.

The inversion layer charge Qw beneath the first gate 26 implements plasticity where the charge density is modulated by Vw, and acts as a virtual drain and source for Tl and T2 (when present) respectively.

In the absence of the pre-synaptic spike train 29 (or other pre-synaptic signal) at the second gate 28, the device 20 is in equilibrium with no current flowing under the third or fourth gates 54, 56 irrespective of the magnitude of the voltages at these gates. Under this operating condition a quantity of charge Qw is stored in the inversion layer 42 as a result of the weight voltage Vw (in this case a positive weight voltage) applied to the first gate 26. When a pre-synaptic signal, e.g. the spike train 29, is applied to the second gate 28, a portion of the substrate 22 beneath this gate goes into deep depletion, which acts as a dynamic drain for transistor T2. The device 20 enters a non-equilibrium state and the density, or quantity, of charge Qw in the inversion layer 42 at any time, t , depends on Vw, typically on the magnitude of Vw, (implementing long term potentiations/plasticity (LTP)) and the relative magnitudes of Vχi and Vr₂ (implementing short term potentiations/plasticity (STP)). Therefore, the magnitude of the current spikes in the output signal of the device 20 is dependant on the magnitudes and/or relative magnitudes of these voltages, and the characteristics of the pre-synaptic signal, e.g. the frequency of the spikes (or other signal events, e.g. pulses) in the train 29. Consider Vw such that the MOS capacitor at the first gate 26 is operating in strong inversion with Vn, Vx₂ greater than zero and assume that a low frequency spike train is applied to the second gate 28. At the instant a spike voltage arrives at the second gate 28, a current pulse flows under the fourth gate 56. Therefore, each pre-synaptic spike causes a quantity of charge to be transferred from the inversion layer 42 to the output 30. The current pulse results from a rapid increase in the surface potential in the inversion layer 42 as the charge is removed, which eventually inhibits the further transfer of charge from the inversion layer 42 to the channel beneath fourth gate 56. Therefore, the average current under the fourth gate 56 is determined by the magnitude of Vχ₂ and the frequency of the spikes in the pre-synaptic signal 29.

In contrast the current under the third gate 54 flows from the charge source 50 to the inversion layer 42 while the potential in the inversion layer 42 is in non- equilibrium, the current magnitude being determined by Vx₁, and in particular the magnitude OfVx₁. Hence, if the frequency of the spike train 29 at the second gate 28 is low enough, the device 20 behaves in a manner known as facilitating because the average current under the fourth gate 56 is less that the current under the first gate 26 and the inversion layer 42 is maintained full of charge (since more charge is entering the inversion layer than is leaving) with a density given by:

where C_0x and Vx are the capacitance per unit area and threshold voltage respectively associated with the MOS capacitor associated with the first gate 26. If the frequency of the pre-synaptic spikes is increased, an operating point is reached where the average current under the fourth gate 56 becomes greater than that under the third gate 54. Under this condition the magnitude of charge in the inversion layer 42 diminishes with each spike received at the second gate 28 (since more charge is leaving the inversion layer 42 than is entering). Accordingly, the current spikes at the output 30 will progressively reduce in magnitude and the device 20 has entered a depression state.

Therefore, the relative magnitudes of Vpi and V_T2 determine the frequency at which the transition from facilitating to depressing occurs. If single spike, or pulse, encoding is used as the pre-synaptic signal, then the device 20 may operate as a static synapse if Vj₂ is tied to a voltage supply rail. In this operating state the value of V_T i sets the minimal time between temporal spike encoding.

Considering that both transistors Tl, T2 only conduct current when the device 20 is in the dynamic state, then the device 20 operates in transient mode and therefore the associated power consumption is small. For example, consider an extreme case with a network containing 10 synapses synchronized to a spike train at gate 58 with a frequency of IMHz. Assuming that Vw = 5 V, which yields an average current spike amplitude of 10^"7 Amps over a duration of 2 ns, then a simple calculation yields that the power consumption/second is of the order of 10^"4 Watts.

It will be understood that the invention is not limited to use with a p-type substrate. For example, the substrate 22 may be formed from n-type material, in which case regions 33 and 53 would be doped to be P+ type regions and the biasing of the device, and current flows, would be the reverse of the device 20, as would be apparent to a skilled person.

The charge density in the inversion layer 42 diminishes with time and so the transfer of charge will result in a spiking current at the output.

By way of example only, the regions 33, 53 at the output may be doped with N_D = 10¹⁹ cm^'3 and the p-type substrate 22 may be doped with N_A = 10¹⁶ cm^'3. The respective gates 26, 28 may be spaced between 0.2 microns and 0.7 microns apart The thickness of the oxide layer 24 may be between 0.02 microns and 100 run. The output may comprise an electrode collector on the N+ region 33. Fixed voltages of +5 V and +3 V may be applied respectively to the collector electrode 30 and first gate 26. It will apparent to a skilled person that these dimensions, voltages and other characteristics may be varied while still achieving the functionality described herein.

Referring now to Figure 4 of the drawings, there is shown, generally indicated as 120, an alternative embodiment of an electronic synapse device. The device 120 and its operation are similar to the device 20 of Figure 3 and so the foregoing description of the device 20 applies to the device 120 as would be apparent to a skilled person, like numerals being used to denote like parts. A key difference between the devices 20, 120 is that the device 120 does not include the fourth terminal 56.

Similarly to the device 20, the device 120 comprises a transistor Tl (in particular a MOSFET) in series with two capacitors Cl and C2. The weight charge Vw, which implements LTP, is stored in the region under the gate 126 of Cl, its magnitude being controlled by Vw. When a spike, or other signal event, from a pre-synaptic neuron device (not shown) is applied to the gate 128 of C2, the charge under gate 126 transfers to the output 130 resulting in an output signal, typically a spike current, being generated at electrode 127, the magnitude of which is dependent on Vw. During this non-equilibrium condition, the depletion layer under Cl widens and acts as a virtual drain for Tl. Therefore, a sub threshold current flows in Tl causing the region under Cl to fill with charge and thereafter to fall to zero. The operation of the device 120 is transient as it depends on the potential induced by the deep depletion condition under Cl . By varying Vj₁ on Tl, the magnitude of the injector current from Tl to the region under Cl is variable and so Vn controls the rate at which the region fills with charge. Synapse devices embodying the invention may readily be associated with, e.g. connected to, one or more pre-synaptic and/or post synaptic neuron devices or structures to form a neuron cell. Any conventional electronic neuron device may be used to provide the functionality of the pre-synaptic and/or post synaptic neuron. For example, the, or each, post synaptic neuron structure may comprise a multi-input floating gate MOSFET, or similar device, the output signal of one or more electronic synapse device providing the input at a respective gate of the MOSFET or similar device.

The invention is not limited to the embodiment described herein and may be modified or varied without departing from the scope of the invention.

Claims

CLAIMS:

1. An electronic synapse device comprising a substrate formed from semiconductor material; a plurality of inputs including a first input for receiving a weighting signal, and a second input for receiving a signal from a pre-synaptic neuron device; an insulating layer provided between said inputs and said semiconductor material; and an output, the second input being located between said first input and said output, and wherein an electrical charge storage region is provided in the substrate substantially in register with said first input, the device further including an electrical charge source that is operable to transfer electrical charge into said electrical charge storage region.

2. A device as claimed in claim 1, further including a third input for receiving a first control signal, the first input being located between said second and third inputs, and the electrical charge source being operable to transfer electrical charge into said electrical charge storage region by application of said first control signal to said third input.

3. A device as claimed in claim 1 or 2, wherein said electrical charge source comprises a first doped region in the substrate, said first doped region being located adjacent an oppositely doped first charge transfer region in the substrate to create a semiconductor junction in the substrate, said first transfer region being located between said first doped region and said charge storage region.

4. A device as claimed in claim 3 when dependent on claim 2, wherein said first charge transfer region is located substantially in register with said third input.

5. A device as claimed in claim 3 or 4, wherein said first doped region is electrically connected to a reference potential.

6. A device as claimed in any one of claims 3 to 5, wherein the arrangement is such that the biasing of said semiconductor junction is determined in use by said first control signal.

7. A device as claimed in any preceding claim, wherein the device further includes a fourth input for receiving a second control signal, the fourth input being located between said first input and said output, and wherein a second charge transfer region is provided in said substrate substantially in register with said fourth input, the arrangement being such that charge is transferable in use from said charge storage region to said output via said second transfer region under the control of said second control signal.

8. A device as claimed in any preceding claim, wherein said electrical charge source, said electrical charge storage region, and said first input are arranged to form a first transistor, wherein the source of said first transistor is provided by said electrical charge source, its drain is provided by said electrical charge storage region, and its gate is provided by said first input.

9. A device as claimed in claim 7 or 8, wherein said electrical charge storage region, said region of the substrate substantially in register with said second input, and said fourth input are arranged to form a second transistor, wherein the source of the second transistor is provided by said electrical charge storage region, its drain is provided by the region of the substrate substantially in register with the second input, and its gate is provided by said fourth input.

10. A device as claimed in claim 8 or 9, wherein said first input and the respective regions of said insulating layer and said substrate that are in register with said first input, together comprise a first capacitor, said first capacitor being located between said first transistor and said output.

11. A device as claimed in any one of claims 8 to 10, wherein said second input and the respective regions of said insulating layer and said substrate that are in register with said second input, together comprise a second capacitor, said second capacitor being located between said first capacitor and said output.

12. A device as claimed in claim 11 when dependent on claim 9, wherein said second transistor is located between said first and second capacitors.

13. A device as claimed in any preceding claim, wherein said output comprises a charge collector, preferably comprising a region of said substrate doped to create a semiconductor junction in said substrate.

14. An electronic neural structure comprising a pre-synaptic neuron device and a post-synaptic neuron device in communication with one another by means of at least one electronic synapse device as claimed in claim 1.