WO2008100843A4 - Correction of voltage offset and clock offset for sampling near zero-crossing point - Google Patents

Correction of voltage offset and clock offset for sampling near zero-crossing point Download PDF

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Publication number
WO2008100843A4
WO2008100843A4 PCT/US2008/053552 US2008053552W WO2008100843A4 WO 2008100843 A4 WO2008100843 A4 WO 2008100843A4 US 2008053552 W US2008053552 W US 2008053552W WO 2008100843 A4 WO2008100843 A4 WO 2008100843A4
Authority
WO
WIPO (PCT)
Prior art keywords
signal
edge
circuit
offset
sampler
Prior art date
Application number
PCT/US2008/053552
Other languages
French (fr)
Other versions
WO2008100843A2 (en
WO2008100843A3 (en
Inventor
Andrew M Fuller
John Poulton
Original Assignee
Rambus Inc
Andrew M Fuller
John Poulton
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rambus Inc, Andrew M Fuller, John Poulton filed Critical Rambus Inc
Priority to EP08743452A priority Critical patent/EP2111710A2/en
Priority to US12/525,044 priority patent/US8199866B2/en
Publication of WO2008100843A2 publication Critical patent/WO2008100843A2/en
Publication of WO2008100843A3 publication Critical patent/WO2008100843A3/en
Publication of WO2008100843A4 publication Critical patent/WO2008100843A4/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
    • H04L25/063—Setting decision thresholds using feedback techniques only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0278—Arrangements for impedance matching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45008—Indexing scheme relating to differential amplifiers the addition of two signals being made by a resistor addition circuit for producing the common mode signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45306—Indexing scheme relating to differential amplifiers the common gate stage implemented as dif amp eventually for cascode dif amp
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45588—Indexing scheme relating to differential amplifiers the IC comprising offset compensating means
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Abstract

Embodiments of a circuit are described. This circuit includes a receiver circuit including a first sampler (312-1) and a second' sampler (312-2). A clock-data-recovery circuit (324) in the receiver circuit adjusts a sample time of the receiver circuit so that the sample time is proximate to a signal crossing point at an edge of an eye pattern associated with received signals. An offset-calibration circuit (326) in the receiver circuit determines and adjusts an offset voltage of a given sampler, which can be the first sampler or the second sampler. This offset-calibration circuit may determine a present offset voltage (412) of the given sampler in a timing region proximate to the signal crossing point (410-2) in which the clock-data-recovery circuit dithers about a present sample time based on the present offset voltage. Additionally, the clock-data-recovery circuit and the offset-calibration circuit may iteratively converge on the signal crossing point and a residual offset voltage of the given sampler.

Claims

29AMENDED CLAIMS received by the International Bureau on 28 January 2009 (28.01.2009)
1. A receive circuit, comprising! a receiver that samples a signal; a phase alignment circuit that detects an edge of the signal; and an offset-calibration circuit coupled to the phase alignment circuit to correct, responsive to correlation of specific signal patterns with edge timing represented by the signal, receiver voltage offset associated with sampling the signal in dependence upon detected correlation,
2. The receive circuit of claim i , where the offset-calibration circuit corrects for receiver voltage offset to urge the sampler toward a level where specific signal transitions are not correlated with an early or late edge timing, to thereby cause the phase alignment circuit to dither about an expected data transition edge notwithstanding inherent receiver voltage offset associated with sampling of the signal.
3. The receive circuit of claim 1, where: the receiver include a first sampler and a second sampler; the first sampler samples a voltage level associated with an expected edge of the signal; the second sampler samples digital values represented by the signal; and the offset-calibration circuit corrects for voltage offset associated with the first sampler to urge the first sampler toward a level where the specific signal patterns are not correlated with an early or late edge timing.
4. The receive circuit of claim 3, where: the samplers collectively generate a set of at least three samples associated with each one of plural edge crossings in the signal; 30
the sets are used to detect occurrence of a predetermined data pattern within the sets; and, for sets where occurrence exists, to detect correlation between the predetermined data pattern and an early/late trend for edge crossings represented by each corresponding set; and the offset-calibration circuit adjusts a voltage offset correction responsive to detected correlation.
5. The receive circuit of claim 4, where the offset calibration-circuit varies the threshold by a first polarity if correlation is detected that indicates that an actual edge tends to be early with respect to an expected edge for a first signal transition and late with respect Io the expected edge For a second signal transition, and by a second polarity if correlation is delected that indicates that actual edge variation tends to be late with respect to the expected edge for the first signal transition and early with respect to the expected edge for the second signal transition.
6. The receive circuit of claim 4, where: the offset-calibration circuit corrects receiver voltage offset by increasing an effective receiver sampling threshold in response to (i) correlation of an early edge crossing with a low- to-high logic transition and (ii) correlation of a late edge crossing with a high-to-low logic transition; and the offset-calibration circuit corrects receiver voltage offset by decreasing the effective receiver sampling threshold in response Io (iii) correlation of a late edge crossing with a low- to-high logic transition and (iv) correlation of an early edge crossing with a high-to-low logic transition.
7. The receive circuit of claim 3, where the two samplers sample the signal using a phase separation of approximately ninety degrees.
8. The receive circuit of claim 3, further comprising: means for switching roles of the two samplers; and means for correcting offset for each of the two samplers during a calibration mode,
9. The receive circuit of claim 1, where the signal is a binary signal.
10. The receive circuit of claim 1, embodied as a memory device.
1 1 „ The receive circuit of claim 1 , embodied as a memory controller.
12. The receive circuit of claim 1 , further comprising a mode in which voltage offset is calibrated and corrected.
13. The receive circuit of claim 1 , wherein the phase alignment circuit is part of a clock recovery circuit that recovers the receiver clock from the signal.
14. A receive circuit, comprising: a first sampler to sample edge crossings of a signal; a second sampler to sample data values of the signal; a phase adjustment circuit to generate an adjusted phase based upon sampled edge crossings and to provide the adjusted phavse to the second sampler to time the sampling of the data values; and an offset-calibration circuit to provide a voltage offset correction to adjust the sampling of edge crossings by the second sampler; where 32
the offset-calibration circuit is adapted to respond Io correlation between specific data value transition patterns and timing of edge crossings by adjusting the voltage offset correction in an iterative manner to reduce detected correlation, and the phase adjustment circuit is adapted to converge on an edge crossing point of the signal based upon the voltage offset correction.
15, The receive circuit of claim 13, where the first sampler and the second sampler are controlled to perform sampling at relative times defined by a fixed receiver clock phase difference.
16. The receive circuit of claim 14, where the fixed receiver clock phase difference is ninety degrees.
17. A receive circuit, comprising: a phase detector to adjust a clock phase dependent upon a signal edge crossing; an offset-calibration circuit to correct voltage offset to adjust voltage level of the edge crossing relative to the signal in response to correlation between (i) early/late tendencies of the signal with respect to the expected edge crossing, and (ii) at least one specific signal transition pattern, the offset-calibration circuit; and a sampler to sample the signal using the clock phase
18. The receive circuit of claim 16, where the phase detector is an Alexander phase detector.
19. The receive circuit of claim 16 embodied in a system, the system also comprising memory and control logic, the memory to store information representing edge samples, the control logic to detect the correlation from the information stored in the memory and to control the offset-cancelation circuit to correct voltage offset. 33
20. The receive circuit of claim 16, where: the receive circuit further comprises a second sampler used to sample edge crossings, where the offset-calibration circuit is coupled to the second sampler to correct voltage offset in lhc second sampler; and the receive circuit further comprises circuitry to switch the role of each of the samplers, lo alternatively correct voltage offset in each of the samplers.
21. A method of determining an voltage offset in a receiver circuit, comprising: detecting data level transitions in a digital signal; detecting data edges in the digital signal; detecting occurrence of at least one predetermined pattern based on the data level transitions; monitoring correlation between an carly/Iate tendency of the data edge and at least one predetermined signal pattern, and responsivcly adjusting voltage offset associated with detecting the data edges.
22. The method of claim 20, where detecting data edges includes detecting data edges based on adjusted voltage offset, and where the method further comprises generating a receiver clock based upon adjusted voltage offset.
23. The method of claim 20, further comprising using multiple samplers, selectively reassigning sampler function for use in sampling data edges, and independently adjusting Voltage offset of each samplers to independently for each sampler reduce correlation between an early/late tendency of the data edge with at least one predetermined signal pattern.
24. A method, comprising: 34
sampling edge crossings of a signal; sampling data values of the signal; adjusting phase based upon sampled edge crossings and using the adjusted phase to time the sampling of the data values; and detecting correlation between specific data value transition patterns and timing of edge crossings; adjusting voltage offset associated with sampling of the edge crossings in an iterative manner to reduce detected correlation; and converging on an edge crossing point of the signal based upon the voltage offset correction.
25. An apparatus comprising instructions stored on machine-readable media, the instructions when executed adapicd to cause a machine to: detect data level transitions in a digital signal; detect data edges in the digital signal; detect occurrence of at least one predetermined pattern based on the data level transitions; monitor correlation between an early/late tendency of the data edge with at least one predetermined signal pattern; and responsive to correlation, adjust voltage offset associated with detecting the data edges.
26, A computer-readable medium containing data representing a receive circuit, where the receive circuit includes: a phase detector to adjust a clock phase dependent upon a signal edge crossing; an offset-calibration circuit to correct voltage offset in response Io correlation between (i) early/late tendencies of the signal with respect to the expected edge crossing, and (ii) at least one specific signal transition pattern, the offset-calibration circuit correcting voltage offset to adjust voltage level of the edge crossing relative to the signal; and 35
a sampler to sample an input signal using the clock phase.
27. The computer-readable medium of claim 25, where the receive circuit is embodied in a memory controller that includes memory and control logic, the memory to store information representing edge samples, lhe control logic to detect the coirelatϊon from the information stored in Lhe memory and to control the offset-cancelation circuit to correct voltage offset,
28. The computer-readable medium of claim 26, where the control logic is at least partially embodied as instructional logic.
29. The computer-readable medium of claim 25, where: the receive ciicuit further comprises a second sampler used to sample edge crossings, where the offset-calibration circuit is coupled to the second sampler to correct voltage offset in the second sampler; and lhe leceive circuit further comprises circuitry to switch the role of each of the samplers, to alternatively correct voltage offset in each of the samplers.
PCT/US2008/053552 2007-02-12 2008-02-11 Correction of voltage offset and clock offset for sampling near zero-crossing point WO2008100843A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP08743452A EP2111710A2 (en) 2007-02-12 2008-02-11 Correction of voltage offset and clock offset for sampling near zero-crossing point
US12/525,044 US8199866B2 (en) 2007-02-12 2008-02-11 Edge-based sampler offset correction

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US90080407P 2007-02-12 2007-02-12
US60/900,804 2007-02-12

Publications (3)

Publication Number Publication Date
WO2008100843A2 WO2008100843A2 (en) 2008-08-21
WO2008100843A3 WO2008100843A3 (en) 2009-02-12
WO2008100843A4 true WO2008100843A4 (en) 2009-04-16

Family

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Family Applications (3)

Application Number Title Priority Date Filing Date
PCT/US2008/001826 WO2008100494A2 (en) 2007-02-12 2008-02-11 Differential receiver with common-gate input stage
PCT/US2008/053552 WO2008100843A2 (en) 2007-02-12 2008-02-11 Correction of voltage offset and clock offset for sampling near zero-crossing point
PCT/US2008/001869 WO2008100523A2 (en) 2007-02-12 2008-02-12 Low-power clock generation and distribution circuitry

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PCT/US2008/001826 WO2008100494A2 (en) 2007-02-12 2008-02-11 Differential receiver with common-gate input stage

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Application Number Title Priority Date Filing Date
PCT/US2008/001869 WO2008100523A2 (en) 2007-02-12 2008-02-12 Low-power clock generation and distribution circuitry

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US (3) US8199866B2 (en)
EP (2) EP2111709A2 (en)
JP (1) JP2010518749A (en)
CN (1) CN101606365A (en)
WO (3) WO2008100494A2 (en)

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US8199866B2 (en) 2012-06-12
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US8310294B2 (en) 2012-11-13
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EP2111709A2 (en) 2009-10-28
WO2008100494A2 (en) 2008-08-21

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