WO2008100843A3 - Correction of voltage offset and clock offset for sampling near zero-crossing point - Google Patents

Correction of voltage offset and clock offset for sampling near zero-crossing point Download PDF

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Publication number
WO2008100843A3
WO2008100843A3 PCT/US2008/053552 US2008053552W WO2008100843A3 WO 2008100843 A3 WO2008100843 A3 WO 2008100843A3 US 2008053552 W US2008053552 W US 2008053552W WO 2008100843 A3 WO2008100843 A3 WO 2008100843A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
offset
sampler
crossing point
clock
Prior art date
Application number
PCT/US2008/053552
Other languages
French (fr)
Other versions
WO2008100843A2 (en
WO2008100843A4 (en
Inventor
Andrew M Fuller
John Poulton
Original Assignee
Rambus Inc
Andrew M Fuller
John Poulton
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rambus Inc, Andrew M Fuller, John Poulton filed Critical Rambus Inc
Priority to EP08743452A priority Critical patent/EP2111710A2/en
Priority to US12/525,044 priority patent/US8199866B2/en
Publication of WO2008100843A2 publication Critical patent/WO2008100843A2/en
Publication of WO2008100843A3 publication Critical patent/WO2008100843A3/en
Publication of WO2008100843A4 publication Critical patent/WO2008100843A4/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
    • H04L25/063—Setting decision thresholds using feedback techniques only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0278—Arrangements for impedance matching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45008—Indexing scheme relating to differential amplifiers the addition of two signals being made by a resistor addition circuit for producing the common mode signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45306—Indexing scheme relating to differential amplifiers the common gate stage implemented as dif amp eventually for cascode dif amp
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45588—Indexing scheme relating to differential amplifiers the IC comprising offset compensating means
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Abstract

Embodiments of a circuit are described. This circuit includes a receiver circuit including a first sampler (312-1) and a second' sampler (312-2). A clock-data-recovery circuit (324) in the receiver circuit adjusts a sample time of the receiver circuit so that the sample time is proximate to a signal crossing point at an edge of an eye pattern associated with received signals. An offset-calibration circuit (326) in the receiver circuit determines and adjusts an offset voltage of a given sampler, which can be the first sampler or the second sampler. This offset-calibration circuit may determine a present offset voltage (412) of the given sampler in a timing region proximate to the signal crossing point (410-2) in which the clock-data-recovery circuit dithers about a present sample time based on the present offset voltage. Additionally, the clock-data-recovery circuit and the offset-calibration circuit may iteratively converge on the signal crossing point and a residual offset voltage of the given sampler.
PCT/US2008/053552 2007-02-12 2008-02-11 Correction of voltage offset and clock offset for sampling near zero-crossing point WO2008100843A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP08743452A EP2111710A2 (en) 2007-02-12 2008-02-11 Correction of voltage offset and clock offset for sampling near zero-crossing point
US12/525,044 US8199866B2 (en) 2007-02-12 2008-02-11 Edge-based sampler offset correction

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US90080407P 2007-02-12 2007-02-12
US60/900,804 2007-02-12

Publications (3)

Publication Number Publication Date
WO2008100843A2 WO2008100843A2 (en) 2008-08-21
WO2008100843A3 true WO2008100843A3 (en) 2009-02-12
WO2008100843A4 WO2008100843A4 (en) 2009-04-16

Family

ID=39388278

Family Applications (3)

Application Number Title Priority Date Filing Date
PCT/US2008/053552 WO2008100843A2 (en) 2007-02-12 2008-02-11 Correction of voltage offset and clock offset for sampling near zero-crossing point
PCT/US2008/001826 WO2008100494A2 (en) 2007-02-12 2008-02-11 Differential receiver with common-gate input stage
PCT/US2008/001869 WO2008100523A2 (en) 2007-02-12 2008-02-12 Low-power clock generation and distribution circuitry

Family Applications After (2)

Application Number Title Priority Date Filing Date
PCT/US2008/001826 WO2008100494A2 (en) 2007-02-12 2008-02-11 Differential receiver with common-gate input stage
PCT/US2008/001869 WO2008100523A2 (en) 2007-02-12 2008-02-12 Low-power clock generation and distribution circuitry

Country Status (5)

Country Link
US (3) US8199866B2 (en)
EP (2) EP2111709A2 (en)
JP (1) JP2010518749A (en)
CN (1) CN101606365A (en)
WO (3) WO2008100843A2 (en)

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EP2111710A2 (en) 2009-10-28
WO2008100494A3 (en) 2008-12-24
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WO2008100843A2 (en) 2008-08-21
WO2008100523A3 (en) 2008-12-04
US20100085100A1 (en) 2010-04-08
WO2008100523A4 (en) 2009-01-29
WO2008100494A4 (en) 2009-02-12
US20100066450A1 (en) 2010-03-18
JP2010518749A (en) 2010-05-27
WO2008100494A2 (en) 2008-08-21
US20100220828A1 (en) 2010-09-02
WO2008100843A4 (en) 2009-04-16
WO2008100523A2 (en) 2008-08-21
EP2111709A2 (en) 2009-10-28
US8199866B2 (en) 2012-06-12
US8310294B2 (en) 2012-11-13

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