WO2008018769A1 - A circular voltage-controlled phase shifter - Google Patents

Abstract

A circular voltage-controlled phase shifter (VCPS) configured to have actually unlimited phase shift range is invented. This is made possible by configuring the system to operate in a circular way differently from the conventional finite VCPS which operates in a linear way, so, whose phase output saturates as the phase control input exceeds some value. The preferred circular VCPS is composed of a vector modulationbased VCPS, a reset block, a control block. In particular, the invented VCPS shows an excellent linear phase shifting characteristic with respect to the control signal due to the vector modulation by a modulation signal with a pseudo-sinusoidal transfer curve as a function of the control signal. The modulation signal generator exploits the currentvoltage (IV) curve of a MOS differential amplifier pair. Thanks to this, the invented circular VCPS is appropriate for implementation in analogue CMOS circuit.

Description

Description A CIRCULAR VOLTAGE-CONTROLLED PHASE SHIFTER

Technical Field

[1] This invention relates to a phase control mechanism, and more specifically to a voltage-controlled phase shifter, a voltage-controlled frequency shifter and their application to phaselocked loopbased systems employed in a communication transceiver so as to substantially extend the control signal range and the phase shifting range. Background Art

[2] The voltage-controlled phase shifter (VCPS) is a phase shifter which shifts the phase of input RF (or, IF) signal by an amount in proportion to a control voltage input. It finds application in many electronic devices like phaselocked loop (PLL), delay locked loop (DLL) and other phase controlling systems. In particular, there were several attempts to apply a VCPS to multiple antenna receivers or beamformer. Among them, [Ref 1] tried to produce an enhanced signal quality by adjusting the phases of signals received at the multiple antennas and combining them.

[3]

[4] [Ref 1] F. Ellinger and et. Al., "Ultracompact reflectivetype phase shifter mmic at cband with 360 degrees phasecontrol range for smart antenna combining," IEEE JSSC, pp.481486, Apr. 2002.

[5]

[6] A problem is that the variable range of the output phase is limited to some value (for example, 180 degrees) under normal CMOS process, and their common interest was to extend the limit using additional circuitry. In this invention, we call the VCPS with a finite phase range a finite VCPS in short. Another problem still remains even if a full phase shift range (360 degrees) is achieved. When a phase control system (e.g., PLL) operates in an autonomous way, the control voltage may exceed a value corresponding to the maximum phase shift (360 degrees) during operation. Without any other means, the control system is highly likely to be stuck at some boundary point. Because of the problem, the above beamformers with the finite VCPS are provided with necessary phase control information, which is confined within 360 degrees range, from a separate baseband signal processor. Obviously, this makes the system quite complex. In this case, it can be a solution to have a means to reset the controlled phase to zero phase shift with a phase domain change being made in some way when the controlled phase reaches the boundary point. By doing so, instead of being stuck at the boundary point, the control mechanism can operate in an autonomous way. In other words, the VCPS should operate in a circular way, as is described in this invention, in order that the phase control system can work in a standalone way.

[7]

[8] In general, the VCPS is a device which takes in a RF sinusoidal signal and outputs its phaseshifted version whose phase is shifted by an amount commanded by a control voltage. Here, the input sinusoid includes both a continuous wave from a local oscillator with a fixed frequency and a narrow band RF (or IF) signal. Mathematically saying, the input sinusoid and the phaseshifted output sinusoid can be expressed as

and v_out it) = Ait) ^■ sm{2φ + θit) + o(y_cori )}

, respectively Here, A(t) and θ(t) mean the amplitude and phase of the input sinusoid which may be modulated according to a certain modulation format. Also, f and φ(v ) c con mean the center frequency of the reference sinusoid and the phase shift as a function of the control voltage v , respectively. We will explain the principle of the circular

VCPS referring to Fig 1. [9] [10] Basically, the finite VCPS, which has been often used in conventional phase control systems, has a transfer curve (101) with a finite input control voltage range v_Mn e [-v₀.v₀] and a finite output phase shift range

as depicted in Fig. 1 (A). Therefore, the finite VCPS operates in a linear way in the control range, but saturates at a certain value beyond the range. This can cause a serious problem when the finite VCPS is put in a control loop and operated in an autonomous way. The control voltage of the finite VCPS may happen to exceed the fixed range during operation, then the control loop will end up being stuck there. On the contrary, the invented circular VCPS operates in a circular way in order to overcome the problem of the finite VCPs.

[H]

[12] To solve the problem, first, we generate L replicas of the input sinusoid whose i th replica is phaseshifted by (ι-l)-φ where i=l,...,L and φ =360°/L Then, we configure them so that the transfer curve of the system will operate along the curves (103), (105), (107) with the direction indicated in Fig. 1 (B) as v vanes. Note that the curves con

(103), (105), (107) correspond to the 2nd, 1st, L th phaseshifted version (i.e., phase domain), respectively. The curve (107) is the L th phaseshifted version because the L th phaseshifted version has phase shifting by (L-l)-φ =-φ using Lφ =360°. Assuming an initial operating point at (b), φ(v ) will move along the 1st phase domain con

((a)(b)(c)) in (103) as long as v lies in [-v , v ]. However, when v reaches v , the con 0 0 con 0 phase domain switches to the 2nd phase domain and φ(v ) will move along the 2nd con phase domain ((d)(e)(f)) in (103) starting from (e). That is, v resets to zero while φ con keeps the same value. On the other hand, when v reaches -v , the phase domain con 0 switches to the L th phase domain and φ(v ) will move along the L th phase domain con

((g)(h)(i)) in (107) starting from (h). That is, v resets to zero while φ keeps the same con value. The phase shift range can be extended infinitely according to the above method. Unwrapping the v range in xaxis each time the reset of v happens, the desired con con

VCPS characteristics with infinite input phase control voltage range and infinite output phase shift range are obtained as depicted in Fig. 28 (C). Because the L phase domains cover 360° and repeats the same 360° phase shifting in a circular way each time v con crosses multiple of L-v , the VCPS is called a circular VCPS. Note that this curve has a o hysterisis characteristic. That is, starting from (g), it will follow the path connecting (g)(h)(i)(b)(c)(e)(f) as v increases. However, starting from (f), it will follow a con different path (f)(e)(d)(b)(a)(h)(g) as v decreases. The reason why the hysterisis char- con acteristic is introduced is to avoid a phase domain bouncing at the phase domain switching point.

[13]

[14] A prior art similar to the invented circular VCPS is found in [Ref 2]:

[15]

[16] [Ref 2]: T. H. Lee and K. S. Donnelly and T.C. Ho, "Voltage controlled phase shifter with unlimited range", U.S. Patent 5,554,945, 1996. Disclosure of Invention Technical Problem

[17] The [Ref 2] also exploits the circular operation to achieve unlimited output phase range. However, because it is basically designed for phase shifting of digital signals whereas the invented VCPS is for phase shifting of analogue signals, direct comparison between the two is not appropriate. Also, the implementation details of the two are quite different. For example, the phase shifting mechanism of [Ref 2] is not so linear with respect to the control signal whereas that of the current invention shows an excellent linear phase shifting characteristics exploiting a pseudosinusoidal characteristic of the MOS transistor. In addition, the [Ref 2] did not consider hysterisis in the phase domain change whereas the current invention introduced the hysterisis mechanism in the phase domain change so as to avoid the phase domain bouncing problem. Therefore, the invented circular VCPS shows superior performance to that of [Ref 2] even if the two are directly compared. Technical Solution

[18] According to an aspect of an exemplary embodiment of the present invention, there is provided a voltage-controlled phase shifter (VCPS) with an input sinusoid, an output sinusoid and a phase control signal input, the voltage controlled phase shifter comprising : a vector modulation-based VCPS configured to generate a continuously phaseshifted version of an input sinusoid in accordance to a phase control signal; a control block configured to receive necessary information signals including a Sign signal and to generate necessary control signals including a Switch signal, a Clear signal and a Freeze signal; and a reset block configured to pass said phase control signal to said vector modulationbased VCPS in normal operation and to reset its output to zero in accordance to said clear signal from said control block.

[19] According to another aspect of an exemplary embodiment of the present invention, there is provided a voltage-controlled frequency shifter (VCFS) with an input sinusoid, an output sinusoid and a frequency control signal input, the voltage controlled frequency shifter comprising: the VCPS wherein said reset block in said VCPS is replaced by said integrator outside said VCPS; a integrator is configured to store phase information and to dump its output to zero when a clear signal is activated from said control block as well as to integrate said frequency control signal.

[20] The voltage-controlled phase shifter (VCPS) may further comprise: a IQ splitter configured to split the phase of said input sinusoid into a quadrature sinusoid pair of said input sinusoid; a modulation signal generator configured to generate a pseudo- sinusoidal modulation signal pair in an analogue circuit as a function of said phase control signal input; and a vector modulator configured to modulate said a quadrature sinusoid pair of said input sinusoid by said a pseudo-sinusoidal modulation signal pair in order to generate a phaseshifted version of said input sinusoid.

[21] The voltage controlled phase shifter (VCPS) may further comprise: a pseudo- sinusoidal waveform generation means configured to generate the first intermediate pseudo-sinusoidal modulation signal pair as a function of said phase control signal input with a finite range; a switching means configured to switch said first intermediate pseudo-sinusoidal modulation signal pair to generate the second pseudo-sinusoidal modulation signal pair so that said second pseudo-sinusoidal modulation signal pair suits the required phase domain; a clutching means configured to pass said second pseudo-sinusoidal modulation signal pair in normal operation and to provide a temporary modulation signal pair during the phase domain change period in order to achieve a seamless phase shifting; and a threshold detection means configured to detect a threshold point at which phase domain change must take place, and to generate a logic level to said control block. [22] The clutching means may be realized as a sample and hold block configured to pass said modulation signal pair while operating within a phase domain, and to sample and hold said modulation signal pair in a phase domain change period according to a Freeze signal activated from said control block , in order to achieve smooth phase domain changeover.

[23] The threshold detection means may be realized as a zero crossing detector configured to detect a zero crossing point of either of said modulation signal pair and to generate a Sign signal, and apply it to said control block .

[24] The control block may comprise a finite state machine configured to receive phase domain change information like a Sign signal from said threshold detection means, and to change its state in an appropriate way, and to generate necessary control signals like a Switch signal, a Clear signal, and a Freeze signal, and to apply them to said switching means, to said reset block, and said clutching means, respectively.

[25] According to another aspect of an exemplary embodiment of the present invention, there is provided a modulation signal generator configured to generate a pseudo- sinusoidal waveform pair as a function of a phase control control signal in such a way that: first, the first intermediate pseudo-sinusoidal modulation signal waveforms are generated as a function of said phase control signal within a finite range between an lower and upper boundary points; second, as soon as said phase control signal crosses over either said lower or uppper boundary point, said first intermediate pseudo- sinusoidal modulation signal waveforms are switched to the second intermediate pseudo-sinusoidal modulation signal waveforms, and said phase control signal is reset to zero (phase domain change) so that the second intermediate pseudo-sinusoidal modulation signal waveforms are continuously connected to the previous second intermediate pseudo- sinusoidal modulation signal waveforms as the phase control signal varies; third, said second intermediate pseudo-sinusoidal modulation signal waveforms are passed to the final pseudo-sinusoidal waveform pair when said phase control signal is within said lower and upper boundary points, and sampled and holded while said first intermediate pseudo-sinusoidal modulation signal waveforms are in the process of switching.

[26] A modulation signal generator may be configured to have a fintie number of phase domains which overlap with neighbouring phase domains, and said phase domain change is configured so that the phase shifting has a hysterisis characteristic as a function of said phase control signal.

[27] According to another aspect of an exemplary embodiment of the present invention, there is provided a modulation signal generator comprising: a pseudo- sinusoidal waveform generator configured to generate the first intermediate pseudo-sinusoidal modulation signal pair as a function of said phase control signal input within a finite range; a switch box configured to switch said first intermediate pseudo-sinusoidal modulation signal pair to generate the second pseudo-sinusoidal modulation signal pair so that said second pseudo-sinusoidal modulation signal pair suits the required phase domain, according to a Switch signal activated from a control block; a sample and hold block configured to pass said second pseudo-sinusoidal modulation signal pair while operating within a phase domain, and to sample and hold said second pseudo- sinusoidal modulation signal pair in a phase domain change period, and to generate a final pseudo- sinusoidal modulation signal pair, according to a Freeze signal activated from a control block; a zero crossing detector configured to detect a zero crossing point of either of said first pseudo-sinusoidal modulation signal pair and to generate a logic signal Sign, and apply it to a control block; and a control block comprising a finite state machine configured to receive phase domain change information like a Sign signal from said zero crossing detector and to change its state in an appropriate way, and to generate necessary control signals like a Switch signal, a Clear signal, and a Freeze signal, and to apply them to said switch box, to an outer reset block, and said sample and hold block, respectively.

[28] The modulation signal generator may be configured without said switch box provided that said second intermediate pseudo-sinusoidal modulation signal pair is identical to said first intermediate pseudo-sinusoidal modulation signal pair.

[29] The pseudo-sinusoidal waveform generator may comprises inphase modulation signal generator and quadraturephase modulation signal generator is configured to generate a pseudo-cosine and pseudo-sine modulation signal pair as a function of said phase control signal input for a finite input range.

[30] The pseudo-sine waveform (odd function) may be synthesized by superimposing multiple copies of a basic waveform, where said basic waveform takes the form of pseudo-sine curve in a finite input range, and said copy may be a shifted version in x- axis and/or reversed version in y-axis and/or x-axis of said basic waveform.

[31] The pseudo-cosine waveform (even function) may be synthesized by superimposing multiple copies of a basic waveform and some constant value, where said basic waveform takes the form of quasisine curve in a finite input range, and said copy may be a shifted version in x-axis and/or reversed version in y-axis and/or x-axis of said basic waveform.

[32] The basic waveform may be obtained from the I- V curve (output current vs. input voltage transfer curve) of a transistor pair (e.g., MOS or BJT or any similar devices) in order to achieve an approximation to the true sine waveform, and said copy is obtained by shifting input voltage level and/or reversing input voltage ports and/or output current branches of said transistor or transistor pair.

[33] The basic waveform may be obtained from the I-V curve (output current vs. input voltage transfer curve) of a plural number of said transistor pairs in parallel in order to achieve a better approximation to the true sine waveform.

[34] The basic waveform may be obtained from the I- V curve (output current vs. input voltage transfer curve) of a plural number of said transistor pairs in parallel in order to achieve an approximation to any required waveform.

[35] The shifting input voltage level of said transistor or transistor pair may be achieved by an appropriate adjustment of W/L (width to length ratio) and a bias current of said MOS according to a way exploiting the dependency of the gate-source voltage of the MOS on the inverse-root of W/L and the dependency on the root of the bias current as described in the body or any other similar way for other devices.

[36] The modulation signal generator may further comprise: a pseudo-sinusoidal waveform generation means configured to generate the first intermediate pseudo- sinusoidal modulation signal pair for a finite input range which spans two periods of the sine waveform as a function of said phase control signal input; a clutching means configured to pass said first pseudo-sinusoidal modulation signal pair in normal operation and to provide a temporary modulation signal pair during the phase domain change period in order to achieve a seamless phase shifting; and a threshold detection means configured to detect a threshold point at which phase domain change must take place, and to generate a logic level to said control block.

[37] The pseudo-sinusoidal waveform generation means may be configured to generate; A pseudo-sinusoidal waveform pair for 720 degrees range according to a phase control signal input; and said control block is configured to make phase domain change only when said control signal input reaches either limit values whose phase shifts correspond to 360 degrees and -360 degrees, respectively.

Advantageous Effects

[38] In this invention, we can see that the unlimited phase shifting is achieved in a circular way (except during the phase domain change period), and the phase shifting is almost linear in the normal intervals. The maximum phase deviation from the linear slope due to the nonideality of the pseudosinusoids is measured to be 3.5 degrees. At the same time, the maximum amplitude deviation ratio from the constant envelope is measured to be 2.2 percent. These values are regarded as small enough to demonstrate effectiveness of the invented circular VCPS. Brief Description of the Drawings

[39] These and other aspects of the present invention will become more apparent and more readily appreciated from the following description of exemplary embodiments thereof, with reference to the accompanying drawings, in which:

[40] Figure 1 is (A) transfer curve of a finite VCPS, (B) transfer curve example of the circular VCPS, (C) Unwrapped transfer curve of the circular VCPS according to the current invention.

[41] Figure 2 is a block diagram of the invented circular VCPS.

[42] Figure 3 is a block diagram of the invented circular VCFS.

[43] Figure 4 is an embodiment example of the invented vector modulationbased VCPS

(VMVCPS). [44] Figure 5 is transfer curves of (A) pseudocosine waveform (v ), (B) pseudosine mod-I-l waveform ( v ) and (C) output phase shift characteristic φ(v ) as a function of v mod-Q-l con con

[45] Figure 6 is required modulation signal pairs ( v , v ) for the respective phase mod- 1-2 mod-Q-l domains Dl D4 (ex: L = 4).

[46] Figure 7 is a state transition diagram of the control box.

[47] Figure 8 is transfer curves of (A) v , (B) v and generation of common mod-I-l mod-Q-l control signals (C) Signl, (D) SignQ, (E) Clear, (F) Freeze to and from the control box as a function of v . con

[48] Figure 9 is (A) a basic differential amplifier pair and (B) its IV curve.

[49] Figure 10 is (A) a double differential amplifier pair and (B) its IV curve.

[50] Figure 11 is (A) an extended differential amplifier pair with input voltage offset and

(B) its IV curve. [51] Figure 12 is (A) transfer curve of pseudocosine waveform (v ) as a function of v mod-I-l and (B)(D) necessary IV curves for its synthesis. con

[52] Figure 13 is (A) transfer curve of pseudosine waveform ( v ) as a function of v mod-Q-l con and (B)(D) necessary IV curves for its synthesis. [53] Figure 14 is an embodiment of pseudocosine waveform generator ( v ). mod-I-l

[54] Figure 15 is an embodiment of pseudosine waveform generator ( v ). mod-Q- 1

[55] Figure 16 is an example of sample and hold block.

[56] Figure 17 is an example of IQ splitter.

[57] Figure 18 is an example of vector modulator.

[58] Figure 19 is the second embodiment example of the invented vector modulationbased

VCPS (VMVCPS). [59] Figure 20 is transfer curves of (A) pseudocosine (v ), (B) pseudosine (v ) mod-I-l mod-Q-l and output phase shift characteristic φ(v ) as a function of v for the second embod con con iment. [60] Figure 21 is (A) transfer curve of v mod-I-l , (B) transfer curve of v mod-Q-l and generation of control signals (C) Signl, (D) SignQ, (E) Clear, (F) Freeze to and from the control box for the second embodiment example.

[61] Figure 22 is a state transition diagram of the control box for the second embodiment.

[62] Figure 23 is (A) transfer curve of v as a function of v , and (B)(H) necessary IV mod-i-l con curves for its synthesis. [63] Figure 24 is (A) transfer curve of v as a function of V , and (B)(F) necessary mod-Q-l con

IV curves for its synthesis. [64] Figure 25 is an embodiment of v generator for the second embodiment example. mod-I-l

[65] Figure 26 is an embodiment of v generator for the second embodiment example. mod-Q- 1

[66] Figure 27 is (A) generated pseudocosine (v ) and pseudosine (v ) waveforms, mod-I mod-Q

(B) phase shifting characteristic, (C) amplitude variation characteristic. Best Mode for Carrying Out the Invention

[67] Structure:

[68] The block diagram of the invented circular voltage-controlled phase shifter (VCPS) is shown in Fig. 2. The circular VCPS (201) is composed of a vector modulationbased VCPS (denoted VMVCPS) (203) and a control block (denoted CONTROL) (205) and a reset block (denoted RESET) (207). It has a RF input sinusoid v (209), a RF output in sinusoid v (211) and a phase control signal v (213). It has also internal control out con signals like Clear (221), Sign (219), Freeze (215) and Switch (217). Assuming v is con inside boundary points, v is forwarded to VMVCPS as it is and shifts the phase of v con m and produces its phaseshifted version v . When v goes beyond either boundary out con point, the control block detects the event through Sign signal from VMVCPS, and sends Clear signal to the reset block. Then, the remainder (223) after subtracting the boundary value from v is applied to the VMVCPS, and carries out the same con operation as above. Other control signals like Freeze and Switch are used to control VMVCPS. [69] The block diagram of the invented circular voltage-controlled frequency shifter

(VCFS) is shown in Fig. 3. The VCFS is obtained by substituting the reset block with an integrator with a reset functionality. Therefore, it is composed of a vector modulationbased VCPS (denoted VMVCPS) (303) and a control block (denoted CONTROL) (305) and an integrator block (denoted INT) (307). It has a RF input sinusoid v (309), in a RF output sinusoid v (311) and a phase control error signal v (323) (or frequency out err control signal). The output of the integrator becomes the phase control signal v con

(313). It has also internal control signals like Clear (321), Sign (319), Freeze (315) and Switch (317 ). Its operation is almost the same as that of the VCPS except that its control input is the phase control error signal, instead of phase control signal. The phase control error signal becomes the phase control signal after the integrator. Due to the integration operation, the VCFS shifts the center frequency of the input sinusoid as much as commanded by the frequency control signal (so, the name VCFS). Because many closed loop phase control systems generate the phase control error signal and employ an integrator in front of the VCPS, the above combined structure VCFS (VCPS (301) and INT (307)) is very useful. Especially, this structure has advantage that it can conserve the phase information explicitly in the integrator (a kind of memory) and can reuse it for some purpose. For example, in a beamforming system under timedivision duplexing (TDD) system, the phase information obtained from the receive beamforming can be reused for the transmit beamforming by storing it in the integrator. In such reasons, we will describe the invented circular VCPS assuming existence of the integrator although the integrator is not necessary component of the circular VCPS itself.

[70] The vector modulationbased VCPS (VMVCPS) (203) (303) plays a central role in the circular VCPS. The block diagram of an embodiment example of the VMVCPS is shown in Fig. 4. The VMVCPS comprises a modulation signal generator (denoted MODULATION SIG GEN) (405), a IQ splitter (denoted IQ SPLITTER) (401), a vector modulator (denoted VECTOR MODULATOR) (403).

[71] The modulation signal generator (405) is again composed of a pseudocosine waveform generator (denoted PSEUDOCOS GEN) (409), a pseudosine waveform generator (denoted PSEUDOSIN GEN) (411), a control signal switch box (denoted SWITCH BOX) (415), a sample and hold (denoted S/H) (417) and a zero crossing detector (denoted ZCD) (413). The combination of the pseudocosine waveform generator and the pseudosine waveform generator is called the pseudosinusoidal waveform generator (denoted PSEUDOSINUSOID GEN) (407).

[72] The IQ splitter (401) splits the RF input sinusoidal signal (denoted v ) (419) into a m quadrature pair (denoted v (421) and v (423)) of v . The modulation signal m-I m-Q m generator produces a quadrature pair of modulation signals (denoted v (437) and v mod- 1

(439)) as a function of v (427) and auxiliary logic signals from the control mod-Q con block. The pseudocosine waveform generator and the pseudosine waveform generator generate the first intermediate quadrature pair (denoted v (429) and v (431)). mod-I-l mod-Q-1

The zero crossing detector detects the zero crossing time of v and v in order mod-I-l mod-Q-1 to generate corresponding Sign signals (denoted Signl (441) and SignQ (443)), respectively, and sends them to the control box in order to notify the current state. The switch box switches v and v into the second intermediate quadrature pair mod-I- 1 mod-Q- 1

(denoted v (433) and v (435)) under control of the Switch signals (denoted mod-I-2 mod-Q-2

Switch 1 (445) and Switch2 (447)) from the control box. The sample and hold generates the final quadrature pair (denoted v (437) and v (439)), which is the mod I mod Q sample and holded version of v and v , under control of the Freeze signal r mod-I-2 mod-Q-2 °

(denoted Freeze) (449) from the control box. The vector modulator performs a vector modulation taking in the inputs such as the quadrature pair of RF input signals (denoted v and v ) from the IQ splitter block and the quadrature pair of m-I m-Q modulation signals (denoted v and v ) from the sample and hold block,

° mod-! mod-Q ^r generating the desired phaseshifted version v (425) of the RF input sinusoidal wave v out as a function of v . m con

[73]

[74] Operation:

[75] Operation of the VMVCPS in Fig. 4 is based on a vector modulation. Let the RF input sinusoidal signal as

^C76] vJt) = A(t) - sm{2πf_ct + θ(t))

(1) [77] where A(t), f and θ(t) are the amplitude, center frequency and phase modulation, if any, of the signal. Then, the ouput sinusoidal signal v should be a phaseshifted out version of v as commanded by the control signal v . That is, in con

^C78] v_out (0 = A(t) ^■ siu{2*# + θ(t) + φ_m ) }

(2) [79] where φ(v ) is the desired phase shift as a function of v . We put A(t)=l for con con convenience. To implement v (t) as expressed in (2), we analyze (2) using a out wellknown trigonometric equality as [^80] v_ouf (t) = BWiUfS + θ(t)}- coφ(v_con)} + cos{2πf_ct + θ(t)} - sin{«>(O}

. (3) [81] From (3), we can see that v (t) can be obtained following the next steps: First, out generate a quadrature pair of the RF input signal as v_m__I (t) = cos{2πf_ct + β(t)} and v_!n__Q(t) = _Sm{2πf_ct + θ(t)}

. Second, generate a quadrature pair of the modulation signal as a function of v as con

and

^V _mod-_fi0,_OJ = sill{{->(v_eoB )}

. Finally, vectormodulate the two quadrature pairs to generate the output signal as [82]

^[83] Vϊ (0 = ^T _1B-β(0 ^{■ v}™d-I<Λ™ ) ^{+ v} _!π-l(0 ^{■ v}mod-β<Λ™ )

[84]

[85] In this invention, for notational convenience, cosine and sine components of any quadrature pair are taken as inphase and quadraturephase components, respectively. Accordingly, their notations have suffix I and Q, repectively.

[86] For the most desired performance, we assume a linear phase shifting characteristic of φ(v ) . That is, con

so that φ(v )=φ , φ(0)=0 and φ(-v )=-φ . Accordingly, the above modulation signal pair can be written as [87]

. (5) [90] [91] In other words, if we generate the modulation signal pair as a function of v as con given by (4) and (5) and apply them to the modulation ports of the vector modulator, the output RF signal will be phaseshifted as much as

con

for some positive φ and v according to

^C92] V₀Jt) }

. (6)

[93]

[94] The above description is the principle of the VMVCPS. The major problem is how to generate the modulation signal pair in (4) and (5) in an analogue circuit. This could be a trivial job if a lookup table is available. However, without employing a lookup table requiring an ADC/DAC pair and a digital circuit, it is not a trivial job to generate the sinusoidal waveform in an analogue circuit as a function of the control signal whose range should extend indefinitely. The method employed in this invention is to generate a pseudosinusoidal waveform for a finite range first (i.e., -v <v <v ), which ap-

0 con 0 proximate the true sinusoidal waveform for the region, and manipulate the waveform in such a way that it can cover the unlimited range of v . con

[95]

[96] Modulation signal generator: [97] An example of the pseudosinusoidal waveforms (denoted v (501) and v mod-I-l mod-Q-1

(503)) are shown in Fig. 5 (A) and (B). They resembles the true cosine and sine waveforms in a finite range of the phase control signal (i.e., -v <v <v ). As a result,

0 con 0 when these waveforms are directly applied to the modulation signal ports (denoted v (437) and v (439)) of the vector modulator in Fig. 4, it will shift the phase of v mod- 1 mod- Q from -φ to φ as v varies from -v to v according to (6) as shown in the curve m 0 0 con 0 0

(505) in Fig. 5 (C). However, the pseudosinusoidal waveforms in this state cannot be extended indefinitely in a sinusoidal fashion due to the hardware limitation of the analogue circuit. In fact, they are saturated at a certain value (so does φ(v ) ) if v con con goes beyond the boundary point.

[98] As a solution for that, we switch the pseudosinusoidal waveforms as the control signal crosses over the boundary values such as v and -v so that the phase shifting characteristic curve can show a circular operation with a proper phase domain change. This phase domain change is realized by using the switch box under control of the switching signals from the control box. The switch box switches the first intermediate quadrature pair (denoted v and v ) to the second intermediate quadrature pair

^{1 r} mod I 1 mod Q l ^{λ r}

(denoted v and v ) under control of the logic signals Switch (denoted Switch 1 mod-I-2 mod-Q-2 and Switch2) from the control box in order to extend the pseudosinusoidal waveform indefinitely. The generation of the modulation signal using the switching mechanism is one of the novelties of the current invention. [99] As a typical example, we divide the whole phase range into four (i.e., L=4) overlapping phase domains: Dl ( -90° to 90° ), D2 ( 0° to 180° ), D3 ( 90° to 270° ), D4 ( -180° to 0°) with φ =90°. They overlap with the neighbouring phase domains in order to have a hysterisis characteristic. An appropriate switching mechanism is shown in Fig. 6. The Fig. 6 (A), (B), (C), (D) describes the required modulation signals (denoted v (solid curve) and v (dashed curve)) for the phase domains Dl, D2, D3, D4, mod-I-2 mod-Q-2 respectively. [100] To help understanding, let us initialize the operation at v =0 (indicated (a¹) in Fig. 6 con

(A)). In Dl, v mod-I-2 is set to c^os(— v_βffl ) is set to

(603). As v increases to reach v (indicated (b)), the phase domain should be con 0 changed from Dl to D2 with v set to mod-I-2 - siii(— O

( set to 2

(607) and v reset to zero ((b¹)). In D2, as v increases to reach v (indicated (c)), the con con O phase domain should be changed from D2 to D3 with v set to mod I 2

- →^- o

(609), v set to mod Q 2

-sπA_cJ vo

(611) and v reset to zero ((c¹)). In D3, as v increases to reach v (indicated (d)), the con con 0 phase domain should be changed from D3 to D4 with v set to mod I 2

( t to

(615) and v reset to zero ((d¹)). In D4, as v increases to reach v (indicated (a)), the con con O phase domain should be changed from D4 to Dl with v set to mod I 2

(601), v mod Q 2 set to

vo (603) and v reset to zero ((a¹)). The above operation repeats in a circular way as v con con keeps on increasing. Through the above way, the pseudosinusoidal waveform can be continued unlimitedly in the positive direction as v increases. con In the same way, the pseudosinusoidal waveforms can be continued unlimitedly in the negative direction as v decreases. Starting from Dl, v is set to con mod I 2

^V0 is set to 2

(603). As v con decreases to reach -v 0 (indicated (f)), the phase domain should be changed from Dl to D4 with v mod I 2 set to sⁱ"(— O

( set to

(615) and v con reset to zero ((d¹)). In D4, as v con decreases to reach -v O (indicated (g)), the phase domain should be changed from D4 to D3 with v mod I 2 set to

(609), v mod Q 2 set to

- si«(— O (611) and v con reset to zero ((c¹)). In D3, as v con decreases to reach -v 0 (indicated (h)), the phase domain should be changed from D3 to D2 with v mod I 2 set to )

( set to

(607) and v con reset to zero ((b¹)). In D2, as v con decreases to reach -v 0 (indicated (i)), the ^r phase domain should be chang °ed from D2 to Dl with v mod I 2 set to

set to

(603) and v con reset to zero ((a¹)). The above operation repeats m a circular way as v con keeps on decreasing. We can identify the hysterisis characteristic m the above operation, and this prevents the bouncing problem at the boundary points. For example, once the phase domain change has taken place (e.g., from Dl to D2), the phase domain will be staying in D2 in spite of small variation of v con , not getting back to Dl, because the VCPS starts its operation with the reset v con in D2. Without this hysterisis mechanism (i.e., v con not being reset to zero after phase domain change), the phase domain will be bouncing back and force between Dl and D2 for small variation of

. The hysterisis mechanism is one of novelties of the current invention. [103] One problem associated with the above phase domain change is that the phase domain change is not carried out instantly. Because of a finite time in clearing the integrator to reset v and in switching the pseudosinusoidal waveforms, the resultant con phaseshifted version is venerable to switching glitches if not provided with any means. [104] To solve the problem, we put a clutching mechanism between the switch box (415) and the vector modulator (403). The clutching mechanism disconnects the path between the two blocks temporarily while keeping the recent modulation signal values. This allows us to change the phase domain safely. During the period of the disconnection, we can clear the integrator and switch the pseudosinusoidal waveforms without effecting on the modulation signals at the input ports of the vector modulator (denoted v and v ). After phase domain change, the path is recovered. The mod-I mod-Q clutching mechanism is similar to that of the car, so the name. The clutching mechanism is realized by using a sample and hold circuit (denoted S/H) (417) under control of the Freeze signal (449) from the control box. Consequently, the modulation signal generator generates an appropriate modulation signal pair (denoted v (437) mod-I and v (439)) and provides them for the vector modulator. The clutching mod-Q mechanism is another novelty of the current invention.

[105]

[106] Control box:

[107] In implementing the modulation signal generator, several control logics are necessary. They are generated by the control box (219), which is implemented as a digital logic circuit. This is a simple control logic and can be easily combined with analogue circuit in a mixedmode CMOS circuit. The major aim of the control box is to make a smooth change of the phase domain when

reaches either boundary values ( v or -v ) so that the phase shifting can be achieved in a perfectly circular manner. [108] [109] When v reaches v or -v , the control box resets the integrator so that v goes back con 0 0 con to zero and switches the modulation signals so that the next phase domain transfer curve can be effective. A zero crossing detector (denoted ZCD) (413) is provided in order to detect the boundary points in terms of the zero crossing points of either v mod-I- 1

(429) or v (431) and apply corresponding logic signals Sign (denoted Signl (441) mod-Q-l and SignQ (443)) to the control box (see Fig. 4). [HO]

[111] The control box operates as an finite state machine whose state changes according to the input logics like Signl and SignQ from the zero crossing detector while generating appropriate control logics like Clear (221), Freeze (449) and Switch (denoted Switch 1 (445) and Switch2 (447)) signals. The generated control logics are activeHigh in this invention. This means the associated operation is active when the logic is High. Here, the state is defined as the respective phase domain. As before, we explain the operation of the control box taking an example for four phase domains (i.e., L=4). Therefore, we have four states (Sl, S2, S3, S4) which stands for the respective phase domains (Dl, D2, D3, D4). The state transition diagram of the control box corresponding to the operation of the modulation signal generator according to the diagram in Fig. 6 is shown in Fig. 7. In the whole operations, there are two kinds of operations: one is statespecific operations, and another is common operations which happen irrepective of specific states.

[112]

[113] We explain the common operations first (see Fig. 8). There are transfer curves of v

(801) and v (803) in Fig. 8 (A) and (B) from the pseudosinusoidal waveform mod-I-1 mod-Q-1 generator, which is the same as Fig. 5 (A) and (B) in the region of interest (i.e., -v <v

0 con

<v ). Also, there are generation of Signl (805) and SignQ (807) in Fig. 8 (C) and (D) from the zero crossing detector, and generation of Clear logic signal (809) and Freeze logic signal (811) in Fig. 8 (E) and (F) from the control logic, respectively. Note that the waveform (803) of Fig. 8 (B) is different from that (503) of Fig. 5 (B) in the outer region (i.e., v <-v , v >v ). This is to enable a more precise waveform generation con 0 con 0 when implemented in CMOS as will be explained later. [114] When v stays within the boundary values (i.e., -v <v <v ), The Clear and Freeze con 0 con 0 keep Low. As v reaches v , Signl will fall ((a) in Fig. 8 (C)) while SignQ stays High. con 0

These Signl and SignQ are applied to the control box, and the control box recogizes that it is time to make phase domain change in the positive direction. At first, the control box activates Freeze logic signal (in this diagram, Freeze goes High in (F)) so as to disconnect the path between the switch box and the vector modulator and to hold the current modulation signals sampled just before the disconnection. Then, the control box activates Clear logic signal (in this diagram, Clear goes High in (E)) so as to reset the integrator (so v ) to zero. con

[115] As v reaches -v , Signl will fall (Qo) in Fig. 8 (C)) while SignQ stays Low. These con 0

Signl and SignQ are applied to the control box, and the control box recogizes that it is time to make phase domain change in the negative direction. At first, the control box activates Freeze logic signal (in this diagram, Freeze goes High in (F)) so as to disconnect the path between the switch box and the vector modulator and to hold the current modulation signals sampled just before the disconnection. Then, the control box activates Clear logic signal (in this diagram, Clear goes High in (E)) so as to reset the integrator (so v ) to zero. con

[116] The remaining thing is for the control box to move the current phase domain over to the next phase domain by manipulating the Switch logic signals (Switch 1 and Switch2). However, there are statespecific operations, and they will be explained further referring to Fig. 7.

[117] When initialized (e.g., powered on) (701), the control box is set to Sl (703) by activating Freeze and Clear to put v to zero and generating an appropnate Switch con logics so that v is connected to v (= mod i 2 mod i 1 c^os(— O

) and v is connected to v (= mod Q 2 mod Q 1

vo

), respectively, as suggested in Fig. 6 (A).

[118] Explaining the operation m the positive direction first: In Sl (703) in Fig. 7, the control box changes to S2 (705) when v reaches v so that Signl falls (i.e., at the con 0 negative edge) and SignQ stays High. The phase domain change from Dl to D2 is carried out by activating Freeze, and then, Clear to put v to zero and generating an con appropiate Switch logics so that v is connected to -v and v is connected mod I 2 mod Q 1 mod Q 2 to v , respectively, as suggested in Fig. 6 (B). In S2 (705) in Fig. 7, the control box mod I 1 changes to S3 (707) when v reaches v so that Signl falls (i.e., at the negative edge) con 0 and SignQ stays High. The phase domain change from D2 to D3 is carried out by activating Freeze, and then, Clear to put v to zero and generating an appropriate con

Switch logics so that v is connected to -v and v is connected to -v , mod 1 2 mod I 1 mod Q 2 mod Q 1 respectively, as suggested in Fig. 6 (C). In S3 (707) in Fig. 7, the control box changes to S4 (709) when v reaches v so that Signl falls (i.e., at the negative edge) and con 0

SignQ stays High. The phase domain change from D3 to D4 is carried out by activating Freeze, and then, Clear to put v to zero and generating an appropiate con

Switch logics so that v is connected to v and v is connected to -v σ mod I 2 mod Q 1 mod Q 2 mod I 1 respectively, as suggested in Fig. 6 (D). In S4 (709) in Fig. 7, the control box changes to Sl (703) when v reaches v so that Signl falls (i.e., at the negative edge) and con 0

SignQ stays High. The phase domain change from D4 to Dl is carried out by activating Freeze, and then, Clear to put v to zero and generating an appropiate con

Switch logics so that v is connected to v and v is connected to v , mod I 2 mod I 1 mod Q 2 mod Q 1 respectively, as suggested in Fig. 6 (A). [119] Explaining the operation in the negative direction next: In Sl (703) in Fig. 7, the control box changes to S4 (709) when v reaches -v so that Signl falls (i.e., at the con 0 negative edge) and SignQ stays Low. The phase domain change from D 1 to D4 is carried out by activating Freeze, and then, Clear to put v to zero and generating an con appropriate Switch logics so that v is connected to v and v is connected moα-l-z mod-(j- 1 moα-LJ-z to -v , respectively, as suggested in Fig. 6 (D). In S4 (709) in Fig. 7, the control mod- 1-1 box changes to S3 (707) when v reaches -v so that Signl falls (i.e., at the negative con 0 edge) and SignQ stays Low. The phase domain change from D4 to D3 is carried out by activating Freeze, and then, Clear to put v to zero and generating an appropiate con

Switch logics so that v is connected to -v and v is connected to -v , mod-I-2 mod-I-1 mod-Q-2 mod-Q-1 respectively, as suggested in Fig. 6 (C). In S3 (707) in Fig. 7, the control box changes to S2 (705) when v reaches -v so that Signl falls (i.e., at the negative edge) and con 0

SignQ stays Low. The phase domain change from D3 to D2 is carried out by activating Freeze, and then, Clear to put v to zero and generating an appropriate Switch logics con so that v is connected to -v and v is connected to v , respectively, mod-I-2 mod-Q-1 mod-Q-2 mod-I-1 as suggested in Fig. 6 (B). In S2 (705) in Fig. 7, the control box changes to Sl (703) when v reaches -v so that Signl falls (i.e., at the negative edge) and SignQ stays con 0

Low. The phase domain change from D2 to Dl is carried out by activating Freeze, and then, Clear to put v to zero and generating an appropriate Switch logics so that v is connected to v and v is connected to v , respectively, as suggested in moα-l-J moa-Q-z moα-(j-l

Fig. 6 (A). In any state, the current state is maintained without the event for state transition, in this example, the event that Signl falls. [120] After phase domain change has been finished, the integration operation of the integrator resumes by deactivating the Clear logic, and then, deactivating the Freeze logic signal so that the path between the switch box and the vector modulator is recovered, that is, v is connected to v and v is connected to v . Here, mod-I mod-I-2 mod-Q mod-Q-2 the time intervals of activation of Clear and Freeze logic signals should be appropriately chosen. In other words, they should be small enough not to harm continuous phase shifting as well as large enough to make sure safe phase domain change.

[121]

[ 122] Pseudosinusoidal waveform generator:

[123]

[124] One of the novelties of the invented method is provision of a means for generating the modulation signal pair (i.e., v (429) and v (431)) which resembles the

° ^r mod-I-l mod-Q-1 cosine and sine waveforms for a finite control signal range so that associated modulation signal switching and the vector modulation results in unlimited phase shifting capability. It is called the pseudosinusoidal waveform generator (denoted PSEUDOSINUSOID GEN) (407) in this invention, and comprises the pseudocosine waveform generator (denoted PSEUDOCOS GEN) (409) and the pseudosine waveform generator (denoted PSEUDOSIN GEN) (411) as shown in Fig. 4. The waveform generator is implemented with CMOS circuit to exploit its area, power efficiency and high performance. By superimposing several waveform components, which are derived from a basic currentvoltage (IV) curve of the MOS differential amplifier pair, desired pseudosinusoidal waveforms can be synthesized for a desired control signal range.

[125] [126] We consider a MOS differential amplifier pair using NMOS shown in Fig. 9 (A). This is called the basic differential amplifier pair in the invention. It is composed of two MOS's Ml (901), M2 (903) and a current source I (905). The sources of Ml and M2 are tied together, and connected to the I . Given the gate voltage V (907), V

° ' SS ° ° Gl G2

(909) and the drain current I (911), I (913) of Ml and M2, respectively, its transfer curve between the differential current output ΔI(v )=I - 1 and the differential con E D2 voltage input v =V -V is given by con Gl G2

(7) [128] [129] where

is the saturation voltage for the differential amplifier pair, and I is the source bias current, K is the NMOS constant, and

W ^' W

L L n is the widthtolength ratio (or, aspect ratio) of Ml and M2. This is called the basic IV curve in this invention, and the basic IV curve (915) is plotted in Fig. 9 (B). Even though the embodiment is achieved using NMOS, an embodiment using PMOS is equally possible under the same principle. [130] [131] If we look at the waveform (915), we can see that it resembles a portion of the true sine curve (i.e., 90 to 90 degrees interval) for -V <v <V . However, its mathematical

Q con Q form given in (7) is obviously different from the true sine curve. We may employ other devices for better approximation or may derive a better approximation to the true sine curve by manipulating the basic IV curve. One method to achieve a better approximation is shown in Fig. 10 (A). This method employs a plural number of the basic differential amplifier pair in parallel, and adjusts V and I values for each basic differential amplifier pair in order to synthesize a better approximation of the true sine waveform. In Fig. 10 (A), two basic differential amplifier pairs are employed for a typical example. Therefore, it is called the double differential amplifier pair in the invention. The first pair comprises Ml 1 (1001), M21 (1003) and I (1009), and the second pair comprises M12 (1005), M22 (1007) and I (1011) with a constraint I +1

=1 . Also, the gates of the corresponding MOS's (e.g., Mi l and M12, M21 and M22) are tied together, and connected to the differential inputs V and V , and the σ ^r Gl G2 drains of the corresponding MOS's (e.g., Mi l and M12, M21 and M22) are tied together, and connected to the differential outputs I and I , respectively. In Fig. 10 (B), the IV curve for ΔI(v )=I -I as a function of v =V -V is plotted. As a con Dl D2 con Gl G2 ^r result of optimization of the V and I values, the IV curve of the double differential r Q SS amplifier pair (solid) (1013) is more close to the true sine waveform than that of the basic differential amplifier pair (dashed) (1015).

[132]

[133] Note that the above IV curves are symmetrical with respect to the origin. Besides the symmetrical IV curve, we need some offset versions to synthesize the desired pseudos- inusoidal waveforms. The IV curve with input voltage offset can be implemented by adding some voltage shifting means on both input ports to the differential amplifier pair. The differential amplifier pair with the input voltage shifting means is called the extended differential amplifier pair in the invention. An example of the extended differential amplifier pair is shown in Fig. 11 (A). It is composed of a differential amplifier pair (basic in Fig. 9 (A) or double in Fig. 10 (A) or other substitute) (denoted DIFF AMP PAIR) (1101) and additional MOS's M3 (1103), M4 (1105) and current sources I (1107), I (1109). In this embodiment, the M3 and M4 are chosen as

SS3 SS4

PMOS, which is the opposite type to the Ml and M2 in the differential amplifier pair considering a headroom problem related to the lower power supply voltage. Even though the embodiment is achieved using PMOS, an embodiment using NMOS is equally possible under the same principle. [134] [135] The combination of M3 and I (also, M4 and I ) constitutes a source follower. The

SS3 SS4 gatesource voltage drop V (1111) and V (1113) of M3 and M4 can be fixed to

GS3 GS4 have some different values, respectively. Denoting the offset voltage V =IV I-IV I.

' ^{r J} ° ° OFF GS4 GS3 ^' the IV curve of the extended differential amplifier pair has a waveform which is offset in xaxis by V from the symmetrical IV curve of the original differential amplifier pair. This curve (1115) is plotted in Fig. 11 (B).

[136] [137] The offset voltage can be adjusted by varying

^< W ^λ

L '3 and

of the two additional MOS 's. Using the basic equation of MOS

IL SXl

V ' _nGK_Srl> = V, TH W

K,

L >z and

II

V_r SSA

G_iW,_Λ4 I= V T₁H W

K» *, L ^■M and assuming I =1 , the offset voltage is expressed as

[138]

•

[140] [141] Here, V and K are the threshold voltage and the PMOS constant, respectively. To

TH P obtain a voltage offset of a positive integer multiple of a reference voltage

, let [142] [143] W- W-

L > A (N+iy >i

(9)

[144] [145] for some N= 1,2,3,- • •• Then, inserting (9) to (8), we get [146] [147] V = NV . (10)

OFF P [148] [149] In summary, we can obtain a postive voltage offset version ΔI(V -NV ), con P

N= 1,2,3,..., of the basic IV curve ΔI(V ) by implementing a CMOS circuit like Fig. 11 (A) with

' W_ 1 w_ \ L /₄ (N+\γ v L '3 with

. Normally, V is fixed to have the same value as V in (7). A negative voltage offset version ΔI(v +NV ) can be obtained from ΔI(v -NV ) by reversing ΔI(v -NV ) con P con P con P with respect to yaxis to obtain ΔI(-v -NV ) , then reversing ΔI(-v -NV ) with con P con P respect to xaxis to obtain -ΔI(-v -NV ) . Because ΔI(v ) is symmetncal with con P con respect to the origin (i.e., -ΔI(-v )=ΔI(v ) ), we can see that the result of the two con con reversions is equal to ΔI(v +NV ), which is the desired one. The reversions with con P respect to yaxis and xaxis can be easily achieved by just reversing the differential input voltage ports ( V and V ) and the differential ouput current branches ( I_^ and I_^ )

Dl D2 of the extended differential amplifier pair block, respectively.

[150] [151] Now, we describe an embodiment of the functional blocks of the invented pseudo sinusoidal waveform generator using the CMOS circuit technology described above. The pseudo sinusoidal waveform generator generates v (501) and v (503) as mod I 1 mod Q 1 a function of the phase control signal v as indicated in Fig. 5 (A) and (B), re- con spectively. The v and v resemble the true cosine and sine waveforms in -v mod I 1 mod Q 1 0

<v <v , respectively. In order to implement the desired waveforms using circuit con 0 elements, they are redrawn in (1201) in Fig. 12 (A) and (1301) in Fig. 13 (A) with the xaxis and yaxis being scaled so that v =V and I=I R . Here, V and I are defined in

0 P SS L P SS the above, and R is a load resistance.

[152]

[153] Note that the waveform (1301) in Fig. 13 (A) is a bit different from that (503) in Fig. 5 (B). The reason why (1301) is used instead of (503) is to produce the pseudosine waveform as close to the true sine waveform as possible in the range of interest (i.e., -v ≤v <v ) in spite of mismatch between V and V and irregularities of the basic IV

0 con 0 P Q curve of the transistor pair. Actually, the irregularities due to the secondary effect get more severe as the CMOS technology gets deeper into submicron. Of course, the same waveform such as (503) can be used for v in (1301) if such mismatch and irreg- mod-Q-l ularities are negligible. [154] [155] The waveform for v (1201) as a function of v in Fig. 12 (A) can be mod I 1 con synthesized by superimposing several waveforms (1203), (1205), (1207) shown in Fig. 12 (B), (C), (D). Note that the waveforms Fig. 12 (B)(D) are in the dimension of current, and the synthesized waveform Fig. 12 (A) is in the dimension of voltage. This means that the superposition is carried out by flowing the current waveforms through a common resistor R and measuring the voltage across the resistor. Also, differential current notations ΔI ,ΔI ,ΔI in the figures are used since a differential mode CMOS a b c implementation is considered in this embodiment. [156] [157] The ΔI and ΔI in Fig. 12 (B) and (D) can be expressed in terms of the basic IV a c curve ΔI(v ) in (7) as ΔI =ΔI(v +V ) and ΔI =-ΔI(v -V ), respectively. The ΔI con a con P c con P b is realized simply by flowing a current

. Note that these current waveforms can be realized in CMOS circuit by using the technique discussed above. Then, the synthesized waveform for v as a function of

v is obtained as the sum of the above waveforms multiplied by R . That is, con L

[158] [159]

ΪW_/-_I (v_C0B ) = {A/(v_coπ + Vp ) - I_3S - Λ/(v_em - Vp ))- R_L . (11)

[160]

[161] In the same way, the waveform for v (1301) as a function of v in Fig. 13 (A) mod-Q- 1 con can be synthesized by superimposing several waveforms (1303), (1305), (1307) shown in Fig. 13 (B), (C), (D). As mentioned above, the only waveform in Fig. 13 (C) would be enough to generate v if the mismatch and irregularities mentioned above are negligible. [162] [163] The ΔI ,ΔI ,ΔI in Fig. 13 (B), (C), (D) can be expressed in terms of the basic IV curve ΔI(v con ) in (7) as ΔI a =-ΔI(v con +2V P ), ΔI b =ΔI(v con ) and ΔI c =-ΔI(v con- 2V P ) , re- spectively. Note that these current waveforms can be realized in CMOS circuit by using the technique discussed above. Then, the synthesized waveform for v as a function of v is obtained as the sum of the above waveforms multiplied by R . That con L is, [164]

^{C 165]} W_β-i (v_MB ) = {-A/(v_røB + 2V_F ) + AI(v_C0J! ) - Λ/(v_eM - 2V_P ))- R_L

. (12) [166] [167] Based on the previous description, the desired pseudocosine waveform for v mod-i-l

(1201) in Fig. 12 (A) can be generated according to the block diagram in Fig. 14. The extended differential amplifier pair blocks Bl (1401), B2 (1403) (see Fig. 11 (A) for details of each block) are arranged so that whose V values are adjusted to V , V , re-

' ^b OFF ^J P P spectively. Fixing

of the first MOS (M3 in Fig. 11 (A)), the values of

' WΛ

T I

\ L j^ of the second MOS (M4 in Fig. 11 (A)) for each extended differential amplifier pair block are chosen as

4 '3

1 W L n

, respectively, to achieve required V values according to (9) and (10). Here, a constant current source I (1405) is added to Node2 (1421) to provide the necessary waveform element ΔI =-I as shown in Fig. 12 (C). The differential input voltage ports and the differential output current branches are arranged to achieve appropriate polarities in the expression of (11). The differential output current branches are connected to a common resistor pair R (1415) and R (1417) so that the proper superposition can take place. As a result, the desired pseudocosine waveform for v (1411) as a function of v (1409) is generated between Nodel (1419) and Node2 con

(1421). [168] [169] In the same way, the whole block diagram for generating v (1301) is shown in mod Q 1

Fig. 15. The extended differential amplifier pair blocks Bl (1501), B2 (1503), B3 (1505) (see Fig. 11 (A) for details of each block) are arranged so that whose V

OFF values are adjusted to 2V , 0, 2V respectively. Fixing

W "

L '2 of the first MOS (M3 in Fig. 11 (A)), the values of

of the second MOS (M4 in Fig. 11 (A)) for each extended differential amplifier pair block are chosen as

V W_^λ 9 v T

,7 n

W

, respectively, to achieve required V values according to (9) and (10). The differential input voltage ports and the differential output current branches are arranged to achieve appropriate polarities in the expression of (12). The differential output current branches are connected to a common resistor pair R (1511) and R (1513) so that the proper superposition can take place. As a result, the desired pseudosine waveform for v (1509) as a function of v (1507) is generated between Nodel (1515) and mod Q 1 con

Node2 (1517).

[170] [171] Miscellaneous blocks: [172] [173] The sample and hold block (417) can be implemented using MOS switches (Ml (1601), M2 (1603), M3 (1605), M4 (1607)) and capacitors (Cl (1609), C2 (1611), C3 (1613), C4 (1615)) as depicted in Fig. 16. It is provided to avoid glitches in the output signal during phase domain change. When the Freeze signal is the logic Low, the MOS switches are turned on so that the differential input signals v (433) and v mod 1 2 mod Q 2

(435) are transferred to the differential output signals as v (437) and v (439), mod I mod Q respectively. On the contrary, while the Freeze signal (449) is the logic High, the MOS switches are turned off so that the differential output signals keep the recently sampled values in the capacitors in spite of possible glitches in input signals during phase domain change. [174] [175] The IQ splitter (401) can be implemented using MOS (Ml (1713), M2 (1715)) and

RC phase delaying components as depicted in Fig. 17. When R (1703) (1705) and C

(1701) (1707) are tuned so that

R₁C₁ where f is the center frequency of the RF input sinusoid v (419), the RC network c in operates as a 90 degrees phase splitter at f . As a result, when a differential input signal v is applied to gates of M1M2 pair, the voltage difference generated between Nodel and Node2 becomes the inphase RF input signal v (421), and the voltage difference m-I generated between Node3 and Node4 becomes the quadrature RF input signal v m-Q

(423), respectively, with respect to v . To minimize the effect of a parasitic ca- m pacitance, we put buffers (1717) (1719) at the output stage.

[176]

[177] The vector modulator (403) can be implemented using two Gilbert cells (1801)

(1803) and an external combining circuit (1809) as depicted in Fig. 18. A quadrature pair of RF input signal ( v in- 1 (421) and v m-Q (423)) and a quadrature pair of the modulation signal ( v (437) and v (439)) are provided to the vector modulator. mod-I mod- Q

By the operation of each Gilbert cell, the current differences ΔI =1 -I and ΔI ==11 --1

^{J r} 12 1 2 34 3 4 at the output ports of Gilbert cells are expressed as ΔI =A v v and ΔI =A v v r ^{Γ Γ} 12 O m Q mod I 34 O m I with some constant A . The two currents are combined and converted to a voltage mod-Q 0 through the load resistor (1805) (1807) to give a differential output voltage waveform v (425) as out

[178]

^{C 179]} Vf (0 = ^V∞-Q (0 ^{■ V}mod-I

^-I (0 ^{" V}mod-β<Λ™ )

(13)

[180]

[181] As a result, v (t) becomes the phaseshifted version of v (t) (419) as much as out m commanded by v (427) as described in the previous section. con

[182]

[183] Phase shifting of digital signals: [184]

[185] Until now, the explanation of the invention was made with assumption that the input signal is an analogue signal. However, the same idea disclosed in the invention can be applied to the phase shifting of digital signals as well. The vector modulationbased VCPS (denoted VMVCPS) for analogue input signals shown in Fig. 4 was composed of an IQ splitter, a modulation signal generator and a vector modulator. Because of the analogue signal nature, the IQ splitter was realized through RC phase delaying components as shown in Fig. 17. The digital version of the VMVCPS would be composed of an IQ splitter, a modulation signal generator and a vector modulator as well. However, although the modulation signal generator is the same as in the analogue signal case, the IQ splitter and the vector modulator should be modified reflecting the digital signal nature.

[186]

[187] For example, the splitted IQ signal pair ( v , v ) can be obtained by using two m-I m-Q divideby2 digital logic circuits which are triggered by the rising and falling edges of the input signal, respectively. At the same time, the modulation signal generator generates the modulation signal pair ( v , v ). The ( v , v ) and ( v , v mod-I mod-Q in-[ m-Q mod-I mod-Q

) are vector modulated in the vector modulator in a way suitable for digital signals, and generates the desired phaseshifted version of the input signal. The details are omitted, but it should be recognized that the same idea disclosed in the invention can be applied to the phase shifting of digital signals as well.

[188]

[ 189] Another embodiment example:

[190]

[191] Another embodiment example of the invention is shown in Fig. 19. In the same way as the first embodiment example in Fig. 4, this second embodiment example employs a IQ splitter (1901), a vector modulator (1903) and a modulation signal generator (1905). This second embodiment example makes a difference from the first one by employing a pseudosinusoid generator (1907) with phase shift range of 720 degrees (i.e., -φ <φ(v )< φ , φ =360°) whereas the first one assumed a pseudosinusoid generator with con 0 0 phase shift range of 360 degrees or less than 360 degrees. Although the finite VCPS is not existent explicitly in the block diagram, the implicit VCPS which could be derived from the pseudosinusoid with a finite phase shifting characteristic is called the finite VCPS in this invention. In fact, the finite VCPS resulting from the pseudosinusoid of the first embodiment example was assumed to have phase shift range of 180 degrees (i.e., -φ <φ(v )< φ , φ =90° ). The fact that the finite VCPS has phase range of 720

0 con 0 0 degrees brings about a convenience that the switch box (415) and associated Switch 1 (445), Switch2 (447) signals in Fig. 4 are no longer needed. This is because we can cover the whole phase range with single phase domain Dl ( -360° to 360°), and the same pseudosinusoid can be used as the next phase domain signal as it is when the phase domain change takes place. [192]

[193] The necessary pseudosinusoids (i.e. modulation signals) according to the second embodiment example is shown in Fig. 20 (A) and (B). The modulation signals v mod-I

(2001) and v (2003) in Fig. 20 (A) and (B) resemble the true sine and cosine curve mod-Q in the region -v <v <v . The resultant transfer curve (2005) of the finite VCPS is

0 con 0 shown in Fig. 20 (C). As v varies from -v to v , φ(v ) varies from -360° to 360° . con 0 0 con

Therefore, the finite VCPS is called 720 degrees VCPS. Note that if v is reset to 0 con when v reaches either boundary values ( v or -v ), the modulation signals can con ^J 0 0 continue their sinusoidal waveforms without need of waveform switching. This makes a contract to the first embodiment example which needed waveform switching through the switch box (415) in Fig. 4.

[194]

[195] The control block (denoted CONTROL) (305) in Fig. 3 operates as a digital logic circuit to control the operation of the circular VCPS. It takes Sign (319) (i.e., Signl (1941) and SignQ (1943)) from the zero crossing detector (1913) as logic inputs, and generates Clear (321) and Freeze (315), and applies them to the integrator (307) and the VMVCPS (303), respectively. The major aim of the control block is to make a smooth switching of the phase domain when v reaches either boundary values (v or -v ) so that the phase shifting can be achieved in a perfectly circular manner.

[196]

[197] When v reaches v or -v , let v , the control block resets the integrator so that v con 0 0 0 con goes back to zero and the next phase domain transfer curve can be effective. For this purpose, a zero crossing detector is provided which detects the zero crossing points of either v or v and applies corresponding logic states, Signl and SignQ, to the mod-I mod-Q control block. The control block decides an appropriate firing instant based on the logic states. [198] [199] The firing instant should occur when v reaches v so that v (2103) crosses a con 0 mod-Q zero point from negative to positive values (so, SignQ (2107) goes from Low to High) while v (2101) remains positive (so, Signl (2105) remains High) (see (e) in Fig. 21 mod-I

(B)), or when v reaches -v so that v crosses the zero point from positive to con 0 mod-Q negative values while v remains positive (see (a) in Fig. 21 (B)). However, the mod-I problem is that this happens not only when v reaches v or -v , but also when v con 0 0 con reaches 0 (see (c) in Fig. 21 (B)). This is inevitable as far as 720 degrees VCPS is employed. Therefore, we need a means to make sure that a proper firing can occur only when v reaches v or -v . con 0 0

[200]

[201] For that purpose, we divide v con range into three regions: Retarding (-v 0 <v con <-v 0 /2 so -360°<φ<-180°), Normal ( -v /2<v <v /2 so -180°<φ<180° ) and Advancing ( v

0 con 0 0

<v <v so 180°<φ<360° ) regions. Defining the two logic variables representing a con 0 particular state at certain moment, we can implement a finite state machine which takes Signl and SignQ as input, and generates Clear and Freeze as output together with an appropriate state transition. Their waveforms as a function of v are shown in Fig. 21 con

(C)(H). Its state transition diagram is shown in Fig. 22. [202] [203] On the power on (2201), the state goes to Normal. In Normal state (2203), if Signl is

Low and a positive edge of SignQ takes place, where v starts to be less than -v /2 con 0

(see (b) in Fig. 21 (B)), the state changes to Retarding. If Signl is Low and a negative edge of SignQ happens, where v starts to be greater than v /2 (see (d) in Fig. 21 (B)), con 0 the state changes to Advancing. Otherwise, it keeps the previous state. [204] [205] In Advancing state (2205), the state changes to Normal at the positive edge of SignQ while Signl remains High where v starts to be greater than v (see (e) in Fig. 21 (B)). con 0

At the same time, the finite state machine activates Freeze and Clear successively so that the phase domain switching can be achieved smoothly. Also, the state changes to Normal at the positive edge of SignQ while Signl remains Low where v starts to be con less than v /2 (see (d) in Fig. 21 (B)). No output is generated from the control block in this case. Otherwise, it keeps the previous state. [206] [207] In Retarding state (2207), the state changes to Normal at the negative edge of SignQ while Signl remains High where v starts to be less than -v (see (a) in Fig. 21 (B)). con 0

At the same time, the finite state machine activates Freeze and Clear successively so that the phase domain switching can be achieved smoothly. Also, the state changes to Normal at the negative edge of SignQ while Signl remains Low where v starts to be con greater than -v /2 (see (b) in Fig. 21 (B)). No output is generated from the control block in this case. Otherwise, it keeps the previous state.

[208]

[209] By the way, to avoid possible glitches which may occur during phase domain switching process, a clutching means is introduced between the modulation signal generator (1905) and the vector modulator (1903) (see Fig. 19). The sample and hold (denoted S/H) (1917) plays the role of the clutch. The sample and hold samples and holds the v mod-I-1 (1929) and v mod-Q-1 (1931) inputs to generate the freezed v mod-I (1937) and v (1939) outputs while the Freeze (1949) is active (i.e., High). Otherwise, Vmod- mod-Q and v are passed to the vector modulator as they are.

I-l mod-Q-1 ^{r J}

[210]

[211] When v reaches v or -v , the phase domain switching happens. At the time, the con 0 0 control block activates Clear and Freeze signals as indicated in Fig. 21 (E) and (F), respectively, and applies the Freeze signal to the sample and hold block. As a result, the v and v inputs to the vector modulator, which are the values of v and v mod- mod-I mod-Q mod-I-1 samples just before the freezing, are prevented from being disturbed in spite of possible glitches during the activated period of Clear. [212] [213] In the similar way to the first embodiment example in Fig. 12 and 13, the pseu- dosinusoids can be generated by manipulating the basic IV curve of the differential

MOS amplifier pair as shown in Fig. 23 and Fig. 24. [214] [215] Denoting ΔI in Fig. 24 (D) as a basic IV curve ΔI(v ) , other IV curves are expressed as ΔI =ΔI(v +4V ) (see Fig. 24 (B)), ΔI =-ΔI(v +2V ) (see Fig. 24 (C)), a con P b con P

ΔI =-ΔI(v -2V ) (see Fig. 24 (E)) and ΔI =ΔI(v -AN ) (see Fig. 24 (F)), re- d con P e con P spectively. Then, the waveform for v in Fig. 24 (A) as a function of v can mod-Q- 1 con synthesized as the sum of the above waveforms multiplied by R . That is,

[216] [217] WiH (v_M ) = {A7(v_M + 4V_P ) - Δ/(v_M + 2F_P ) + ΛJ(v_M )

" A/(v_M - 2V_P) + Λ/(v_M - W_P)} - R₁ (14)

[218]

[219] In the same way, the waveform for v in Fig. 23 (A) as a function of v can be mod-I- 1 con synthesized as [220]

^C221] W j-i (v_M ) = {Λ7(v_M + 5V_P ) - Λ/(v_M + W_P ) + Λ/(v_røn + V_P ) - I₃₈

~ A/(v_M - V_P ) + M(v_con - W_P ) - M(y_Cϋ7i - 5V_P)} - R_L.

(15) [222] [223] Based on the previous description, the whole block diagram for generating v in mod-Q- 1

Fig. 24 (A) is shown in Fig. 26. The extended differential amplifier pair blocks Bl (2601), B2 (2603), B3 (2605), B4 (2607), B5 (2609) (see Fig. 11 (A) for details of each block) are arranged so that whose V values are adjusted to 4V ,2V ,0,2V ,4V , σ OFF ^J P P P P respectively. Fixing

> i of the first (reference) MOS (M3 in Fig. 11 (A)), the values of ^f W_ L of the second MOS (M4 in Fig. 11 (A)) for each extended differential amplifier pair block are chosen as

3

, respectively, to achieve required V values according to (9) and (10). The differential input voltage ports and the differential output current branches are arranged to achieve appropriate polarities in the expression of (14). The differential output current branches are connected to a common resistor pair R (2611) and R (2613) so that the proper superposition can take place. As a result, the desired pseudosine waveform Vmod- (2621) as a function of v (2619) is generated between Node 1 (2615) and Node 2

Q-I con

(2617).

[224] [225] In the same way, the desired waveform for V in Fig. 23 (A) is generated mod-I-l according to the block diagram in Fig. 25. The differential amplifier blocks Bl (2501), B2 (2503), B3 (2505), B4 (2507), B5 (2509), B6 (2511) (see Fig. 11 (A) for details of each block) are arranged so that whose V values are adjusted to 5V ,3V ,V ,V ,3V

OFF P P P P P

,5V , respectively. Fixing

^''W^*'1'

X₃ of the first (reference) MOS (M3 in Fig. 11 (A)), the values of

W L of the second MOS (M4 in Fig. 11 (A)) for each differential amplifier block are chosen as

1 (W^"\ 1 (W^"\ \ ( W ^"λ 1 ⁽ W W 1 W

36 { L J₃ 16 \ L h 4 \ L Ji L J i 16 ^ L j_z 36 L Ji

, respectively, to achieve required V values according to (9) and (10). Here, a constant current source I (2513) is added to Node 2 (2523) to provide the necessary waveform element ΔI =-I as shown in Fig. 23 (E). The differential input voltage d SS ports and the differential output current branches are arranged to achieve appropriate polarities in the expression of (15). The differential output current branches are connected to a common resistor pair R (2517) and R (2519) so that the proper superposition can take place. As a result, the desired pseudocosine waveform v mod-I-l

(2527) as a function of v (2525) is generated between Node 1 (2521) and Node 2 con

(2523). [226]

[227] Simulation results:

[228]

[229] To check the phase shifting performance, we applied a RF sinusoidal signal v (309) m and a constant phase control error signal v (323) with a positive value to the invented err

VCFS as shown in Fig. 3. This means phase control signal v (313) should be linearly con increasing with respect to the time (i.e., v (t)=K -t (K >0)) due to the operation of the con 1 1 integrator (307). Because the phase control signal increases linearly with respect to the time, the phase shifting should be taking place in proportion to the time elapsed as well. The simulated waveforms for v (437) and v (439) (not v and v ) niod-I mod-Q mod-I-1 mod-Q-1 as a function of time ( μsec) are shown in Fig. 27 (A) in a solid line and a dashed line, respectively. We can see that the desired pseudosinusoidal waveforms are generated as the time elapses so as to achieve the necessary phase shifting. When either v or v mod-I crosses zero, the phase domain change takes place with clearing the integrator mod-Q output. This process repeats and the whole phase domains from Dl to D4 are covered.

The ovals in Fig. 27 (A) indicate the phase domain change period. [230] [231] The phase shifting and amplitude of the output signal v (311), which are out determined by

and

4 ^Vτaπd-I + ^Vmod-£

, are plotted in Fig. 27 (B) and (C), respectively. From the plot, we can see that the unlimited phase shifting is achieved in a circular way (except during the phase domain change period), and the phase shifting is almost linear in the normal intervals. The maximum phase deviation from the linear slope due to the nonideality of the pseu- dosinusoids is measured to be 3.5 degrees. At the same time, the maximum amplitude deviation ratio from the constant envelope is measured to be 2.2 percent. These values are regarded as small enough to demonstrate effectiveness of the invented circular VCPS.

[232] Although a few exemplary embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these exemplary embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the appended claims and their equivalents.

Claims

Claims

[1] A voltage-controlled phase shifter (VCPS) with an input sinusoid, an output sinusoid and a phase control signal input, the voltage controlled phase shifter comprising : a vector modulation-based VCPS configured to generate a continuously phaseshifted version of an input sinusoid in accordance to a phase control signal; a control block configured to receive necessary information signals including a

Sign signal and to generate necessary control signals including a Switch signal, a

Clear signal and a Freeze signal; and a reset block configured to pass said phase control signal to said vector modula- tionbased VCPS in normal operation and to reset its output to zero in accordance to said clear signal from said control block.

[2] A voltage-controlled frequency shifter (VCFS) with an input sinusoid, an output sinusoid and a frequency control signal input, the voltage controlled frequency shifter comprising: a VCPS in accordance to Claim 1 wherein said reset block in said VCPS is replaced by said integrator outside said VCPS; a integrator is configured to store phase information and to dump its output to zero when a clear signal is activated from said control block in Claim 1 as well as to integrate said frequency control signal.

[3] The voltage-controlled phase shifter (VCPS) in accordance to Claim 1 further comprising: a IQ splitter configured to split the phase of said input sinusoid into a quadrature sinusoid pair of said input sinusoid; a modulation signal generator configured to generate a pseudo-sinusoidal modulation signal pair in an analogue circuit as a function of said phase control signal input; and a vector modulator configured to modulate said a quadrature sinusoid pair of said input sinusoid by said a pseudo-sinusoidal modulation signal pair in order to generate a phaseshifted version of said input sinusoid.

[4] The voltage controlled phase shifter (VCPS) in accordance to Claim 3 further comprising: a pseudo-sinusoidal waveform generation means configured to generate the first intermediate pseudo-sinusoidal modulation signal pair as a function of said phase control signal input with a finite range; a switching means configured to switch said first intermediate pseudo-sinusoidal modulation signal pair to generate the second pseudo-sinusoidal modulation signal pair so that said second pseudo-sinusoidal modulation signal pair suits the required phase domain; a clutching means configured to pass said second pseudo-sinusoidal modulation signal pair in normal operation and to provide a temporary modulation signal pair during the phase domain change period in order to achieve a seamless phase shifting; and a threshold detection means configured to detect a threshold point at which phase domain change must take place, and to generate a logic level to said control block;

[5] The voltage controlled phase shifter (VCPS) in accordance to Claim 4, wherein the clutching means realized as a sample and hold block configured to pass said modulation signal pair while operating within a phase domain, and to sample and hold said modulation signal pair in a phase domain change period according to a Freeze signal activated from said control block in Claim 1 , in order to achieve smooth phase domain changeover.

[6] The voltage controlled phase shifter (VCPS) in accordance to Claim 4, wherein the threshold detection means realized as a zero crossing detector configured to detect a zero crossing point of either of said modulation signal pair and to generate a Sign signal, and apply it to said control block in Claim 1.

[7] The voltage controlled phase shifter (VCPS) in accordance to Claim 1, wherein the control block comprising a finite state machine configured to receive phase domain change information like a Sign signal from said threshold detection means in Claim 4, and to change its state in an appropriate way, and to generate necessary control signals like a Switch signal, a Clear signal, and a Freeze signal, and to apply them to said switching means in said Claim 4, to said reset block in Claim 1 , and said clutching means in Claim 4, respectively.

[8] A modulation signal generator configured to generate a pseudo-sinusoidal waveform pair as a function of a phase control control signal in such a way that: first, the first intermediate pseudo-sinusoidal modulation signal waveforms are generated as a function of said phase control signal within a finite range between an lower and upper boundary points. second, as soon as said phase control signal crosses over either said lower or uppper boundary point, said first intermediate pseudo-sinusoidal modulation signal waveforms are switched to the second intermediate pseudo-sinusoidal modulation signal waveforms, and said phase control signal is reset to zero (phase domain change) so that the second intermediate pseudo-sinusoidal modulation signal waveforms are continuously connected to the previous second intermediate pseudo-sinusoidal modulation signal waveforms as the phase control signal varies. third, said second intermediate pseudo-sinusoidal modulation signal waveforms are passed to the final pseudo-sinusoidal waveform pair when said phase control signal is within said lower and upper boundary points, and sampled and holded while said first intermediate pseudo-sinusoidal modulation signal waveforms are in the process of switching.

[9] A modulation signal generator in accordance to Claim 8 configured to have a fintie number of phase domains which overlap with neighbouring phase domains, and said phase domain change is configured so that the phase shifting has a hysterisis characteristic as a function of said phase control signal.

[10] A modulation signal generator comprising: a pseudo-sinusoidal waveform generator configured to generate the first intermediate pseudo- sinusoidal modulation signal pair as a function of said phase control signal input within a finite range; a switch box configured to switch said first intermediate pseudo-sinusoidal modulation signal pair to generate the second pseudo-sinusoidal modulation signal pair so that said second pseudo-sinusoidal modulation signal pair suits the required phase domain, according to a Switch signal activated from a control block; a sample and hold block configured to pass said second pseudo-sinusoidal modulation signal pair while operating within a phase domain, and to sample and hold said second pseudo-sinusoidal modulation signal pair in a phase domain change period, and to generate a final pseudo-sinusoidal modulation signal pair, according to a Freeze signal activated from a control block; a zero crossing detector configured to detect a zero crossing point of either of said first pseudo-sinusoidal modulation signal pair and to generate a logic signal Sign, and apply it to a control block; and a control block comprising a finite state machine configured to receive phase domain change information like a Sign signal from said zero crossing detector and to change its state in an appropriate way, and to generate necessary control signals like a Switch signal, a Clear signal, and a Freeze signal, and to apply them to said switch box, to an outer reset block, and said sample and hold block, respectively.

[11] The modulation signal generator in accordance to Claim 10 configured without said switch box provided that said second intermediate pseudo-sinusoidal modulation signal pair is identical to said first intermediate pseudo-sinusoidal modulation signal pair.

[12] The modulation signal generator in accordance to Claim 10, wherein the pseudo- sinusoidal waveform generator comprises inphase modulation signal generator and quadraturephase modulation signal generator is configured to generate a pseudo-cosine and pseudo-sine modulation signal pair as a function of said phase control signal input for a finite input range.

[13] The modulation signal generator in accordance to Claim 12, wherein the pseudo- sine waveform (odd function) is synthesized by superimposing multiple copies of a basic waveform, where said basic waveform takes the form of pseudo-sine curve in a finite input range, and said copy may be a shifted version in x-axis and/or reversed version in y-axis and/or x-axis of said basic waveform.

[14] The modulation signal generator in accordance to Claim 12, wherein the pseudo- cosine waveform (even function) is synthesized by superimposing multiple copies of a basic waveform and some constant value, where said basic waveform takes the form of quasisine curve in a finite input range, and said copy may be a shifted version in x-axis and/or reversed version in y-axis and/or x-axis of said basic waveform.

[15] The modulation signal generator in Claim 13 and Claim 14, wherein the basic waveform is obtained from the I-V curve (output current vs. input voltage transfer curve) of a transistor pair (e.g., MOS or BJT or any similar devices) in order to achieve an approximation to the true sine waveform, and said copy in Claim 13 and Claim 14 is obtained by shifting input voltage level and/or reversing input voltage ports and/or output current branches of said transistor or transistor pair.

[16] The modulation signal generator in Claim 13 and Claim 14, wherein the basic waveform is obtained from the I-V curve (output current vs. input voltage transfer curve) of a plural number of said transistor pairs in Claim 16 in parallel in order to achieve a better approximation to the true sine waveform.

[17] The modulation signal generator in Claim 13 and Claim 14, wherein basic waveform is obtained from the I-V curve (output current vs. input voltage transfer curve) of a plural number of said transistor pairs in Claim 15 in parallel in order to achieve an approximation to any required waveform.

[18] The modulation signal generator in Claim 15, wherein the shifting input voltage level of said transistor or transistor pair is achieved by an appropriate adjustment of W/L (width to length ratio) and a bias current of said MOS according to a way exploiting the dependency of the gate-source voltage of the MOS on the inverse- root of W/L and the dependency on the root of the bias current as described in the body or any other similar way for other devices.

[19] The modulation signal generator in accordance to Claim 3, further comprising: a pseudo-sinusoidal waveform generation means configured to generate the first intermediate pseudo-sinusoidal modulation signal pair for a finite input range which spans two periods of the sine waveform as a function of said phase control signal input; a clutching means configured to pass said first pseudo-sinusoidal modulation signal pair in normal operation and to provide a temporary modulation signal pair during the phase domain change period in order to achieve a seamless phase shifting; and a threshold detection means configured to detect a threshold point at which phase domain change must take place, and to generate a logic level to said control block.

[20] The modulation signal generator in accordance to Claim 19, wherein the pseudo- sinusoidal waveform generation means is configured to generate; A pseudo-sinusoidal waveform pair for 720 degrees range according to a phase control signal input; and said control block in accordance to Claim 1 is configured to make phase domain change only when said control signal input reaches either limit values whose phase shifts correspond to 360 degrees and -360 degrees, respectively.