WO2007130000A3 - Method of increasing reliability of packaged semiconductor integrated circuit dice - Google Patents

Method of increasing reliability of packaged semiconductor integrated circuit dice Download PDF

Info

Publication number
WO2007130000A3
WO2007130000A3 PCT/US2005/028047 US2005028047W WO2007130000A3 WO 2007130000 A3 WO2007130000 A3 WO 2007130000A3 US 2005028047 W US2005028047 W US 2005028047W WO 2007130000 A3 WO2007130000 A3 WO 2007130000A3
Authority
WO
WIPO (PCT)
Prior art keywords
dice
die
character map
weighted character
cluster
Prior art date
Application number
PCT/US2005/028047
Other languages
French (fr)
Other versions
WO2007130000A2 (en
Inventor
Paul I Suciu
Kristopher R Marcus
Charles B Friedberg
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of WO2007130000A2 publication Critical patent/WO2007130000A2/en
Publication of WO2007130000A3 publication Critical patent/WO2007130000A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

Semiconductor dice are electrically tested prior to final assembly. Dice failing the test are identified and not packaged. However, “good dice” (i.e., those dice that passed testing) in proximity to the failed dice frequently fail prematurely in the field. Therefore, in one embodiment, a method (300) to identify those dice having a probability for early failure includes identifying a core die and a die cluster, adding (307) the core die and at least one additional die from the die cluster to a weighted character map, and assigning (309) a weighting value to each of the dice added to the weighted character map. At least one tier of buffer dice is then added to the weighted character map adjacent to each die on the weighted character map. Both the dice from the die cluster and the tier of buffer dice are marked, thereby preventing those dice from being packaged and consequently, shipped to customers.
PCT/US2005/028047 2004-09-14 2005-08-08 Method of increasing reliability of packaged semiconductor integrated circuit dice WO2007130000A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/940,128 2004-09-14
US10/940,128 US7105364B2 (en) 2004-09-14 2004-09-14 Method of increasing reliability of packaged semiconductor integrated circuit dice

Publications (2)

Publication Number Publication Date
WO2007130000A2 WO2007130000A2 (en) 2007-11-15
WO2007130000A3 true WO2007130000A3 (en) 2008-11-06

Family

ID=35942201

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/028047 WO2007130000A2 (en) 2004-09-14 2005-08-08 Method of increasing reliability of packaged semiconductor integrated circuit dice

Country Status (3)

Country Link
US (3) US7105364B2 (en)
TW (1) TWI368288B (en)
WO (1) WO2007130000A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3940694B2 (en) * 2003-04-18 2007-07-04 株式会社東芝 Semiconductor device and manufacturing method thereof
US7105364B2 (en) * 2004-09-14 2006-09-12 Atmel Corporation Method of increasing reliability of packaged semiconductor integrated circuit dice
JP4931710B2 (en) * 2007-06-29 2012-05-16 株式会社リコー Non-defective chip classification method on wafer, chip quality determination method using the same, chip classification program, chip quality determination program, marking mechanism, and semiconductor device manufacturing method
JP4820389B2 (en) * 2008-07-22 2011-11-24 株式会社リコー Chip quality judgment method, chip quality judgment program, and marking mechanism using the same
EP2246708A1 (en) * 2009-04-30 2010-11-03 Micronas GmbH Method for producing a defect map of individual components, in particular semiconductor components, on a carrier, in particular a semiconductor wafer
US10114071B2 (en) 2016-04-26 2018-10-30 International Business Machines Corporation Testing mechanism for a proximity fail probability of defects across integrated chips
US10902576B2 (en) * 2016-08-12 2021-01-26 Texas Instruments Incorporated System and method for electronic die inking after automatic visual defect inspection
CN108122801B (en) * 2017-12-12 2021-07-09 武汉新芯集成电路制造有限公司 Wafer marking method and wafer marking system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5991699A (en) * 1995-05-04 1999-11-23 Kla Instruments Corporation Detecting groups of defects in semiconductor feature space
US6714885B1 (en) * 1998-07-20 2004-03-30 Isemicon, Inc. Method for measuring number of yield loss chips and number of poor chips by type due to defect of semiconductor chips

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5539752A (en) 1995-06-30 1996-07-23 Advanced Micro Devices, Inc. Method and system for automated analysis of semiconductor defect data
US5777901A (en) 1995-09-29 1998-07-07 Advanced Micro Devices, Inc. Method and system for automated die yield prediction in semiconductor manufacturing
US20020156550A1 (en) * 2001-02-28 2002-10-24 Langford Rick Edward Robust windowing method using the poisson yield model for determining the systematic and random yield of failing circuits on semiconductor wafers
US20020121915A1 (en) 2001-03-05 2002-09-05 Agere Systems Guardian Corp. Automated pattern clustering detection for wafer probe maps
JP4038356B2 (en) * 2001-04-10 2008-01-23 株式会社日立製作所 Defect data analysis method and apparatus, and review system
US6965895B2 (en) 2001-07-16 2005-11-15 Applied Materials, Inc. Method and apparatus for analyzing manufacturing data
US7105364B2 (en) 2004-09-14 2006-09-12 Atmel Corporation Method of increasing reliability of packaged semiconductor integrated circuit dice

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5991699A (en) * 1995-05-04 1999-11-23 Kla Instruments Corporation Detecting groups of defects in semiconductor feature space
US6714885B1 (en) * 1998-07-20 2004-03-30 Isemicon, Inc. Method for measuring number of yield loss chips and number of poor chips by type due to defect of semiconductor chips

Also Published As

Publication number Publication date
US20060226862A1 (en) 2006-10-12
US7452733B2 (en) 2008-11-18
US20060043998A1 (en) 2006-03-02
TWI368288B (en) 2012-07-11
WO2007130000A2 (en) 2007-11-15
US7767473B2 (en) 2010-08-03
US20090166898A1 (en) 2009-07-02
TW200618154A (en) 2006-06-01
US7105364B2 (en) 2006-09-12

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