WO2007089546A3 - Adjusting a processor operating parameter based on a performance criterion - Google Patents

Adjusting a processor operating parameter based on a performance criterion Download PDF

Info

Publication number
WO2007089546A3
WO2007089546A3 PCT/US2007/002090 US2007002090W WO2007089546A3 WO 2007089546 A3 WO2007089546 A3 WO 2007089546A3 US 2007002090 W US2007002090 W US 2007002090W WO 2007089546 A3 WO2007089546 A3 WO 2007089546A3
Authority
WO
WIPO (PCT)
Prior art keywords
operating parameter
adjusting
performance criterion
parameter based
controller
Prior art date
Application number
PCT/US2007/002090
Other languages
French (fr)
Other versions
WO2007089546A2 (en
Inventor
Bran Ferren
W Daniel Hillis
William Henry Mangione-Smith
Nathan P Myhrvold
Clarence T Tegreene
Lowell L Wood
Original Assignee
Searete Llc
Bran Ferren
W Daniel Hillis
William Henry Mangione-Smith
Nathan P Myhrvold
Clarence T Tegreene
Lowell L Wood
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/343,927 external-priority patent/US8214191B2/en
Priority claimed from US11/343,745 external-priority patent/US8209524B2/en
Priority claimed from US11/364,130 external-priority patent/US7493516B2/en
Application filed by Searete Llc, Bran Ferren, W Daniel Hillis, William Henry Mangione-Smith, Nathan P Myhrvold, Clarence T Tegreene, Lowell L Wood filed Critical Searete Llc
Publication of WO2007089546A2 publication Critical patent/WO2007089546A2/en
Publication of WO2007089546A3 publication Critical patent/WO2007089546A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
    • G06F11/1407—Checkpointing the instruction stream
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/348—Circuit details, i.e. tracer hardware

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Retry When Errors Occur (AREA)
  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)
  • Testing And Monitoring For Control Systems (AREA)

Abstract

Embodiments include a controller apparatus, a computerized apparatus, a device, an apparatus, and a method. A controller-apparatus includes a monitoring circuit for detecting a computational error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable operating parameter. The controller apparatus also includes a recovery circuit for rolling back an execution of the sequence of instructions to a checkpoint in response to the detected computational error. The controller apparatus further includes a control circuit for adjusting the adjustable operating parameter in response to a performance criterion.
PCT/US2007/002090 2006-01-31 2007-01-23 Adjusting a processor operating parameter based on a performance criterion WO2007089546A2 (en)

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US11/343,927 US8214191B2 (en) 2005-08-29 2006-01-31 Cross-architecture execution optimization
US11/343,745 2006-01-31
US11/343,927 2006-01-31
US11/343,745 US8209524B2 (en) 2005-08-29 2006-01-31 Cross-architecture optimization
US11/364,130 US7493516B2 (en) 2005-08-29 2006-02-28 Hardware-error tolerant computing
US11/364,573 US7607042B2 (en) 2005-08-29 2006-02-28 Adjusting a processor operating parameter based on a performance criterion
US11/364,573 2006-02-28
US11/364,131 2006-02-28
US11/364,131 US8375247B2 (en) 2005-08-29 2006-02-28 Handling processor computational errors
US11/364,130 2006-02-28

Publications (2)

Publication Number Publication Date
WO2007089546A2 WO2007089546A2 (en) 2007-08-09
WO2007089546A3 true WO2007089546A3 (en) 2008-10-16

Family

ID=38327877

Family Applications (3)

Application Number Title Priority Date Filing Date
PCT/US2007/002090 WO2007089546A2 (en) 2006-01-31 2007-01-23 Adjusting a processor operating parameter based on a performance criterion
PCT/US2007/002089 WO2007089545A2 (en) 2006-01-31 2007-01-23 Handling processor computational errors
PCT/US2007/001904 WO2007089498A2 (en) 2006-01-31 2007-01-24 Hardware-error tolerant computing

Family Applications After (2)

Application Number Title Priority Date Filing Date
PCT/US2007/002089 WO2007089545A2 (en) 2006-01-31 2007-01-23 Handling processor computational errors
PCT/US2007/001904 WO2007089498A2 (en) 2006-01-31 2007-01-24 Hardware-error tolerant computing

Country Status (1)

Country Link
WO (3) WO2007089546A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040174944A1 (en) * 1999-09-27 2004-09-09 The Board Of Governors For Higher Education, State Of Rhode Island And Providence Plantatins System and method of digital system performance enhancement
US20050005203A1 (en) * 2003-01-28 2005-01-06 Czajkowski David R. SEU and SEFI fault tolerant computer
US20050132238A1 (en) * 2003-12-16 2005-06-16 Murthi Nanja Performance monitoring based dynamic voltage and frequency scaling
US20060020838A1 (en) * 2004-06-30 2006-01-26 Tschanz James W Method, apparatus and system of adjusting one or more performance-related parameters of a processor

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3663393B2 (en) * 2001-06-27 2005-06-22 インターナショナル・ビジネス・マシーンズ・コーポレーション Method, processor unit and computer system for checkpointing a multi-processor data processing system
US20050138478A1 (en) * 2003-11-14 2005-06-23 Safford Kevin D. Error detection method and system for processors that employ alternating threads
US7415644B2 (en) * 2004-10-22 2008-08-19 International Business Machines Corporation Self-repairing of microprocessor array structures

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040174944A1 (en) * 1999-09-27 2004-09-09 The Board Of Governors For Higher Education, State Of Rhode Island And Providence Plantatins System and method of digital system performance enhancement
US20050005203A1 (en) * 2003-01-28 2005-01-06 Czajkowski David R. SEU and SEFI fault tolerant computer
US20050132238A1 (en) * 2003-12-16 2005-06-16 Murthi Nanja Performance monitoring based dynamic voltage and frequency scaling
US20060020838A1 (en) * 2004-06-30 2006-01-26 Tschanz James W Method, apparatus and system of adjusting one or more performance-related parameters of a processor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MITRA ET AL.: "Robust System Design from Unreliable Components", PENN STATE UNIVERSITY, 2005, pages 194, 235, Retrieved from the Internet <URL:http://www.cse.psu.edu/~yuanxie/ISCA-tutorial.html> *

Also Published As

Publication number Publication date
WO2007089546A2 (en) 2007-08-09
WO2007089498A3 (en) 2008-05-08
WO2007089545A3 (en) 2008-09-25
WO2007089498A2 (en) 2007-08-09
WO2007089545A2 (en) 2007-08-09

Similar Documents

Publication Publication Date Title
WO2012127292A8 (en) Open/close actuating mechanism control device and open/close actuating mechanism control method for vehicle
WO2007014107A3 (en) System and method of monitoring the operation of a medical device
EP2073098A3 (en) Device, system, and method of power saving using location sensing modules
WO2011011711A3 (en) Method and apparatus for detection and control of dc arc faults
WO2012027599A3 (en) Touch sensing apparatus and method
WO2008110895A3 (en) Apparatus, method and system for gesture detection
WO2008073296A3 (en) Method of performing an agricultural work operation using real time prescription adjustment
WO2007109320A3 (en) Application of abnormal event detection (aed) technology to polymers process
WO2009120794A3 (en) Method and apparatus for resetting a silicon controlled rectifier bridge
WO2007089660A3 (en) Multi-voltage synchronous systems
WO2008068486A3 (en) Dispensing device for air treatment agents
EP2241964A3 (en) Information processing apparatus, information processing method, and information processing program
WO2007072028A3 (en) Air traffic control
TW200727101A (en) Apparatus for automatically adjusting display parameters relying on visual performance and method for the same
EP1672584A3 (en) Human tracking apparatus and method, storage medium storing program executing the method, and mobile electronic system including the apparatus
WO2010120403A3 (en) System, method and apparatus for control of a prosthetic device
WO2009006980A3 (en) Appliance and method for predicting a loss of control over a muscle
EP2474348A3 (en) Carbon dioxide separating and recovering system and method of controlling the same
WO2009041233A1 (en) Mold clamping device and method of controlling mold clamping
WO2011087557A3 (en) System and method for limiting operator control of an implement
ATE484780T1 (en) SENSOR WITH TIMER FOR OUTPUTING AN OBJECT DETECTION TIME
WO2008008424A8 (en) Method and apparatus for formation testing
WO2009013318A3 (en) Test arrangement comprising a test model that has at least one control element, and an associated method
WO2007134857A3 (en) Method and device for the error recovery of a data processing unit
WO2012042412A3 (en) Device and method for automatically detecting installed lamp type

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07762703

Country of ref document: EP

Kind code of ref document: A2