WO2007078913A3 - Cross-architecture execution optimization - Google Patents

Cross-architecture execution optimization Download PDF

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Publication number
WO2007078913A3
WO2007078913A3 PCT/US2006/048213 US2006048213W WO2007078913A3 WO 2007078913 A3 WO2007078913 A3 WO 2007078913A3 US 2006048213 W US2006048213 W US 2006048213W WO 2007078913 A3 WO2007078913 A3 WO 2007078913A3
Authority
WO
WIPO (PCT)
Prior art keywords
cross
architecture
execution optimization
execution
architecture execution
Prior art date
Application number
PCT/US2006/048213
Other languages
French (fr)
Other versions
WO2007078913A2 (en
Inventor
Bran Ferren
Daniel W Hillis
William Henry Mangione-Smith
Nathan P Myhrvold
Clarence T Tegreene
Lowell L Wood Jr
Original Assignee
Searete Llc
Bran Ferren
Daniel W Hillis
William Henry Mangione-Smith
Nathan P Myhrvold
Clarence T Tegreene
Lowell L Wood Jr
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/324,174 external-priority patent/US20070050605A1/en
Priority claimed from US11/343,927 external-priority patent/US8214191B2/en
Application filed by Searete Llc, Bran Ferren, Daniel W Hillis, William Henry Mangione-Smith, Nathan P Myhrvold, Clarence T Tegreene, Lowell L Wood Jr filed Critical Searete Llc
Publication of WO2007078913A2 publication Critical patent/WO2007078913A2/en
Publication of WO2007078913A3 publication Critical patent/WO2007078913A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/443—Optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/443—Optimisation
    • G06F8/4441—Reducing the execution time required by the program code

Abstract

Embodiments include a device, apparatus, and a method. A device includes an input circuit for receiving data corresponding to a runtime execution of a first instruction by a first processor having a first architecture. The device also includes a generator circuit for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture.
PCT/US2006/048213 2005-12-30 2006-12-18 Cross-architecture execution optimization WO2007078913A2 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US11/324,174 2005-12-30
US11/324,174 US20070050605A1 (en) 2005-08-29 2005-12-30 Freeze-dried ghost pages
US11/343,927 US8214191B2 (en) 2005-08-29 2006-01-31 Cross-architecture execution optimization
US11/343,927 2006-01-31
US11/343,745 2006-01-31
US11/343,745 US8209524B2 (en) 2005-08-29 2006-01-31 Cross-architecture optimization

Publications (2)

Publication Number Publication Date
WO2007078913A2 WO2007078913A2 (en) 2007-07-12
WO2007078913A3 true WO2007078913A3 (en) 2008-11-13

Family

ID=38228766

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/048213 WO2007078913A2 (en) 2005-12-30 2006-12-18 Cross-architecture execution optimization

Country Status (2)

Country Link
US (1) US8209524B2 (en)
WO (1) WO2007078913A2 (en)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7627739B2 (en) * 2005-08-29 2009-12-01 Searete, Llc Optimization of a hardware resource shared by a multiprocessor
US8255745B2 (en) * 2005-08-29 2012-08-28 The Invention Science Fund I, Llc Hardware-error tolerant computing
US8214191B2 (en) * 2005-08-29 2012-07-03 The Invention Science Fund I, Llc Cross-architecture execution optimization
US20070050606A1 (en) * 2005-08-29 2007-03-01 Searete Llc, A Limited Liability Corporation Of The State Of Delaware Runtime-based optimization profile
US7647487B2 (en) * 2005-08-29 2010-01-12 Searete, Llc Instruction-associated processor resource optimization
US8375247B2 (en) * 2005-08-29 2013-02-12 The Invention Science Fund I, Llc Handling processor computational errors
US8516300B2 (en) 2005-08-29 2013-08-20 The Invention Science Fund I, Llc Multi-votage synchronous systems
US7877584B2 (en) * 2005-08-29 2011-01-25 The Invention Science Fund I, Llc Predictive processor resource management
US7725693B2 (en) * 2005-08-29 2010-05-25 Searete, Llc Execution optimization using a processor resource management policy saved in an association with an instruction group
US8423824B2 (en) 2005-08-29 2013-04-16 The Invention Science Fund I, Llc Power sparing synchronous apparatus
US7774558B2 (en) * 2005-08-29 2010-08-10 The Invention Science Fund I, Inc Multiprocessor resource optimization
US7779213B2 (en) 2005-08-29 2010-08-17 The Invention Science Fund I, Inc Optimization of instruction group execution through hardware resource management policies
US7653834B2 (en) 2005-08-29 2010-01-26 Searete, Llc Power sparing synchronous apparatus
US7739524B2 (en) * 2005-08-29 2010-06-15 The Invention Science Fund I, Inc Power consumption management
US8181004B2 (en) * 2005-08-29 2012-05-15 The Invention Science Fund I, Llc Selecting a resource management policy for a resource available to a processor
US8838620B2 (en) * 2006-02-03 2014-09-16 International Business Machines Corporation Predictive data object retrieval
KR100813662B1 (en) * 2006-11-17 2008-03-14 삼성전자주식회사 Profiler for optimizing processor architecture and application
US8522217B2 (en) * 2010-04-20 2013-08-27 Microsoft Corporation Visualization of runtime analysis across dynamic boundaries
US8782434B1 (en) 2010-07-15 2014-07-15 The Research Foundation For The State University Of New York System and method for validating program execution at run-time
US9195486B2 (en) * 2010-07-30 2015-11-24 Apple Inc. Observation and analysis based code optimization
US9122873B2 (en) 2012-09-14 2015-09-01 The Research Foundation For The State University Of New York Continuous run-time validation of program execution: a practical approach
US9069782B2 (en) 2012-10-01 2015-06-30 The Research Foundation For The State University Of New York System and method for security and privacy aware virtual machine checkpointing
EP3049921A4 (en) * 2013-09-26 2017-05-17 Intel Corporation Methods and apparatus to validate translated guest code in a dynamic binary translator

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030079113A1 (en) * 1991-07-08 2003-04-24 Nguyen Le Trong High-performance, superscalar-based computer system with out-of-order instruction execution
US20030200537A1 (en) * 2002-04-18 2003-10-23 International Business Machines Corporation Apparatus and method for using database knowledge to optimize a computer program
US20040073894A1 (en) * 1999-11-12 2004-04-15 Sun Microsystems, Inc., A Delaware Corporation. Optimization of n-base typed arithmetic expressions

Family Cites Families (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4228496A (en) 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
DE3382152D1 (en) 1982-12-09 1991-03-07 Sequoia Systems Inc SECURITY STORAGE SYSTEM.
US4819154A (en) 1982-12-09 1989-04-04 Sequoia Systems, Inc. Memory back up system with one cache memory and two physically separated main memories
US4751639A (en) 1985-06-24 1988-06-14 Ncr Corporation Virtual command rollback in a fault tolerant data processing system
US4847755A (en) * 1985-10-31 1989-07-11 Mcc Development, Ltd. Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies
US4763244A (en) * 1986-01-15 1988-08-09 Motorola, Inc. Paged memory management unit capable of selectively supporting multiple address spaces
US4891787A (en) * 1986-12-17 1990-01-02 Massachusetts Institute Of Technology Parallel processing system with processor array having SIMD/MIMD instruction processing
US5297097A (en) 1988-06-17 1994-03-22 Hitachi Ltd. Large scale integrated circuit for low voltage operation
US5084891A (en) * 1989-09-08 1992-01-28 Bell Communications Research, Inc. Technique for jointly performing bit synchronization and error detection in a TDM/TDMA system
US5212777A (en) * 1989-11-17 1993-05-18 Texas Instruments Incorporated Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation
US5966528A (en) * 1990-11-13 1999-10-12 International Business Machines Corporation SIMD/MIMD array processor with vector processing
EP0496506B1 (en) 1991-01-25 2000-09-20 Hitachi, Ltd. Fault tolerant computer system incorporating processing units which have at least three processors
CA2073516A1 (en) * 1991-11-27 1993-05-28 Peter Michael Kogge Dynamic multi-mode parallel processor array architecture computer system
US5535405A (en) 1993-12-23 1996-07-09 Unisys Corporation Microsequencer bus controller system
IL112660A (en) * 1994-03-31 1998-01-04 Minnesota Mining & Mfg System integrating active and simulated decision- making processes
US6052773A (en) * 1995-02-10 2000-04-18 Massachusetts Institute Of Technology DPGA-coupled microprocessors
US5768551A (en) * 1995-09-29 1998-06-16 Emc Corporation Inter connected loop channel for reducing electrical signal jitter
US7113173B1 (en) 1995-10-16 2006-09-26 Nec Corporation Local handwriting recognition in a wireless interface tablet device
US5691870A (en) 1995-11-07 1997-11-25 Compaq Computer Corporation Circuit for monitoring and disabling power supply signals to a microprocessor in a computer system utilizing secondary voltage regulators
US5774736A (en) * 1995-12-15 1998-06-30 Wright; Robert S. Redundant CPU power system
US6199095B1 (en) 1996-01-29 2001-03-06 Compaq Computer Corporation System and method for achieving object method transparency in a multi-code execution environment
US6535903B2 (en) 1996-01-29 2003-03-18 Compaq Information Technologies Group, L.P. Method and apparatus for maintaining translated routine stack in a binary translation environment
US5915232A (en) * 1996-12-10 1999-06-22 Advanced Micro Devices, Inc. Method and apparatus for tracking power of an integrated circuit
US6021489A (en) * 1997-06-30 2000-02-01 Intel Corporation Apparatus and method for sharing a branch prediction unit in a microprocessor implementing a two instruction set architecture
US6374349B2 (en) * 1998-03-19 2002-04-16 Mcfarling Scott Branch predictor with serially connected predictor stages for improving branch prediction accuracy
US6247118B1 (en) 1998-06-05 2001-06-12 Mcdonnell Douglas Corporation Systems and methods for transient error recovery in reduced instruction set computer processors via instruction retry
US6205537B1 (en) * 1998-07-16 2001-03-20 University Of Rochester Mechanism for dynamically adapting the complexity of a microprocessor
US6553488B2 (en) 1998-09-08 2003-04-22 Intel Corporation Method and apparatus for branch prediction using first and second level branch prediction tables
US6611910B2 (en) 1998-10-12 2003-08-26 Idea Corporation Method for processing branch operations
GB9825102D0 (en) * 1998-11-16 1999-01-13 Insignia Solutions Plc Computer system
US6954923B1 (en) * 1999-01-28 2005-10-11 Ati International Srl Recording classification of instructions executed by a computer
US8065504B2 (en) 1999-01-28 2011-11-22 Ati International Srl Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor
US6763452B1 (en) * 1999-01-28 2004-07-13 Ati International Srl Modifying program execution based on profiling
US6347341B1 (en) * 1999-02-22 2002-02-12 International Business Machines Corporation Computer program product used for exchange and transfer of data having a siga vector and utilizing a queued direct input-output device
US6496056B1 (en) * 1999-03-08 2002-12-17 Agere Systems Inc. Process-tolerant integrated circuit design
US6499101B1 (en) 1999-03-18 2002-12-24 I.P. First L.L.C. Static branch prediction mechanism for conditional branch instructions
US6427206B1 (en) * 1999-05-03 2002-07-30 Intel Corporation Optimized branch predictions for strongly predicted compiler branches
US6519654B1 (en) * 1999-07-07 2003-02-11 Sharp Laboratories Of America, Incorporation Method of designing an interface for a real-time messaging system
US6985547B2 (en) * 1999-09-27 2006-01-10 The Board Of Governors For Higher Education, State Of Rhode Island And Providence Plantations System and method of digital system performance enhancement
US6772325B1 (en) * 1999-10-01 2004-08-03 Hitachi, Ltd. Processor architecture and operation for exploiting improved branch control instruction
US6324643B1 (en) * 1999-10-01 2001-11-27 Hitachi, Ltd. Branch prediction and target instruction control for processor
US6675374B2 (en) * 1999-10-12 2004-01-06 Hewlett-Packard Development Company, L.P. Insertion of prefetch instructions into computer program code
US6625750B1 (en) 1999-11-16 2003-09-23 Emc Corporation Hardware and software failover services for a file server
US6571373B1 (en) * 2000-01-31 2003-05-27 International Business Machines Corporation Simulator-independent system-on-chip verification methodology
KR100395763B1 (en) 2000-02-01 2003-08-25 삼성전자주식회사 A branch predictor for microprocessor having multiple processes
US7085920B2 (en) 2000-02-02 2006-08-01 Fujitsu Limited Branch prediction method, arithmetic and logic unit, and information processing apparatus for performing brach prediction at the time of occurrence of a branch instruction
JP3502592B2 (en) 2000-03-02 2004-03-02 株式会社東芝 Branch prediction device
JP3641997B2 (en) * 2000-03-30 2005-04-27 日本電気株式会社 Program conversion apparatus and method, and recording medium
US6766419B1 (en) * 2000-03-31 2004-07-20 Intel Corporation Optimization of cache evictions through software hints
WO2001095161A2 (en) 2000-06-02 2001-12-13 Virtio Corporation Method and system for virtual prototyping
US6877084B1 (en) * 2000-08-09 2005-04-05 Advanced Micro Devices, Inc. Central processing unit (CPU) accessing an extended register set in an extended register mode
JP3664473B2 (en) * 2000-10-04 2005-06-29 インターナショナル・ビジネス・マシーンズ・コーポレーション Program optimization method and compiler using the same
GB0028079D0 (en) * 2000-11-17 2001-01-03 Imperial College System and method
US20020087828A1 (en) * 2000-12-28 2002-07-04 International Business Machines Corporation Symmetric multiprocessing (SMP) system with fully-interconnected heterogenous microprocessors
US6986066B2 (en) * 2001-01-05 2006-01-10 International Business Machines Corporation Computer system having low energy consumption
US7231531B2 (en) * 2001-03-16 2007-06-12 Dualcor Technologies, Inc. Personal electronics device with a dual core processor
US7140010B2 (en) * 2001-03-30 2006-11-21 Sun Microsystems, Inc. Method and apparatus for simultaneous optimization of code targeting multiple machines
US7072975B2 (en) * 2001-04-24 2006-07-04 Wideray Corporation Apparatus and method for communicating information to portable computing devices
US6968476B2 (en) 2001-06-27 2005-11-22 International Business Machines Corporation Checkpointing a superscalar, out-of-order processor for error recovery
US6792599B2 (en) * 2001-10-15 2004-09-14 Intel Corporation Method and apparatus for an atomic operation in a parallel computing environment
US7039910B2 (en) * 2001-11-28 2006-05-02 Sun Microsystems, Inc. Technique for associating execution characteristics with instructions or operations of program code
US6959372B1 (en) * 2002-02-19 2005-10-25 Cogent Chipware Inc. Processor cluster architecture and associated parallel processing methods
US7082602B2 (en) * 2002-04-12 2006-07-25 Intel Corporation Function unit based finite state automata data structure, transitions and methods for making the same
US7100060B2 (en) * 2002-06-26 2006-08-29 Intel Corporation Techniques for utilization of asymmetric secondary processing resources
US20040093591A1 (en) 2002-11-12 2004-05-13 Spiros Kalogeropulos Method and apparatus prefetching indexed array references
US7886164B1 (en) * 2002-11-14 2011-02-08 Nvidia Corporation Processor temperature adjustment system and method
US7028218B2 (en) 2002-12-02 2006-04-11 Emc Corporation Redundant multi-processor and logical processor configuration for a file server
US7260742B2 (en) 2003-01-28 2007-08-21 Czajkowski David R SEU and SEFI fault tolerant computer
WO2004084070A1 (en) 2003-03-20 2004-09-30 Arm Limited Systematic and random error detection and recovery within processing stages of an integrated circuit
US7093147B2 (en) * 2003-04-25 2006-08-15 Hewlett-Packard Development Company, L.P. Dynamically selecting processor cores for overall power efficiency
US7373642B2 (en) * 2003-07-29 2008-05-13 Stretch, Inc. Defining instruction extensions in a standard programming language
US6927611B2 (en) * 2003-10-29 2005-08-09 International Business Machines Corporation Semidigital delay-locked loop using an analog-based finite state machine
US20050093607A1 (en) 2003-11-05 2005-05-05 David Marshall Data transmission circuit and method
US20050138478A1 (en) 2003-11-14 2005-06-23 Safford Kevin D. Error detection method and system for processors that employ alternating threads
US7770034B2 (en) * 2003-12-16 2010-08-03 Intel Corporation Performance monitoring based dynamic voltage and frequency scaling
US20050149915A1 (en) * 2003-12-29 2005-07-07 Intel Corporation Methods and apparatus for optimizing a program undergoing dynamic binary translation using profile information
US7496908B2 (en) * 2004-01-14 2009-02-24 International Business Machines Corporation Method and apparatus for optimizing code execution using annotated trace information having performance indicator and counter information
JP2005301476A (en) 2004-04-08 2005-10-27 Hitachi Ltd Power supply control system and storage device
US7613881B2 (en) * 2004-06-08 2009-11-03 Dartdevices Interop Corporation Method and system for configuring and using virtual pointers to access one or more independent address spaces
US7376849B2 (en) 2004-06-30 2008-05-20 Intel Corporation Method, apparatus and system of adjusting one or more performance-related parameters of a processor
US20060026543A1 (en) * 2004-07-29 2006-02-02 Texas Instruments Incorporated Accurate timing analysis of integrated circuits when combinatorial logic offers a load
US20060119382A1 (en) 2004-12-07 2006-06-08 Shumarayev Sergey Y Apparatus and methods for adjusting performance characteristics of programmable logic devices
US7791889B2 (en) 2005-02-16 2010-09-07 Hewlett-Packard Development Company, L.P. Redundant power beneath circuit board
JP4330547B2 (en) 2005-03-17 2009-09-16 富士通株式会社 Information processing system control method, information processing system, information processing system control program, and redundant configuration control device
US20070006178A1 (en) * 2005-05-12 2007-01-04 Microsoft Corporation Function-level just-in-time translation engine with multiple pass optimization
US7647487B2 (en) 2005-08-29 2010-01-12 Searete, Llc Instruction-associated processor resource optimization
US7653834B2 (en) 2005-08-29 2010-01-26 Searete, Llc Power sparing synchronous apparatus
US8214191B2 (en) 2005-08-29 2012-07-03 The Invention Science Fund I, Llc Cross-architecture execution optimization
US7774558B2 (en) 2005-08-29 2010-08-10 The Invention Science Fund I, Inc Multiprocessor resource optimization
US8181004B2 (en) 2005-08-29 2012-05-15 The Invention Science Fund I, Llc Selecting a resource management policy for a resource available to a processor
US20070050606A1 (en) 2005-08-29 2007-03-01 Searete Llc, A Limited Liability Corporation Of The State Of Delaware Runtime-based optimization profile
US7779213B2 (en) 2005-08-29 2010-08-17 The Invention Science Fund I, Inc Optimization of instruction group execution through hardware resource management policies
US8375247B2 (en) 2005-08-29 2013-02-12 The Invention Science Fund I, Llc Handling processor computational errors
US7725693B2 (en) 2005-08-29 2010-05-25 Searete, Llc Execution optimization using a processor resource management policy saved in an association with an instruction group
US7739524B2 (en) 2005-08-29 2010-06-15 The Invention Science Fund I, Inc Power consumption management
US7627739B2 (en) 2005-08-29 2009-12-01 Searete, Llc Optimization of a hardware resource shared by a multiprocessor
US20070050605A1 (en) 2005-08-29 2007-03-01 Bran Ferren Freeze-dried ghost pages
US7877584B2 (en) 2005-08-29 2011-01-25 The Invention Science Fund I, Llc Predictive processor resource management
DE102005049232A1 (en) * 2005-10-14 2007-04-26 Infineon Technologies Ag Integrated circuit and method for operating an integrated circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030079113A1 (en) * 1991-07-08 2003-04-24 Nguyen Le Trong High-performance, superscalar-based computer system with out-of-order instruction execution
US20040073894A1 (en) * 1999-11-12 2004-04-15 Sun Microsystems, Inc., A Delaware Corporation. Optimization of n-base typed arithmetic expressions
US20030200537A1 (en) * 2002-04-18 2003-10-23 International Business Machines Corporation Apparatus and method for using database knowledge to optimize a computer program

Also Published As

Publication number Publication date
WO2007078913A2 (en) 2007-07-12
US8209524B2 (en) 2012-06-26
US20070074173A1 (en) 2007-03-29

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