WO2006124410A3 - Latency insensitive fifo signaling protocol - Google Patents

Latency insensitive fifo signaling protocol Download PDF

Info

Publication number
WO2006124410A3
WO2006124410A3 PCT/US2006/017899 US2006017899W WO2006124410A3 WO 2006124410 A3 WO2006124410 A3 WO 2006124410A3 US 2006017899 W US2006017899 W US 2006017899W WO 2006124410 A3 WO2006124410 A3 WO 2006124410A3
Authority
WO
WIPO (PCT)
Prior art keywords
fifo
data
counter
source
domain
Prior art date
Application number
PCT/US2006/017899
Other languages
French (fr)
Other versions
WO2006124410A2 (en
Inventor
Kenneth Alan Dockser
Victor Roberts Augsburg
James Norris Dieffenderfer
Jeffrey Todd Bridges
Robert Douglas Clancy
Thomas Andrew Sartorius
Original Assignee
Qualcomm Inc
Kenneth Alan Dockser
Victor Roberts Augsburg
James Norris Dieffenderfer
Jeffrey Todd Bridges
Robert Douglas Clancy
Thomas Andrew Sartorius
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc, Kenneth Alan Dockser, Victor Roberts Augsburg, James Norris Dieffenderfer, Jeffrey Todd Bridges, Robert Douglas Clancy, Thomas Andrew Sartorius filed Critical Qualcomm Inc
Priority to BRPI0608975-5A priority Critical patent/BRPI0608975A2/en
Priority to CN2006800243721A priority patent/CN101213534B/en
Priority to JP2008511268A priority patent/JP4681046B2/en
Priority to EP06752441A priority patent/EP1880299A4/en
Publication of WO2006124410A2 publication Critical patent/WO2006124410A2/en
Publication of WO2006124410A3 publication Critical patent/WO2006124410A3/en
Priority to IL187298A priority patent/IL187298A0/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/12—Indexing scheme relating to groups G06F5/12 - G06F5/14
    • G06F2205/126—Monitoring of intermediate fill level, i.e. with additional means for monitoring the fill level, e.g. half full flag, almost empty flag

Abstract

Data from a source domain (311 ) operating at a first data rate is transferred to a FIFO (319) in another domain (313) operating at a different data rate. The FIFO (319) buffers data before transfer to a sink for further processing or storage. A source side counter (325) tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter (325) decrements in response to a data ready signal from the source domain (311)1 without delay. The counter (325) increments in response to signaling from the sink domain (313) of a read of data off the FIFO (319). Hence, incrementing is subject to the signaling latency between domains. The source (315) may send one more beat of data when the counter (325) indicates the FIFO (319) is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one o more FIFO positions.
PCT/US2006/017899 2005-05-11 2006-05-08 Latency insensitive fifo signaling protocol WO2006124410A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
BRPI0608975-5A BRPI0608975A2 (en) 2005-05-11 2006-05-08 fifo signaling protocol insensitive to latency
CN2006800243721A CN101213534B (en) 2005-05-11 2006-05-08 Latency insensitive FIFO signaling protocol
JP2008511268A JP4681046B2 (en) 2005-05-11 2006-05-08 Insensitive FIFO signaling protocol
EP06752441A EP1880299A4 (en) 2005-05-11 2006-05-08 Latency insensitive fifo signaling protocol
IL187298A IL187298A0 (en) 2005-05-11 2007-11-11 Latency insensitive fifo signaling protocol

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/128,135 US7454538B2 (en) 2005-05-11 2005-05-11 Latency insensitive FIFO signaling protocol
US11/128,135 2005-05-11

Publications (2)

Publication Number Publication Date
WO2006124410A2 WO2006124410A2 (en) 2006-11-23
WO2006124410A3 true WO2006124410A3 (en) 2007-09-20

Family

ID=37420511

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/017899 WO2006124410A2 (en) 2005-05-11 2006-05-08 Latency insensitive fifo signaling protocol

Country Status (8)

Country Link
US (2) US7454538B2 (en)
EP (1) EP1880299A4 (en)
JP (2) JP4681046B2 (en)
KR (1) KR100965356B1 (en)
CN (1) CN101213534B (en)
BR (1) BRPI0608975A2 (en)
IL (1) IL187298A0 (en)
WO (1) WO2006124410A2 (en)

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US7613909B2 (en) * 2007-04-17 2009-11-03 Xmos Limited Resuming thread to service ready port transferring data externally at different clock rate than internal circuitry of a processor
JP5532724B2 (en) * 2009-07-30 2014-06-25 株式会社リコー Interface circuit and semiconductor device having the same
KR20110061189A (en) * 2009-12-01 2011-06-09 삼성전자주식회사 Asynchronization upsizing circuit in data processing system
TWI466016B (en) * 2011-07-01 2014-12-21 Realtek Semiconductor Corp First in first out device and method thereof
CN104038306B (en) * 2013-03-05 2017-09-29 上海航天测控通信研究所 The method and its asynchronous FIFO of low delay real-time Transmission multi code Rate of Chinese character bit stream data
US9880961B2 (en) * 2013-11-27 2018-01-30 Arm Limited Asynchronous bridge circuitry and a method of transferring data using asynchronous bridge circuitry
JPWO2016158063A1 (en) * 2015-03-30 2018-01-25 ソニーセミコンダクタソリューションズ株式会社 Asynchronous interface
TWI680466B (en) 2015-05-28 2019-12-21 日商東芝記憶體股份有限公司 Semiconductor device
CN108280437B (en) * 2018-01-30 2021-06-15 四川新先达测控技术有限公司 Pulse signal processing method and device and user terminal
CN111008002B (en) * 2019-12-06 2022-04-08 苏州盛科通信股份有限公司 Apparatus and method for automatically calculating and updating FIFO depth
CN113220607B (en) * 2021-05-26 2023-05-12 浙江赛思电子科技有限公司 Data processing method based on FIFO
CN114443524A (en) * 2022-01-28 2022-05-06 山东云海国创云计算装备产业创新中心有限公司 Data transmission method, system, storage medium and equipment

Citations (2)

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US6115760A (en) * 1998-08-24 2000-09-05 3Com Corporation Intelligent scaleable FIFO buffer circuit for interfacing between digital domains
US20020172156A1 (en) * 2001-05-15 2002-11-21 Sandbote Sam B. Adaptive control of multiplexed input buffer channels

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JPS62219390A (en) * 1986-03-20 1987-09-26 Fujitsu Ltd Fifo memory
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US6115760A (en) * 1998-08-24 2000-09-05 3Com Corporation Intelligent scaleable FIFO buffer circuit for interfacing between digital domains
US20020172156A1 (en) * 2001-05-15 2002-11-21 Sandbote Sam B. Adaptive control of multiplexed input buffer channels

Also Published As

Publication number Publication date
KR20080007506A (en) 2008-01-21
US7725625B2 (en) 2010-05-25
WO2006124410A2 (en) 2006-11-23
CN101213534B (en) 2012-02-15
JP2008541623A (en) 2008-11-20
US7454538B2 (en) 2008-11-18
BRPI0608975A2 (en) 2010-02-17
KR100965356B1 (en) 2010-06-23
US20080281996A1 (en) 2008-11-13
JP4681046B2 (en) 2011-05-11
IL187298A0 (en) 2009-02-11
CN101213534A (en) 2008-07-02
EP1880299A4 (en) 2009-07-08
US20060259669A1 (en) 2006-11-16
EP1880299A2 (en) 2008-01-23
JP2011101390A (en) 2011-05-19
JP4976537B2 (en) 2012-07-18

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