WO2006023360A1 - Memory command delay balancing in a daisy-chained memory topology - Google Patents
Memory command delay balancing in a daisy-chained memory topology Download PDFInfo
- Publication number
- WO2006023360A1 WO2006023360A1 PCT/US2005/028535 US2005028535W WO2006023360A1 WO 2006023360 A1 WO2006023360 A1 WO 2006023360A1 US 2005028535 W US2005028535 W US 2005028535W WO 2006023360 A1 WO2006023360 A1 WO 2006023360A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- command
- memory
- controller
- delay
- response
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Dram (AREA)
- Communication Control (AREA)
- Information Transfer Systems (AREA)
- Computer And Data Communications (AREA)
- Multi Processors (AREA)
- Memory System (AREA)
Abstract
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AT05784488T ATE435457T1 (en) | 2004-08-19 | 2005-08-09 | MEMORY INSTRUCTION DELAY COMPENSATION IN A CHAINED MEMORY TOPOLOGY |
DE602005015225T DE602005015225D1 (en) | 2004-08-19 | 2005-08-09 | MEMORY COMMUNICATION DELAY IN A CHAINED MEMORY TOPOLOGY |
KR1020077002577A KR100883007B1 (en) | 2004-08-19 | 2005-08-09 | Memory command delay balancing in a daisy-chained memory topology |
EP05784488A EP1779251B1 (en) | 2004-08-19 | 2005-08-09 | Memory command delay balancing in a daisy-chained memory topology |
CN2005800283599A CN101014941B (en) | 2004-08-19 | 2005-08-09 | Memory command delay balancing in a daisy-chained memory topology |
JP2007527878A JP4742347B2 (en) | 2004-08-19 | 2005-08-09 | Memory command delay balancing for daisy-chained memory topologies |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/922,299 | 2004-08-19 | ||
US10/922,299 US7669027B2 (en) | 2004-08-19 | 2004-08-19 | Memory command delay balancing in a daisy-chained memory topology |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006023360A1 true WO2006023360A1 (en) | 2006-03-02 |
Family
ID=35311582
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2005/028535 WO2006023360A1 (en) | 2004-08-19 | 2005-08-09 | Memory command delay balancing in a daisy-chained memory topology |
Country Status (9)
Country | Link |
---|---|
US (5) | US7669027B2 (en) |
EP (1) | EP1779251B1 (en) |
JP (1) | JP4742347B2 (en) |
KR (1) | KR100883007B1 (en) |
CN (1) | CN101014941B (en) |
AT (1) | ATE435457T1 (en) |
DE (1) | DE602005015225D1 (en) |
TW (1) | TWI317068B (en) |
WO (1) | WO2006023360A1 (en) |
Cited By (7)
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JP2009531746A (en) * | 2006-03-28 | 2009-09-03 | モサイド・テクノロジーズ・インコーポレーテッド | Daisy chain layout of non-volatile memory |
US8166268B2 (en) | 2004-08-19 | 2012-04-24 | Micron Technology, Inc. | Memory command delay balancing in a daisy-chained memory topology |
US8654601B2 (en) | 2005-09-30 | 2014-02-18 | Mosaid Technologies Incorporated | Memory with output control |
US8743610B2 (en) | 2005-09-30 | 2014-06-03 | Conversant Intellectual Property Management Inc. | Method and system for accessing a flash memory device |
US8773928B2 (en) | 2009-07-09 | 2014-07-08 | Micron Technology, Inc. | Command latency systems and methods |
US9240227B2 (en) | 2005-09-30 | 2016-01-19 | Conversant Intellectual Property Management Inc. | Daisy chain cascading devices |
DE102006062725B4 (en) * | 2006-04-15 | 2018-01-18 | Polaris Innovations Ltd. | Memory system with integrated memory modules and method for operating a memory system |
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KR100666225B1 (en) * | 2005-02-17 | 2007-01-09 | 삼성전자주식회사 | Multi device system forming daisy chain and operating method for the same |
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US5892981A (en) * | 1996-10-10 | 1999-04-06 | Hewlett-Packard Company | Memory system and device |
WO1999019876A1 (en) * | 1997-10-10 | 1999-04-22 | Rambus Incorporated | Apparatus and method for device timing compensation |
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2004
- 2004-08-19 US US10/922,299 patent/US7669027B2/en not_active Expired - Fee Related
-
2005
- 2005-08-09 KR KR1020077002577A patent/KR100883007B1/en not_active IP Right Cessation
- 2005-08-09 DE DE602005015225T patent/DE602005015225D1/en active Active
- 2005-08-09 CN CN2005800283599A patent/CN101014941B/en not_active Expired - Fee Related
- 2005-08-09 EP EP05784488A patent/EP1779251B1/en not_active Not-in-force
- 2005-08-09 AT AT05784488T patent/ATE435457T1/en not_active IP Right Cessation
- 2005-08-09 WO PCT/US2005/028535 patent/WO2006023360A1/en active Application Filing
- 2005-08-09 JP JP2007527878A patent/JP4742347B2/en not_active Expired - Fee Related
- 2005-08-12 TW TW094127497A patent/TWI317068B/en not_active IP Right Cessation
-
2010
- 2010-01-19 US US12/689,495 patent/US7908451B2/en not_active Expired - Fee Related
-
2011
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-
2012
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2013
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Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8166268B2 (en) | 2004-08-19 | 2012-04-24 | Micron Technology, Inc. | Memory command delay balancing in a daisy-chained memory topology |
US8612712B2 (en) | 2004-08-19 | 2013-12-17 | Round Rock Research, Llc | Memory command delay balancing in a daisy-chained memory topology |
US8935505B2 (en) | 2004-08-19 | 2015-01-13 | Round Rock Research, Llc | System and method for controlling memory command delay |
US8654601B2 (en) | 2005-09-30 | 2014-02-18 | Mosaid Technologies Incorporated | Memory with output control |
US8743610B2 (en) | 2005-09-30 | 2014-06-03 | Conversant Intellectual Property Management Inc. | Method and system for accessing a flash memory device |
US9230654B2 (en) | 2005-09-30 | 2016-01-05 | Conversant Intellectual Property Management Inc. | Method and system for accessing a flash memory device |
US9240227B2 (en) | 2005-09-30 | 2016-01-19 | Conversant Intellectual Property Management Inc. | Daisy chain cascading devices |
JP2009531746A (en) * | 2006-03-28 | 2009-09-03 | モサイド・テクノロジーズ・インコーポレーテッド | Daisy chain layout of non-volatile memory |
JP2013037712A (en) * | 2006-03-28 | 2013-02-21 | Mosaid Technologies Inc | Daisy chain arrangement of nonvolatile memory |
DE102006062725B4 (en) * | 2006-04-15 | 2018-01-18 | Polaris Innovations Ltd. | Memory system with integrated memory modules and method for operating a memory system |
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Also Published As
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DE602005015225D1 (en) | 2009-08-13 |
CN101014941A (en) | 2007-08-08 |
TW200619950A (en) | 2006-06-16 |
EP1779251B1 (en) | 2009-07-01 |
CN101014941B (en) | 2013-03-06 |
US20120210089A1 (en) | 2012-08-16 |
US20110145522A1 (en) | 2011-06-16 |
EP1779251A1 (en) | 2007-05-02 |
US20100122059A1 (en) | 2010-05-13 |
US7669027B2 (en) | 2010-02-23 |
US7908451B2 (en) | 2011-03-15 |
JP2008510257A (en) | 2008-04-03 |
KR100883007B1 (en) | 2009-02-12 |
US8935505B2 (en) | 2015-01-13 |
US8612712B2 (en) | 2013-12-17 |
KR20070039117A (en) | 2007-04-11 |
US8166268B2 (en) | 2012-04-24 |
US20140089620A1 (en) | 2014-03-27 |
JP4742347B2 (en) | 2011-08-10 |
TWI317068B (en) | 2009-11-11 |
ATE435457T1 (en) | 2009-07-15 |
US20060041730A1 (en) | 2006-02-23 |
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