WO2005114670B1 - Pipelined data relocation and improved chip architectures - Google Patents

Pipelined data relocation and improved chip architectures

Info

Publication number
WO2005114670B1
WO2005114670B1 PCT/US2005/016341 US2005016341W WO2005114670B1 WO 2005114670 B1 WO2005114670 B1 WO 2005114670B1 US 2005016341 W US2005016341 W US 2005016341W WO 2005114670 B1 WO2005114670 B1 WO 2005114670B1
Authority
WO
WIPO (PCT)
Prior art keywords
data
controller
memory
registers
transferring
Prior art date
Application number
PCT/US2005/016341
Other languages
French (fr)
Other versions
WO2005114670A1 (en
Inventor
Sergey Anatolievich Gorobets
Kevin M Conley
Original Assignee
Sandisk Corp
Sergey Anatolievich Gorobets
Kevin M Conley
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandisk Corp, Sergey Anatolievich Gorobets, Kevin M Conley filed Critical Sandisk Corp
Priority to KR20067023780A priority Critical patent/KR101152283B1/en
Priority to EP05742859A priority patent/EP1756832A1/en
Publication of WO2005114670A1 publication Critical patent/WO2005114670A1/en
Publication of WO2005114670B1 publication Critical patent/WO2005114670B1/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023Free address space management
    • G06F12/0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Abstract

The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural improve are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.

Claims

AMENDED CLAIMS[Received by the International Bureau on 10 November 2005 (10.11.2005): original claims 1-46 replaced by amended/added claims 1-47; (9 pages)]
1. A memory system, comprising: a controller; and a memory, including: a non-volatile data storage section; and first and second data registers to temporarily store data, wherein first data can be transferred between either one of the data registers and the controller concurrently with transferring second data between the other one of the data registers and the non-volatile data storage section.
2. The memory system of claim I3 wherein said with tnmsferring second data between the other one of the data registers and the non-volatile data storage section is a transfer to the non-volatile data storage section and lhc first data can additionally be transferred to said either one of the data registers from the non¬ volatile data storage section concurrently with the transferring second data.
3. The memory system of claim 1, wherein the memory exchanges the coαtents of the first data register with the contents of the second data register in response to a command from the controller.
4. The memory system of claim 1, wherein the memory exchanges the contents of the first data register with the contents of the second data register in response to a command from the controller.
5. The memory system of any of claims 1-4, wherein ihe second data can be operated upon in the controller concurrently with transferring the first data between said one of the data registers and the non-volatile data storage section.
6. The memory system of claim 5, wherein the controller includes error correction circuitry and the controller can perform error correction operations
40 upon the second data concurrently with transferring the first data between said one of the data registers and the non-volatile data storage section.
7. The memory system of claim 5, wherein the controller can perform data verification operations upon the second data concurrently with transferring the first data be.ween said one of the data registers and the non-volatile data storage section.
8. The memory system of claim 1, wherein said controller includes a plurality of data buffers and wherein the controller can perform a data checking operation on the contents of a first of said data buffers concurrently with transferring data between another of said data buffers and said memory .
9. The memory system of claim 8, wherein said data checking operation is an error detection and correcrion operation.
10. The memory system of claim 8, wherein said data checking operation is program-verify operation.
11. A memory system, comprising: a controller; and a memory, including a non-volatile data storage section; a first data register connectable to the non-volatile data storage section to transfer data between the first data register and the non-volatile data storage section; and a second data register, connectable to the controller to transfer data between the second data register and the controller, wherein the memory exchanges the contents of the first data register with the contents of the second data register in response to a command from the controller.
41
12. The memory system of claim 11, wherein the second data can be operated upon in the controller concurrently with transferring the first data between said one of the data registers and the non-volatile data storage section.
13. The memory system of claim 12, wherein the controller includes error correction circuitry and the controller can perfoπn error correction operations upon the second data concurrently with transferring the first data between said one of the dala registers and the non-volatile data storage section.
14. The memory system of claim 12, wherein the controller can perfoπn data verification operations upon the second data concurrently with transferring the first data between said one of the data registers and the non-volatile data storage section.
15. The memory system of claim H, wherein the exchange the contents is part of a compound command from the controller
16. The memory system of claim 11, wherein said controller includes a plurality of data buffers and wherein the controller can perform a data checking operation on the contents of a first of said data buffers concurrently with transferring data between another of said data buffers and said memory.
17. The memory system of claim 16, wherein said data checking operation is an error detection and correction operation.
18. The memory system of claim 16, wherein said data checking operation is program-verify operation.
19. The memory system of claim 11, further comprising a third data register connectable to the first data register and the second data register, whereby the memory exchanges the contents of the first data register
42 with the contents of the second data register by temporarily storing the contents of one of the first and second data registers in the third data register.
20. The memory system of claim 11, wherein first data can be transferred to one of said data registers from the non-volatile data storage section concurrently with transferring second data from the other one of said data registers to the non-volatile data storage section.
21- A memory system, comprising: a controller including a plurality data buffers; and a memory including a non-volatile data storage section and one or more data registers, wherein the controller can perform a data checking operation on the contents of a first of said data buffers while concurrently transferring data between another of said data buffers and one of said data registers.
22. The memory system of claim 21, wherein said data checking operation is an error detection and correction operation.
23. The memory system of claim 21, wherein said data checking operation is program-verify operation.
24. The memory system of claim 21, wherein the controller can additionally perform a programming operation from said one of said data registers concurrently with said data checking operation.
25. The memory system of claim 21, wherein the memory includes a plurality of said data registers and wherein first data can be transferred io one of said data registers from the non-volatile data storage section concurrently with transferring second data from the other one of said data registers to the non-volatile data storage section.
26. A method of operating a memory system comprising a controller and a memory including first and second data registers and a no ri- volatile data storage section, the method comprising: determining one of said data registers for the transfer of data between the controller and the memory; transferring first data between the memory array and the other of said data registers; and transferring second data between said determined one of the daia registers and the controller, wherein at least a portion of the transferring second data is performed concurrently with said transferring first data.
27. The method of claim 26, wherein said first data is road from the memory into said other of said data registers.
28. The method of claim 26, wherein said first data is programmed from said other of said data registers into the memory.
29. The method of either of claims 26 and 28, wherein said second data is transferred from the controller.
30. The method of either of claims 26-28, wherein said second data is transferred to the controller.
31. The method of claim 30, further comprising, subsequent to transferring the second data to the controller: checking/correcting the second data by the controller.
32. The method of claim 31, wherein said checking/correcting the second data comprises: determining the quality of the second data; and in response to said determining the quality of the second data, cfiTTftrfincr the serΛπH data
44 the method further comprising: transferring back the corrected second data from the controller to said determined one of the data registers, wherein the checking/correcting and the transferring back the second data is performed concurrently with said transferring first data.
33. A method of operating a memory system comprising a controller and a memory including first and second data registers and a non -volatile data storage section, the method comprising: loading first data into a first of said data registers from eiiher the data storage section or the controller; loading second data into the second of said data registers from either the data storage section or the controller; and swapping the memory the contents of the first and second data registers in response to a command from the controller.
34. The method of claim 33, wherein the first data is loaded from the controller and the second data is loaded from the data storage section, further comprising, subsequent to said swapping: transferring the second data from first data register to the controller; and checking/correcting the second data by the controller.
35. The method of claim 34, wherein said checking/correcting the second data comprises: determining the quality of the second data; and in response to said determining the quality of the second data, correcting the second data, the method further comprising: transferring back the corrected second data from the controller to the first data register,1 and
45 programming &e first data from the second data register to the data storage section, wherein said checking/correcting the second data and the transferring the second data to and back from the controller is performed concurrenily with said programming first data.
36. The method claim of 33, the memory system further comprising a third data register, the swapping the memory the contents of the first and second data registers comprising: temporarily storing the contents of one of the first and second data registers in the third data register.
37. A method of operating a memory system comprising a controller including first and second data buffers and a memory including a non¬ volatile data storage section, the method comprising: performing a data checking operation on first data stored in a first of the data buffers; and concurrently transferring second data between the second of the of the data buffers and the memory.
38. The method of claim 37. wherein said data checking operation is a error detection and correction operation.
39. The method of claim 37, wherein said data checking operation is a program verily operation.
40. A method of operating a memory system comprising a controller and a memory including one or more data registers and a non-volatile data storage section, the method comprising sequentially performing in a pipelined manner a plurality of program operations, each of said program operations sequentially comprising the sub-operations of: writing a data set from one of said one or more data registers to the non-volatile data storage section;
46 reading the data set as written back to one of said one or more data registers; transferring the data set as written back to the controller; ard verifying by the controller of the Set data as written, wherein the verifying of the data set for one programming operation is performed concurrently with the writing sub-operation of the following programming operation.
41, The method of claim 40, wherein the transferring of the data set for one programming operation is also performed concurrently with the writing sub- operation of the following programming operation.
42. A method of operating a memory system comprising a controller and a memory a plurality of memory chips, each including one or more data registers and a non-volaifle data storage section, the method comprising sequentially performing in a pipelined manner a plurality of data relocation operations on two or more of said memory chips, each of said data relocation operations on a given one of the memory chips sequentially comprising the sub-operations of: reading a data set from the storage section to oDe of said one or more data registers; transferring the data set to the controller; checking/correcting the data set, wherein said checking/correciing the data set includes: determining the quality of the data set; and if the quality of the data set is not acceptable, correcting the data set; if the data set is corrected, transferring the corrected daia set back to one of said one or more data registers; and programming the data back to the storage section, wherein the checking/correcting of a first data set for one data relocation operation in a first memory chip is performed concurrently with a sub-operation of Ά second data set for the following data relocation operation in the first memory chip and
47 concurrently with a sub-operation of a first data set for the following daia relocation operation in a second memory chip-
43. The method of claim 42, wherein the first data sei in the first memory chip and the first data set in the second meiDOiy chip are logically related.
44. The method of claim 43, wherein the first data set in the first memory chip and the first data set in the second memory chip are part of the same metablock.
45. The method of claim 42, wherein said sub-operutiςm of the following data relocation operation is the following data relocation operation's programming operation.
46. The method of claim 42, wherein the transferring to iind from the controller of the data set for said one data relocation operation is also performed concurrently with the programming sub-operation of the following data relocation operation.
47. The method of claim 42, wherein the reading of the data set for said one data relocation operation is also performed concurrently with the programming sub-operation of the following data relocation operation.
PCT/US2005/016341 2004-05-13 2005-05-09 Pipelined data relocation and improved chip architectures WO2005114670A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR20067023780A KR101152283B1 (en) 2004-05-13 2005-05-09 Pipelined data relocation and improved chip architectures
EP05742859A EP1756832A1 (en) 2004-05-13 2005-05-09 Pipelined data relocation and improved chip architectures

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/846,289 US7490283B2 (en) 2004-05-13 2004-05-13 Pipelined data relocation and improved chip architectures
US10/846,289 2004-05-13

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WO2005114670B1 true WO2005114670B1 (en) 2006-02-09

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US (3) US7490283B2 (en)
EP (1) EP1756832A1 (en)
KR (1) KR101152283B1 (en)
TW (1) TWI287730B (en)
WO (1) WO2005114670A1 (en)

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US7490283B2 (en) 2009-02-10
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US9122591B2 (en) 2015-09-01
US20050257120A1 (en) 2005-11-17
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US8621323B2 (en) 2013-12-31
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KR20070049603A (en) 2007-05-11
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