WO2005112102A3 - Chemical-enhanced package singulation process - Google Patents

Chemical-enhanced package singulation process Download PDF

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Publication number
WO2005112102A3
WO2005112102A3 PCT/US2005/016482 US2005016482W WO2005112102A3 WO 2005112102 A3 WO2005112102 A3 WO 2005112102A3 US 2005016482 W US2005016482 W US 2005016482W WO 2005112102 A3 WO2005112102 A3 WO 2005112102A3
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WO
WIPO (PCT)
Prior art keywords
chemical
matrix
singulation process
inter
chemical etching
Prior art date
Application number
PCT/US2005/016482
Other languages
French (fr)
Other versions
WO2005112102A2 (en
Inventor
Hamza Yilmaz
Anthony Chia
Xiaoguang Zeng
Hie Ming Wong
Liming Wang
Yiju Zhang
Original Assignee
Gem Services Inc
Hamza Yilmaz
Anthony Chia
Xiaoguang Zeng
Hie Ming Wong
Liming Wang
Yiju Zhang
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gem Services Inc, Hamza Yilmaz, Anthony Chia, Xiaoguang Zeng, Hie Ming Wong, Liming Wang, Yiju Zhang filed Critical Gem Services Inc
Priority to JP2007513312A priority Critical patent/JP4599399B2/en
Priority to CN2005800149782A priority patent/CN101292330B/en
Publication of WO2005112102A2 publication Critical patent/WO2005112102A2/en
Publication of WO2005112102A3 publication Critical patent/WO2005112102A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Abstract

Singulation of individual electronic packages fabricated as part of a common matrix, is accomplished by mask patterning and chemical exposure in combination with physical sawing. In one embodiment of a singulation process in accordance with the present invention, an initial, shallow saw cut into inter-package regions of the matrix exposes underlying metal to subsequent chemical etching steps. In an alternative embodiment, a separate photoresist mask may be patterned over the matrix to selectively expose metal in inter-package regions to chemical etching.
PCT/US2005/016482 2004-05-11 2005-05-10 Chemical-enhanced package singulation process WO2005112102A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007513312A JP4599399B2 (en) 2004-05-11 2005-05-10 Chemically improved package singulation method
CN2005800149782A CN101292330B (en) 2004-05-11 2005-05-10 Chemically-enhanced package singulation process

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/843,867 2004-05-11
US10/843,867 US7553700B2 (en) 2004-05-11 2004-05-11 Chemical-enhanced package singulation process

Publications (2)

Publication Number Publication Date
WO2005112102A2 WO2005112102A2 (en) 2005-11-24
WO2005112102A3 true WO2005112102A3 (en) 2007-12-06

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/016482 WO2005112102A2 (en) 2004-05-11 2005-05-10 Chemical-enhanced package singulation process

Country Status (4)

Country Link
US (1) US7553700B2 (en)
JP (1) JP4599399B2 (en)
CN (1) CN101292330B (en)
WO (1) WO2005112102A2 (en)

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JP4643464B2 (en) * 2006-02-13 2011-03-02 株式会社ディスコ Package substrate dividing method and dividing apparatus
JP5232394B2 (en) * 2007-02-28 2013-07-10 ローム株式会社 Manufacturing method of semiconductor device
US7932587B2 (en) * 2007-09-07 2011-04-26 Infineon Technologies Ag Singulated semiconductor package
TWI512897B (en) * 2010-01-18 2015-12-11 Semiconductor Components Ind Semiconductor die singulation method
KR20200053096A (en) * 2018-11-08 2020-05-18 삼성전자주식회사 Method of cleaning a semiconductor chip and apparatus for performing the same
US10937709B2 (en) 2019-01-11 2021-03-02 Infineon Technologies Ag Substrates for semiconductor packages

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US6951801B2 (en) * 2003-01-27 2005-10-04 Freescale Semiconductor, Inc. Metal reduction in wafer scribe area

Also Published As

Publication number Publication date
CN101292330B (en) 2010-06-02
WO2005112102A2 (en) 2005-11-24
JP2008509541A (en) 2008-03-27
CN101292330A (en) 2008-10-22
US7553700B2 (en) 2009-06-30
JP4599399B2 (en) 2010-12-15
US20050255634A1 (en) 2005-11-17

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