WO2005095679A3 - Sequential lithographic methods to reduce stacking fault nucleation sites and structures having reduced stacking fault nucleation sites - Google Patents

Sequential lithographic methods to reduce stacking fault nucleation sites and structures having reduced stacking fault nucleation sites Download PDF

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Publication number
WO2005095679A3
WO2005095679A3 PCT/US2005/004480 US2005004480W WO2005095679A3 WO 2005095679 A3 WO2005095679 A3 WO 2005095679A3 US 2005004480 W US2005004480 W US 2005004480W WO 2005095679 A3 WO2005095679 A3 WO 2005095679A3
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WO
WIPO (PCT)
Prior art keywords
nucleation sites
stacking fault
fault nucleation
structures
silicon carbide
Prior art date
Application number
PCT/US2005/004480
Other languages
French (fr)
Other versions
WO2005095679A2 (en
Inventor
Christer Hallin
Heinz Lendenmann
Joseph John Sumakeris
Original Assignee
Cree Inc
Christer Hallin
Heinz Lendenmann
Joseph John Sumakeris
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cree Inc, Christer Hallin, Heinz Lendenmann, Joseph John Sumakeris filed Critical Cree Inc
Priority to EP05760477A priority Critical patent/EP1726037B1/en
Priority to DE602005020911T priority patent/DE602005020911D1/en
Priority to AT05760477T priority patent/ATE466377T1/en
Priority to CA002554815A priority patent/CA2554815A1/en
Priority to JP2007503907A priority patent/JP5014117B2/en
Publication of WO2005095679A2 publication Critical patent/WO2005095679A2/en
Publication of WO2005095679A3 publication Critical patent/WO2005095679A3/en
Priority to KR1020067019094A priority patent/KR101074598B1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02378Silicon carbide
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/02428Structure
    • H01L21/0243Surface structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/02433Crystal orientation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02529Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02636Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639Preparation of substrate for selective deposition
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/931Silicon carbide semiconductor

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Apparatus For Radiation Diagnosis (AREA)
  • Detection And Correction Of Errors (AREA)
  • Stacking Of Articles And Auxiliary Devices (AREA)

Abstract

An epitaxial silicon carbide layer is fabricated by forming first features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The first features include at least one sidewall that is orientated nonparallel (i.e., oblique or perpendicular) to the crystallographic direction. A first epitaxial silicon carbide layer is then grown on the surface of the silicon carbide substrate that includes first features therein. Second features are then formed in the first epitaxial layer. The second features include at least one sidewall that is oriented nonparallel to the crystallographic direction. A second epitaxial silicon carbide layer is then grown on the surface of the first epitaxial silicon carbide layer that includes the second features therein.
PCT/US2005/004480 2004-03-18 2005-02-14 Sequential lithographic methods to reduce stacking fault nucleation sites and structures having reduced stacking fault nucleation sites WO2005095679A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
EP05760477A EP1726037B1 (en) 2004-03-18 2005-02-14 Sequential lithographic methods to reduce stacking fault nucleation sites and structures having reduced stacking fault nucleation sites
DE602005020911T DE602005020911D1 (en) 2004-03-18 2005-02-14 SEQUENTIAL LITHOGRAPHIC PROCEDURES FOR REDUCING STACKING ERROR NUCLEATION SITES AND STRUCTURES WITH REDUCED STACKING ERROR NUCLEATION SITES
AT05760477T ATE466377T1 (en) 2004-03-18 2005-02-14 SEQUENTIAL LITHOGRAPHIC METHODS FOR REDUCING STACKING DEFECT NUCLATION SITES AND STRUCTURES WITH REDUCED STACKING DEFECT NUCLATION SITES
CA002554815A CA2554815A1 (en) 2004-03-18 2005-02-14 Sequential lithographic methods to reduce stacking fault nucleation sites and structures having reduced stacking fault nucleation sites
JP2007503907A JP5014117B2 (en) 2004-03-18 2005-02-14 Sequential lithography method for reducing stacking fault nucleation sites and structure with reduced stacking fault nucleation sites
KR1020067019094A KR101074598B1 (en) 2004-03-18 2006-09-15 Sequential lithographic methods to reduce stacking fault nucleation sites and structures having reduced stacking fault nucleation sites

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US55412304P 2004-03-18 2004-03-18
US60/554,123 2004-03-18
US10/929,911 US7109521B2 (en) 2004-03-18 2004-08-30 Silicon carbide semiconductor structures including multiple epitaxial layers having sidewalls
US10/929,911 2004-08-30

Publications (2)

Publication Number Publication Date
WO2005095679A2 WO2005095679A2 (en) 2005-10-13
WO2005095679A3 true WO2005095679A3 (en) 2005-12-08

Family

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Application Number Title Priority Date Filing Date
PCT/US2005/004480 WO2005095679A2 (en) 2004-03-18 2005-02-14 Sequential lithographic methods to reduce stacking fault nucleation sites and structures having reduced stacking fault nucleation sites

Country Status (9)

Country Link
US (2) US7109521B2 (en)
EP (1) EP1726037B1 (en)
JP (1) JP5014117B2 (en)
KR (1) KR101074598B1 (en)
AT (1) ATE466377T1 (en)
CA (1) CA2554815A1 (en)
DE (1) DE602005020911D1 (en)
TW (1) TW200601412A (en)
WO (1) WO2005095679A2 (en)

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