WO2005089450A2

WO2005089450A2 - Organic semiconductor devices and methods

Info

Publication number: WO2005089450A2
Application number: PCT/US2005/008988
Authority: WO
Inventors: Victoria Soghomonian; Jean J. Heremans; Jungyol Jo
Original assignee: Ohio University
Priority date: 2004-03-19
Filing date: 2005-03-18
Publication date: 2005-09-29
Also published as: WO2005089450A3

Abstract

Semiconductor devices, methods of making semiconductor devices, and methods of operating semiconductor devices. The semiconductor devices have a first contact and a second contact. An electric field at the first contact is different from an electric field at the second contact. The devices can be operated to display n-type or p-type behavior.

Description

ORGANIC SEMICONDUCTOR DEVICES AND METHODS

This invention was partially supported by a Federal Grant from the National Science Foundation Grant Number 0103034. The government has certain rights in this invention.

CROSS REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Application Ser. No. 60/554,685 filed March 19, 2004, which is incorporated by reference in its entirety herein.

FIELD OF THE INVENTION The present invention relates to devices and methods of making devices that incorporate organic semiconductors. More particularly, the present invention relates to transistors incorporating organic semiconductors that exhibit ambipolar behavior.

BACKGROUND

Organic semiconductors have been included in a variety of semiconductor devices. Such devices may be inexpensive, lightweight, rugged, and/or flexible. For example, organic circuits may be inexpensively printed on a flexible substrate. However, many organic semiconductor devices and fabrication methods may not exhibit all desired qualities such as cost effectiveness, suitable performance characteristics, or type (n- or p-type).

Thus, there remains a need in the art for additional organic semiconductor devices and methods of making such devices.

SUMMARY OF THE INVENTION

In accordance with embodiments of the present invention, semiconductor devices are provided. The devices comprise a first contact, a second contact, a gate, and an organic semiconductor. An electric field at the first contact resulting from respective voltages applied to the gate, the first contact, and the second contact does not equal an electric field at the second contact resulting from the respective voltages applied to the gate, the first contact, and the second contact.

In accordance with further embodiments of the present invention, methods of making semiconductor devices are provided. The methods comprise providing at least one gate; forming an insulating layer proximate to the gate; forming a first contact and a second contact proximate the insulating layer; and providing an organic semiconductor suc_h that charge carriers can flow through the organic semiconductor between the first contact and the second contact. An electric field at the first contact resulting from respective voltages applied to the gate, the first contact, and the second contact does not equal an electric fielcl at the second contact resulting from the respective voltages applied to the gate, the first contact, and the second contact

In accordance with embodiments of the present invention, methods of operating a semiconductor device having a first contact, a second contact, at least one gate, and at least one organic semiconductor, wherein the semiconductor device is disposed such that an electric field at the first contact resulting from respective voltages applied to the gate, the first contact, and the second contact does not equal an electric field at the second contact resulting from the respective voltages applied to the gate, the first contact, and the second contact, comprise: applying a first voltage to the first contact; applying a second vol-tage to the second contact; and applying a gate voltage to the at least one gate such that charge carriers flow between said first and second contacts. The type of charge carrier is select&d by applying a first voltage that is alternatively more positive or more negative than the second voltage.

The above summary of the present invention is not intended to describe each disclosed embodiment or every implementation of the present invention. Ttie Figures and the detailed description which follow more particularly exemplify these embodiments.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DI AWINGS

The following detailed description of embodiments of the invention can be best understood when read in conjunction with the following drawings, where lit e structure is indicated with like reference numerals and in which:

Fig. 1 illustrates a semiconductor device in accordance with embodiments of the present invention;

Fig. 2 illustrates a semiconductor device in accordance with other embodiments of the present invention;

Figs. 3 A-3D illustrate possible configurations for complementary metal-oxide semiconductor devices in accordance with embodiments of the present invention.

Figs. 4A-4B are plots of the current- voltage characteristics of semiconductor devices in accordance with embodiments of the present invention. DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

The present invention will now be described with occasional reference to the specific embodiments of the invention. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for describing particular embodiments only and is not intended to be limiting of the invention. As used in the description of the invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety.

In accordance with an embodiment of the present invention, semiconductor devices and methods of making semiconductor devices are provided. Referring to Fig. 1, a semiconductor device 10 has a gate 16, a layer 18 over the gate, and a first contact 12, and a second contact 14 disposed on the layer 18. Additionally, an organic semiconductor 20 may be disposed at least between the first contact 12 and the second contact 14 as shown. Alternatively, the first and second contacts may be disposed on top of the organic semiconductor (not shown). The semiconductor device 10 is disposed such that an electric field El (not shown) at the first contact 12 resulting from respective voltages applied to the gate 16, the first contact 12 and the second contact 14, does not equal the electric field E2 (not shown) at the second contact 14 resulting from the voltages applied to the gate 16, the first contact 12 and the second contact 14.

The gate 16 may be formed in any suitable manner using any suitable material. For example, the gate 16 may comprise a silicon or a metal gate. The layer 18 may comprise any suitable layer, and the layer 18 may comprise any etchable material. For purposes of defining and describing the present invention, the term "etchable material" shall be understood as referring to any material that may be etched using a suitable wet or dry etching method. The layer 18 may comprise an insulating layer. For example, the layer 18 may be, but is not limited to, silicon oxide, polydimethylsiloxane, and polyimide. The organic semiconductor 20 may be any suitable organic semiconductor and derivatives thereof. For example, the organic semiconductor 20 may be, but is not limited to, pentacene, tetracene, sexithiophene, and 3,4,9, 10-perylenetetracarboxylic dianhydride. The organic semiconductor 20 may be formed in any suitable manner. For example, the organic semiconductor 20 may be formed by evaporation. The device 10 may be fabricated such that the organic semiconductor 20 is an amorphous, microcrystalline or crystalline semiconductor. For purposes of defining and describing the present invention, "microcrystalline" shall be understood as referring to a material having more than one grain per channel length. Alternatively, the device 10 may be fabricated such that the organic semiconductor 20 is a crystalline semiconductor. For purposes of defining and describing the present invention, "crystalline" shall be understood as referring to a material where the channel is comprised entirely of one grain.

The first and second contacts 12, 14 may comprise any suitable conductive contact. For example, the first and second 12, 14, contacts may be, but are not limited to, gold (Au), palladium (Pd), platinum (Pt), calcium (Ca), magnesium (Mg), lithium (Li) contacts, or combinations thereof. Furthermore, the conductive contacts may incorporate or be surface treated with other materials such as, but not limited to, lithium fluoride (LiF), carbon (C), alkane or arene thiol self-assembled monolayers that modify their electron or hole injection properties. For example, the first and second contacts 12, 14 may be Au contacts treated wLth LiF in order to provide contacts that preferentially inject electrons. It will be understood that the first contact 12 and the second contact 14 may be fabricated from the same contact material or from different contact materials. Additionally, the first and second contacts 12, 14 may be formed in any suitable manner. For example, the first and second contacts 12, 1<4, may be formed by evaporating Au at an oblique angle with respect to the semiconductor device 10.

The semiconductor device 10 maybe operated as a transistor by utilizing the first and second contacts 12, 14 as the source or drain of the transistor. When the semiconductor device is operated as a transistor, charge carriers may flow between the source and the drain in the channel 22 between the first contact 12 and the second contact 14. As discussed above, the semiconductor device 10 is disposed such that an electric field El (not shown) at the first contact 12 from voltages applied to the gate 16, the first contact 12 and the second contact 4, does not equal the electric field E2 (not shown) at the second contact 14 from voltages applied to the gate 16, the first contact 12 and the second contact 14. In the device illustrated in Fig. 1, the first contact 12 is located further from the gate 16 than the second contact 14. Thus, dl is greater than d2. Generally, the electric field at a point distant from an applied voltage may be described as V/distance from applied voltage. Because dl is greatex than d2, the portion of the electric field El from a voltage applied to the gate at the first contact 12 is smaller than the portion of the electric field E2 from a voltage applied to the gate at the second contact 14. Additionally, the portion of the electric field El at the first contact 12 from a voltage applied to the second contact generally does not equal the portion of the electric field E2 at the second contact 14 from a voltage applied to the first contact 12. For example, the voltage applied to the first contact 12 may be different than the voltage applied to the second contact 14.

The contact 12 or 14 with the higher electric field strength may act as the dominant carrier injector, and the injected carrier type may be controlled by the applied drain— source voltage and the applied gate-source voltage. It will be understood that the contact ttiat is kept at ground and the contact with respect to which the other voltages are defined, is called the source. When a negative voltage is applied to the second contact 14 with respect to the first contact 12 which is now the source, the device 10 displays n-type behavior because the second contact 14 injects electrons into the channel 22. When a negative voltage is applied to the first contact 12 with respect to the second contact 14, which is now the source, the device 10 displays p-type behavior because the second contact 14 injects holes into the channel 22. Therefore the device 10 may display ambipolar (n-type or p-type) behavior depending on how the device is operated. For example, the contact with higher electric field strength may be a dominant carrier injector, and the injected carrier type can be controlled by the applied drain-source voltage. When a negative voltage is applied to the strong field contact, the device may display n-type behavior. When a positive voltage is applied to the stro g field contact, the device may display p-type behavior. In the devices of the present invention, it is not necessary to provide differently doped semiconductor material in order to provide an n- type or p-type device. Instead, n-type or p-type behavior may be selected by changing which contact operates as the source or drain.

The device 10 may be fabricated and operated such that the ratio of E2/E1 is at least about 1.2 to about 5. In a further example, the device 10 may be fabricated and operated such that the ratio of E2/E1 is at least about 1.5 to about 2. Additionally, the device 10 may be fabricated such that the channel 22 has a length L from the first contact 12 to the second contact 14, and the length L may be up to about 5 μm. In a further example, length. L may be up to about 2 μm. In still a further example, the length L may be up to about 1.5 μm. In another example, the length L may be less than about 1 μm. In another example, the channel lengths may be less than about to 0.5 μm. For example, the layer 18 may have a step etched therein as shown in Fig.l, and the edge of the step may be used as a shadow mask to ensure a distance L between the first contact 12 and the second contact 14.

Referring to Fig. 2, a semiconductor device 10 and a methods of making a semiconductor device 10 having an alternative configuration in accordance with another embodiment of the present invention are provided. The semiconductor device 10 comprises a layer 18 having a first gate 24 and a second gate 26 under the layer 18. An organic semiconductor 20 may be disposed proximate to the layer 18, and first 12 and second 14 contacts are disposed proximate to the organic semiconductor 20 as shown. Alternatively, first and second contacts may also de disposed proximate to the layer and the organic semiconductor may be disposed between first and second contacts (not shown). The semiconductor device 10 is operated such that an electric field El (not shown) at the first contact 12 resulting from respective voltages applied to the first gate 24, the first contact 12 and the second contact 14 does not equal the electric field E2 (not shown) at the second contact 14 resulting from respective voltages applied to the second gate 26, the first contact 12 and the second contact 14.

The semiconductor device 10 may be operated as a transistor by utilizing the first and second contacts 12, 14 as the source or drain of the transistor. When the semiconductor device is operated as a transistor, charge carriers may flow between the source and the drain in the channel 22 between the first contact 12 and the second contact 14. As discussed above, the semiconductor device 10 is operated such that an electric field El (not shown) at the first contact 12 from voltages applied to the first gate 24, the first contact 12 and the second contact 14 does not equal the electric field E2 (not shown) at the second contact 14 from voltages applied to the second gate 26, the first contact 12 and the second contact 14. The difference in the electric fields may be achieved by applying a first voltage to the first gate 24 and a second voltage to the second gate 26. The first voltage generally does not equal the second voltage. As discussed above, the electric field at a point distance from an applied voltage may be described as V/distance from the applied voltage. Thus, the first and second gates 24, 26 may be operated such that the electric field El at the first contact 12 is larger than the electric field E2 at the second contact 14. Alternatively, the first and second gates 24, 26 may be operated such that the electric field El at the first contact is smaller than the electric field E2 at the second contact 14. Additionally, different voltages may be applied to the first contact 12 and the second contact 14 such that the portions of the electric fields El and E2 at the first contact 12 or the second contact 14 from voltages applied to the first contact 12 and the second contact 14 are different.

The device 10 may be operated such that the first contact 12 is either the source or the drain, and the second contact 14 is either the drain or the source. When the device 10 is operated such that a negative voltage is applied to contact 14 acting as the drain with respect to contact 12 acting as the source and contact 14 has the higher electric field strength, the device 10 may display n-type behavior. When the device 10 is operated such that a negative voltage is applied to contact 12 acting as the drain with respect to contact 14 acting as the source and contact 14 has the higher electric field strength, the device 10 may display p-type behavior. Therefore, the device 10 may display ambipolar behavior depending on how the device is operated.

It will be understood that the device 10 may be fabricated using the materials and methods described in conjunction with the device of Fig. 1. For example, the device 10 may be fabricated such that channel 22 has a length from the first contact 12 to the second contact 14, and the length may be up to about 5 μm. In a further example, length may be up to about 2 μm. In still a further example, the length may be up to about 1.5 μm. In another example, the length may be less than about 1 μm. In another example, the channel lengths may be less than about 0.5 μm. The device 10 may be operated such that the ratio of E2/E1 is at least about 1.2 to about 5. Alternatively, the device 10 may be operated such that the ratio of E2/E1 is at least about 1.5 to 2.

It will be understood that the semiconductor devices and methods of the present invention may be used to form any number of devices. For example, at least one pair of the semiconductor devices could be operated in a complementary manner to form a complementary metal-oxide-semiconductor circuits. Thus, one of the semiconductor devices could be operated so that the device displays n-type behavior and one of the semiconductor devices could be operated so that the device displays p-type behavior. In another example, the semiconductor devices could be incorporated into devices comprising lasers or light- emitting diodes. In yet another example, the semiconductor devices could be used to provide a passive load in a circuit incorporating a transistor. Because the semiconductor devices of the present invention may exhibit short channel lengths, this device geometry may be utilized to realize organic transistors operating at high frequencies. In a further example referring to Figs. 3A-3D, the devices of the present invention may be used to form complementary metal-oxide semiconductor CMOS circuits. Referring to Fig. 3 A, a p-type transistor 10a having a gate 16 and first and second contacts 12, 14 may be fabricated as discussed above. For example, the first and second contacts 12, 14 may comprise Au. The transistor 10a may be operated such that the second contact 14 has a positive voltage applied thereto, and the transistor 10a may display p-type behavior. Referring to Fig. 3B, a n-type transistor 10b having a gate 16 and first and second contacts 12a and 14a may be fabricated as discussed above. For example, the first and second contacts 12a, 14a may comprise Au having a LiF layer over the Au. The contacts 12a, 14a having a LiF layer may act as electron injecting contacts. The second contact 14a may have a negative voltage applied thereto, and the transistor 10b may display n-type behavior.

Referring to Fig. 3C, the transistors 10a and 10b may be fabricated in desired locations by choosing an appropriate metal contact type at a desired location as illustrated schematically. The transistors 10a and 10b may be connected by metallization in a desired manner to produce a CMOS circuit, as illustrated in Fig. 3D.

Unless otherwise indicated, all numbers expressing quantities of ingredients, properties such as molecular weight, reaction and deposition conditions, and so forth as used in the specification and claims are to be understood as being modified in all instances by the term "about." Accordingly, unless otherwise indicated, the numerical properties set forth in the following specification and claims are approximations that may vary depending on the desired properties sought to be obtained in embodiments of the present invention. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical values, however, inherently contain certain errors necessarily resulting from error found in their respective measurements.

EXAMPLE

A submicron pentacene field effect transistor having a structure similar to that shown in Fig. 1 was fabricated. A p-type silicon wafer with 4500 A-thick oxide, was used as the starting material. Part of the oxide was etched off in buffered oxide etchant to achieve a 2500 A tall oxide step. Submicron spacing between drain and source was realized by evaporating Au at a 65 degree angle on the oxide step. The oxide step served as a shadow mask to fabricate the channel. After the tilted Au deposition, pentacene was deposited to a thickness of 1500 A in a 10^" torr vacuum chamber at a substrate temperature of 37-40 °C. Prior to pentacene deposition, the wafer was primed with octadecyltrichlorosilane (OTS) vapor. Conventional pentacene OFET structures of 15 μm channel length fabricated on 4500 A thick flat oxide by our procedure showed about 0.25 cmVVs mobility, at -80 V gate voltage. In the step, the highly doped p-type Si substrate serves as gate metal, and the remaining oxide as gate insulator.

In Fig. 4A, the lower Au contact was operated as the drain. At low drain voltages (~ —5 V), the drain current increases under negative gate voltages, as expected in a p-type transistor. When drain voltage increases to — 12 V and higher, positive gate voltages lead to the largest drain currents as expected from n-type transistors. In Fig. 4B, the drain and source contacts are interchanged, and the OFET displays p-type behavior for all drain voltages.

It will be obvious to those skilled in the art that various changes may be made without departing from the scope of the invention, which is not to be considered limited to what is described in the specification. The present invention should not be considered limited to the specific examples described above, but rather should be understood to cover all aspects of the invention. Various modifications, equivalent processes, as well as numerous structures and devices to which the present invention may be applicable will be readily apparent to those of skill in the art.

What is claimed is:

Claims

1. A semiconductor device, comprising: a first contact; a second contact; a gate; and an organic semiconductor, wherein an electric field at the first contact resulting from respective voltages applied to the gate, the first contact, and the second contact does not equal an electric field at the second contact resulting from the respective voltages applied to the gate, the first contact, and the second contact.

2. The semiconductor device as claimed in claim 1 wherein the ratio of the electric field at the second contact to the electric field at the first contact is at least about 1.2 to about 5.

3. The semiconductor device as claimed in claim 1 wherein the ratio of the electric field at the first contact to the electric field at the second contact is at least about 1.2 to about 5.

4. The semiconductor device as claimed in claim 1 wherein the distance between the first contact and the second contact is less than about 5 μm.

5. The semiconductor device as claimed in claim 1 wherein the distance between the first contact and the second contact is between about 0.5 μm to about 2 μm.

6. The semiconductor device as claimed in claim 1 wherein at least one type of charge carrier flows through the organic semiconductor between the first contact and the second contact when respective voltages are applied to the at least one gate and at least one of the first and second contacts.

7. The semiconductor device as claimed in claim 6 wherein the electric field at the first contact is greater than the electric field at the second contact.

8. The semiconductor device as claimed in claim 7 wherein the at least one type of charge carrier comprises an n-type charge carrier when a negative voltage is applied to the first contact with respect to the second contact.

9. The semiconductor device as claimed in claim 7 wherein the at least one type of charge carrier comprises a p-type charge carrier when a negative voltage is applied to the second contact with respect the first contact.

10. The semiconductor device as claimed in claim 6 wherein the electric field at the first contact is smaller than the electric field at the second contact.

11. The semiconductor device as claimed in claim 10 wherein the at least one type of charge carrier comprises a p-type charge carrier when a negative voltage is applied to the first contact with respect to the second contact.

12. The semiconductor device as claimed in claim 10 wherein the at least one type of charge carrier comprises an n-type charge carrier when a negative voltage is applied to the second contact with respect to the first contact.

13. The semiconductor device as claimed in claim 1 wherein the organic semiconductor is selected from amorphous, microcrystalline, and crystalline semiconductors.

14. The semiconductor device as claimed in claim 1 wherein the first contact is disposed a first distance from the at least one gate, the second contact is disposed a second distance from the at least one gate, and the first distance is greater than the second distance.

15. The semiconductor device as claimed in claim 14 wherein the gate comprises a gate material, and wherein an insulating layer is disposed between the gate material and the first and second contacts.

16. The semiconductor device as claimed in claim 15 wherein the organic semiconductor is disposed at least between the first contact and the second contact.

17. The semiconductor device as claimed in claim 1 comprising a first gate and a second gate.

18. The semiconductor device as claimed in claim 17 wherein the first gate is disposed such that a portion of the first gate is disposed under at least a portion of the second gate.

19. The semiconductor device as claimed in claim 18 wherein the first and second gates are disposed on an insulating layer, and wherein the insulating layer is disposed on the organic semiconductor.

20. The semiconductor device as claimed in claim 17 wherein the electric field at the first contact from voltages applied to the first gate does not equal the electric field at the second contact from voltages applied to the second gate.

21. The semiconductor device as claimed in 20 wherein the voltage applied to the first gate is different from the voltage applied to the second gate.

22. The semiconductor device as claimed in claim 21 wherein the electric field at the first contact is larger than the electric field at the second contact.

23. The semiconductor device as claimed in claim 22 wherein the at least one type of charge carrier comprises an n-type charge carrier when a negative voltage is applied to the first contact with respect to the second contact.

24. The semiconductor device as claimed in claim 22 wherein the at least one type of charge carrier comprises a p-type charge carrier when a negative voltage is applied to the second contact with respect the first contact.

25. The semiconductor device as claimed in claim 21 wherein the electric field at the first contact is smaller than the electric field at the second contact.

26. The semiconductor device as claimed in claim 25 wherein the at least one type of charge carrier comprises a p-type charge carrier when a negative voltage is applied to the first contact with respect to the second contact.

27. The semiconductor device as claimed in claim 25 wherein the at least one type of charge carrier comprises an n-type charge carrier when a negative voltage is applied to the second contact with respect to the first contact.

28. The semiconductor device as claimed in claim 1 further comprising a plurality of said semiconductor devices connected in circuit communication to form a memory device.

29. A method of making a semiconductor device comprising: providing at least one gate; fonning an insulating layer proximate to the gate; forming a first contact and a second contact proximate the insulating layer; and providing an organic semiconductor such that charge carriers can flow through the organic semiconductor between the first contact and the second contact, wherein an electric field at the first contact resulting from respective voltages applied to the gate, the first contact, and the second contact does not equal an electric field at the second contact resulting from the respective voltages applied to the gate, the first contact, and the second contact

30. The method as claimed in claim 29 further comprising etching the insulating layer such that a first surface of the insulating layer is a first distance from the gate and such that a second surface of the insulating layer is a second distance from the gate, wherein the first distance is greater than the second distance; subsequently forming a first contact proximate to the first surface of the insulating layer; subsequently forming a second contact proximate to the second surface of the insulating layer.

31. The method as claimed in claim 29 further comprising forming a first gate and a second gate such that a portion of the first gate is disposed under at least a portion of the second gate, wherein an electric field at the first contact from a voltage applied to the first gate does not equal an electric field at the second contact from a voltage applied to the second gate.

32. The method as claimed in claim 29 comprising forming a plurality of the semiconductor devices.

33. A method of operating a semiconductor device having a first contact, a second contact, at least one gate, and at least one organic semiconductor, wherein the semiconductor device is disposed such that an electric field at the first contact resulting from respective voltages applied to the gate, the first contact, and the second contact does not equal an electric field at the second contact resulting from the respective voltages applied to the gate, the first contact, and the second contact, comprising: applying a first voltage to the first contact; applying a second voltage to the second contact; and applying a gate voltage to the at least one gate such that charge carriers flow between said first and second contacts, wherein the type of charge carrier is selected by applying a first voltage that is alternatively more positive or more negative than the second voltage.

34. The method as claimed in claim 33 wherein the step of applying a first voltage to the first contact comprises applying a first voltage that is more negative than the second voltage, and wherein the charge carriers comprise n-type charge carriers.

35. The method as claimed in claim 33 wherein the step of applying a first voltage to the first contact comprises applying a first voltage that is more positive than the second voltage, and wherein the charge carriers comprise p-type charge carriers.