WO2005050444A3 - An apparatus and method for automatically parallelizing network applications through pipelining transformation - Google Patents

An apparatus and method for automatically parallelizing network applications through pipelining transformation Download PDF

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Publication number
WO2005050444A3
WO2005050444A3 PCT/US2004/037160 US2004037160W WO2005050444A3 WO 2005050444 A3 WO2005050444 A3 WO 2005050444A3 US 2004037160 W US2004037160 W US 2004037160W WO 2005050444 A3 WO2005050444 A3 WO 2005050444A3
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WO
WIPO (PCT)
Prior art keywords
pipeline
transformation
sequential
network applications
network
Prior art date
Application number
PCT/US2004/037160
Other languages
French (fr)
Other versions
WO2005050444A2 (en
Inventor
Jinquan Dai
William Harrison Iii
Bo Huang
Cotton Seed
Long Li
Original Assignee
Intel Corp
Jinquan Dai
William Harrison Iii
Bo Huang
Cotton Seed
Long Li
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Jinquan Dai, William Harrison Iii, Bo Huang, Cotton Seed, Long Li filed Critical Intel Corp
Priority to JP2006539703A priority Critical patent/JP4664923B2/en
Priority to CN2004800404781A priority patent/CN1906579B/en
Priority to EP04810518A priority patent/EP1685483B1/en
Priority to DE602004018023T priority patent/DE602004018023D1/en
Publication of WO2005050444A2 publication Critical patent/WO2005050444A2/en
Publication of WO2005050444A3 publication Critical patent/WO2005050444A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/456—Parallelism detection

Abstract

In some embodiments, a method and apparatus for automatically parallelizing a sequential network application through pipeline transformation are described. In one embodiment, the method includes the configuration of a network processor into a D-stage processor pipeline. Once configured, a sequential network application program is transformed into D-pipeline stages. Once transformed, the D-pipeline stages are executed in parallel within the D-stage processor pipeline. In one embodiment, transformation of a sequential application program is performed by modeling the sequential network program as a flow network model and selecting from the flow network model into a plurality of preliminary pipeline stages. Other embodiments are described and claimed.
PCT/US2004/037160 2003-11-14 2004-11-05 An apparatus and method for automatically parallelizing network applications through pipelining transformation WO2005050444A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2006539703A JP4664923B2 (en) 2003-11-14 2004-11-05 Apparatus and method for automatically parallelizing network applications through pipeline transformation
CN2004800404781A CN1906579B (en) 2003-11-14 2004-11-05 Apparatus and method for automatically parallelizing network applications through pipelining transformation
EP04810518A EP1685483B1 (en) 2003-11-14 2004-11-05 An apparatus and method for automatically parallelising network applications through pipelining transformation
DE602004018023T DE602004018023D1 (en) 2003-11-14 2004-11-05 DEVICE AND METHOD FOR AUTOMATIC PARALLELIZING NETWORK APPLICATIONS THROUGH PIPELINE TRANSFORMATION

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/714,465 US7793276B2 (en) 2003-11-14 2003-11-14 Apparatus and method for automatically parallelizing network applications through pipelining transformation
US10/714,465 2003-11-14

Publications (2)

Publication Number Publication Date
WO2005050444A2 WO2005050444A2 (en) 2005-06-02
WO2005050444A3 true WO2005050444A3 (en) 2005-09-15

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PCT/US2004/037160 WO2005050444A2 (en) 2003-11-14 2004-11-05 An apparatus and method for automatically parallelizing network applications through pipelining transformation

Country Status (7)

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US (2) US7793276B2 (en)
EP (1) EP1685483B1 (en)
JP (1) JP4664923B2 (en)
CN (1) CN1906579B (en)
AT (1) ATE415655T1 (en)
DE (1) DE602004018023D1 (en)
WO (1) WO2005050444A2 (en)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7793276B2 (en) * 2003-11-14 2010-09-07 Intel Corporation Apparatus and method for automatically parallelizing network applications through pipelining transformation
US8856401B2 (en) * 2003-11-25 2014-10-07 Lsi Corporation Universal controller for peripheral devices in a computing system
US7693690B2 (en) * 2005-08-09 2010-04-06 Nec Laboratories America, Inc. Disjunctive image computation for sequential systems
US7774769B2 (en) * 2005-09-22 2010-08-10 Intel Corporation Transmitting trace-specific information in a transformed application
WO2007056893A1 (en) * 2005-11-18 2007-05-24 Intel Corporation Latency hiding of traces using block coloring
US8453131B2 (en) * 2005-12-24 2013-05-28 Intel Corporation Method and apparatus for ordering code based on critical sections
US20070237146A1 (en) * 2006-03-31 2007-10-11 Ilija Hadzic Methods and apparatus for modeling and synthesizing packet processing pipelines
US8037466B2 (en) 2006-12-29 2011-10-11 Intel Corporation Method and apparatus for merging critical sections
US20090201817A1 (en) * 2008-02-08 2009-08-13 International Business Machines Corporation Method of optimizing a flow of value in a network
EP2257873A4 (en) * 2008-02-12 2013-05-15 Scrutiny Inc Systems and methods for information flow analysis
EP2359237A4 (en) * 2008-11-28 2012-04-25 Siemens Ag Automatic control system and method for executing control program in parallel
EP2361408A4 (en) 2008-12-01 2012-05-23 Kpit Cummins Infosystems Ltd Method and system for parallelization of sequencial computer program codes
US8239866B2 (en) * 2009-04-24 2012-08-07 Microsoft Corporation Reduction of memory latencies using fine grained parallelism and FIFO data structures
US8566801B2 (en) * 2009-05-22 2013-10-22 International Business Machines Corporation Concurrent static single assignment for general barrier synchronized parallel programs
US8448155B2 (en) * 2009-06-01 2013-05-21 National Instruments Corporation Automatically creating parallel iterative program code in a graphical data flow program
JP4931978B2 (en) * 2009-10-06 2012-05-16 インターナショナル・ビジネス・マシーンズ・コーポレーション Parallelization processing method, system, and program
JP4886838B2 (en) * 2009-10-30 2012-02-29 インターナショナル・ビジネス・マシーンズ・コーポレーション Parallelization method, system, and program
US8276148B2 (en) 2009-12-04 2012-09-25 International Business Machines Corporation Continuous optimization of archive management scheduling by use of integrated content-resource analytic model
CN101876899B (en) * 2009-12-18 2014-06-25 北京北大众志微系统科技有限责任公司 Method and system for optimizing computer program
JP5479942B2 (en) * 2010-02-22 2014-04-23 インターナショナル・ビジネス・マシーンズ・コーポレーション Parallelization method, system, and program
US8868470B2 (en) * 2010-11-09 2014-10-21 Microsoft Corporation Parallel processing of data sets
WO2013010159A1 (en) * 2011-07-14 2013-01-17 Siemens Corporation Reducing the scan cycle time of control applications through multi-core execution of user programs
US20130138473A1 (en) * 2011-11-28 2013-05-30 Sap Ag Business Process Optimization
US20130139164A1 (en) * 2011-11-28 2013-05-30 Sap Ag Business Process Optimization
CN105573717B (en) * 2014-10-08 2018-02-06 华为技术有限公司 A kind of procedure division method and device of multi-core processor oriented
US9747089B2 (en) * 2014-10-21 2017-08-29 International Business Machines Corporation Automatic conversion of sequential array-based programs to parallel map-reduce programs
US9836568B1 (en) * 2016-03-14 2017-12-05 Xilinx, Inc. Programmable integrated circuit design flow using timing-driven pipeline analysis
US10509634B2 (en) * 2016-03-30 2019-12-17 International Business Machines Corporation Data flow analysis for dynamic application, skipping views
US10785107B2 (en) * 2018-05-16 2020-09-22 Microsoft Technology Licensing, Llc Method and apparatus for optimizing legacy network infrastructure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6651246B1 (en) * 1999-11-08 2003-11-18 International Business Machines Corporation Loop allocation for optimizing compilers

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0644209A (en) * 1992-07-27 1994-02-18 Toshiba Corp Parallel simulation model division determining device
JPH09106351A (en) * 1995-10-12 1997-04-22 Hitachi Ltd Variable renaming method
US6223337B1 (en) * 1997-12-12 2001-04-24 Hewlett-Packard Company Random test generation for compiler optimization
US7233998B2 (en) * 2001-03-22 2007-06-19 Sony Computer Entertainment Inc. Computer architecture and software cells for broadband networks
US7793276B2 (en) * 2003-11-14 2010-09-07 Intel Corporation Apparatus and method for automatically parallelizing network applications through pipelining transformation
US7581214B2 (en) * 2004-04-15 2009-08-25 Intel Corporation Live set transmission in pipelining applications
WO2007068148A1 (en) * 2005-12-17 2007-06-21 Intel Corporation Method and apparatus for partitioning programs to balance memory latency
US8261249B2 (en) * 2008-01-08 2012-09-04 International Business Machines Corporation Distributed schemes for deploying an application in a large parallel system
US8122441B2 (en) * 2008-06-24 2012-02-21 International Business Machines Corporation Sharing compiler optimizations in a multi-node system
US8214814B2 (en) * 2008-06-24 2012-07-03 International Business Machines Corporation Sharing compiler optimizations in a multi-node system
JP5479942B2 (en) * 2010-02-22 2014-04-23 インターナショナル・ビジネス・マシーンズ・コーポレーション Parallelization method, system, and program

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6651246B1 (en) * 1999-11-08 2003-11-18 International Business Machines Corporation Loop allocation for optimizing compilers

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
DALER N. RAKHMATOV AND SARMA B.K. VRUDHULA: "Hardware-Software Partitioning for Dynamically Reconfigurable Systems", PROCEEDINGS OF THE TENTH INTERNATIONAL SYMPOSIUM ON HARDWARE/SOFTWARE CODESIGN. CODES 2002 6-8 MAY 2002 ESTES PARK, CO, USA, May 2002 (2002-05-01), Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627) ACM New York, NY, USA, pages 145 - 150, XP002333778, ISBN: 1-58113-542-4 *
HONGHUA YANG AND D.F. WONG: "Efficient Network Flow Based Min-Cut Balanced Partitioning", PROCEEDINGS OF 1994 IEEE INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN (CAD-94) 6-10 NOV. 1994 SAN JOSE, CA, USA, November 1994 (1994-11-01), 1994 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.94CH3455-3) ACM New York, NY, USA, pages 50 - 55, XP010252276, ISBN: 0-89791-690-5 *
HUIQUN LIU ET AL: "Network flow based circuit partitioning for time-multiplexed FPGAs", 1998 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN. DIGEST OF TECHNICAL PAPERS (IEEE CAT. NO.98CB36287) ACM NEW YORK, NY, USA, 1998, pages 497 - 504, XP002333779, ISBN: 1-58113-008-2 *
INTEL: "Introduction to the Auto-Partitioning Programming Model", WHITE PAPER, October 2003 (2003-10-01), pages 1 - 10, XP002333777, Retrieved from the Internet <URL:www.intel.com/design/network/papers/25411401.pdf> [retrieved on 20050621] *
JINQUAN DAI, BO HUANG, LONG LI ND LUDDY HARRISON: "Automatically Partitioning Packet Processing Applications for Pipelined Architectures", PROCEEDINGS OF THE ACM SIGPLAN 2005 CONFERENCE ON PROGRAMMING LANGUAGE DESIGN AND IMPLEMENTATION, June 2005 (2005-06-01), pages 237 - 247, XP002333780 *
SRIDKHAR LAKSHMANAMURTHY, KIN-YIP LIU AND YIM PUN: "Network Processor Performance Analysis Methodology", INTEL TECHNOLOGY JOURNAL INTEL CORP USA, vol. 6, no. 3, 15 August 2002 (2002-08-15), pages 19 - 28, XP002333775, ISSN: 1535-864X *

Also Published As

Publication number Publication date
WO2005050444A2 (en) 2005-06-02
JP4664923B2 (en) 2011-04-06
DE602004018023D1 (en) 2009-01-08
US20100223605A1 (en) 2010-09-02
US20050108696A1 (en) 2005-05-19
EP1685483A2 (en) 2006-08-02
US8438552B2 (en) 2013-05-07
EP1685483B1 (en) 2008-11-26
JP2007511835A (en) 2007-05-10
CN1906579B (en) 2010-06-23
CN1906579A (en) 2007-01-31
ATE415655T1 (en) 2008-12-15
US7793276B2 (en) 2010-09-07

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