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Publication numberWO2005040917 A3
Publication typeApplication
Application numberPCT/US2004/028864
Publication date23 Feb 2006
Filing date7 Sep 2004
Priority date7 Oct 2003
Also published asUS7003758, US7111277, US7114145, US7117477, US7117478, US7120895, US7873937, US8209640, US8516405, US8893067, US20050076322, US20050091633, US20050097500, US20050120327, US20050122500, US20050166174, US20070022402, US20110083113, US20120269421, US20130332894, WO2005040917A2
Publication numberPCT/2004/28864, PCT/US/2004/028864, PCT/US/2004/28864, PCT/US/4/028864, PCT/US/4/28864, PCT/US2004/028864, PCT/US2004/28864, PCT/US2004028864, PCT/US200428864, PCT/US4/028864, PCT/US4/28864, PCT/US4028864, PCT/US428864, WO 2005/040917 A3, WO 2005040917 A3, WO 2005040917A3, WO-A3-2005040917, WO2005/040917A3, WO2005040917 A3, WO2005040917A3
InventorsJun Ye, Yen-Wen Lu, Yu Cao, Luoqi Chen, Xun Chen
ApplicantBrion Tech Inc, Jun Ye, Yen-Wen Lu, Yu Cao, Luoqi Chen, Xun Chen
Export CitationBiBTeX, EndNote, RefMan
External Links: Patentscope, Espacenet
System and method for lithography simulation
WO 2005040917 A3
Abstract
There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture (110), including application-specific hardware accelerators (116a… 116n), and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system (110) includes: general purpose-type computing device(s) (114a, 142a, 142b) to perform the case-based logic having branches and interdependency in the data handling and accelerator subsystems (146a1… 146ax, …, 146n1… 146nx) to perform a majority of the computation intensive tasks.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5594850 *25 Jan 199414 Jan 1997Hitachi, Ltd.Image simulation method
US5680588 *6 Jun 199521 Oct 1997International Business Machines CorporationMethod and system for optimizing illumination in an optical photolithography projection imaging system
US6285488 *2 Mar 19994 Sep 2001Micronic Laser Systems AbPattern generator for avoiding stitching errors
US6372391 *25 Sep 200016 Apr 2002The University Of HoustonTemplate mask lithography utilizing structured beam
US20030107770 *11 Jul 200112 Jun 2003Applied Materials, Inc.Algorithm for adjusting edges of grayscale pixel-map images
US20040022354 *30 May 20025 Feb 2004Kazuaki ShimizuMulti-layer film spectroscopic element for boron fluorescene x-ray analysis
Classifications
International ClassificationG03B27/54, G03F7/20, G06K9/00, G06F17/50, G03F, G06T7/00
Cooperative ClassificationG03F7/004, G03F1/00, G06F19/00, G21K5/00, G06F17/5081, G06F17/5009, G06F2217/12, G06F2217/14, G06T2207/30148, G06T7/0004, G03F7/70666, G03F7/705
European ClassificationG03F7/70L2B, G03F7/70L10L, G06T7/00B1
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