WO2005013143A3 - A single chip protocol converter - Google Patents

A single chip protocol converter Download PDF

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Publication number
WO2005013143A3
WO2005013143A3 PCT/US2004/023784 US2004023784W WO2005013143A3 WO 2005013143 A3 WO2005013143 A3 WO 2005013143A3 US 2004023784 W US2004023784 W US 2004023784W WO 2005013143 A3 WO2005013143 A3 WO 2005013143A3
Authority
WO
WIPO (PCT)
Prior art keywords
soc
core
protocol
chip
protocol conversion
Prior art date
Application number
PCT/US2004/023784
Other languages
French (fr)
Other versions
WO2005013143A2 (en
Inventor
Christos J Georgiou
Victor L Gregurick
Indira Nair
Valentina Salapura
Original Assignee
Christos J Georgiou
Victor L Gregurick
Indira Nair
Valentina Salapura
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/604,491 external-priority patent/US7353362B2/en
Application filed by Christos J Georgiou, Victor L Gregurick, Indira Nair, Valentina Salapura filed Critical Christos J Georgiou
Priority to EP04779028A priority Critical patent/EP1654669A2/en
Publication of WO2005013143A2 publication Critical patent/WO2005013143A2/en
Publication of WO2005013143A3 publication Critical patent/WO2005013143A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
    • G06F15/7832—Architectures of general purpose stored program computers comprising a single central processing unit without memory on one IC chip (single chip microprocessors)
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/109—Integrated on microchip, e.g. switch-on-chip
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/60—Software-defined switches
    • H04L49/602—Multilayer or multiprotocol switching, e.g. IP switching

Abstract

A System-on-Chip (SoC) component comprises a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory forming a processor cluster; and a switch fabric means connecting each processor within the cluster. The SoC core is capable of performing multi-threading operation processing for SoC devices when configured as a DSP, coprocessor, Hybrid ASIC, or network processing arrangements. The SoC core is configured as a single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within one core. The protocol converter chip is capable of being be implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within the SoC protocol conversion macro core without requiring the processing resources of a host system.
PCT/US2004/023784 2003-07-25 2004-07-23 A single chip protocol converter WO2005013143A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP04779028A EP1654669A2 (en) 2003-07-25 2004-07-23 A single chip protocol converter

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US10/604,491 US7353362B2 (en) 2003-07-25 2003-07-25 Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus
US10/604,491 2003-07-25
US10/768,828 2004-01-30
US10/768,828 US7412588B2 (en) 2003-07-25 2004-01-30 Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus

Publications (2)

Publication Number Publication Date
WO2005013143A2 WO2005013143A2 (en) 2005-02-10
WO2005013143A3 true WO2005013143A3 (en) 2005-06-30

Family

ID=34119193

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/023784 WO2005013143A2 (en) 2003-07-25 2004-07-23 A single chip protocol converter

Country Status (4)

Country Link
US (3) US7412588B2 (en)
EP (1) EP1654669A2 (en)
KR (2) KR100986006B1 (en)
WO (1) WO2005013143A2 (en)

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