WO2004104819A1 - 並列処理装置及び並列処理方法 - Google Patents
並列処理装置及び並列処理方法 Download PDFInfo
- Publication number
- WO2004104819A1 WO2004104819A1 PCT/JP2004/001526 JP2004001526W WO2004104819A1 WO 2004104819 A1 WO2004104819 A1 WO 2004104819A1 JP 2004001526 W JP2004001526 W JP 2004001526W WO 2004104819 A1 WO2004104819 A1 WO 2004104819A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- output
- circuit
- column
- row
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
- G06F7/5095—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators word-serial, i.e. with an accumulator-register
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V10/00—Arrangements for image or video recognition or understanding
- G06V10/10—Image acquisition
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V10/00—Arrangements for image or video recognition or understanding
- G06V10/20—Image preprocessing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V10/00—Arrangements for image or video recognition or understanding
- G06V10/70—Arrangements for image or video recognition or understanding using pattern recognition or machine learning
- G06V10/74—Image or video pattern matching; Proximity measures in feature spaces
- G06V10/75—Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video features; Coarse-fine approaches, e.g. multi-scale approaches; using context analysis; Selection of dictionaries
- G06V10/751—Comparing pixel values or logical combinations thereof, or feature values having positional relevance, e.g. template matching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V10/00—Arrangements for image or video recognition or understanding
- G06V10/94—Hardware or software architectures specially adapted for image or video understanding
- G06V10/955—Hardware or software architectures specially adapted for image or video understanding using specific electronic processors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/607—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters
Definitions
- the processing circuit 2302 outputs the above-described true when the reference irregularities recorded in advance match the detected irregularities, the cell shown in FIG.
- the shape of the surface (fingerprint) detected in the area where 2301 is arranged can be collated.
- the number of cells where true is output exceeds 80% of all cells, it is determined that the detected fingerprint shape matches the fingerprint data recorded in advance (authentication) it can.
- the sum of the reference irregularities of all cells is the fingerprint data.
- FIG. 16 is a configuration diagram showing a configuration example of the accumulation adder.
- the accumulation adder 110 adds the row addition results output in synchronization with the clock signal (CK) and the row adder 106 in synchronization with the clock signal (CK).
- the accumulation adder 110 outputs a signal within the set range (m 'row Xn' column). The total result (final result) of the processing results output from the processing circuit 102 of the cell 101 is output.
- the start address and the row range m by the row address signal generation circuit 1733 may be set in the row range setting section 172, and the end address and the row range m ′ may be set. It may be set.
- the row range setting unit 172 can be configured by a register circuit or the like that holds the set value indicating the above-described range.
- a row address signal generation circuit 173 can be configured by a logic circuit, a counter circuit, and the like.
- the polarity of the signal is determined in advance, the potential corresponding to “0” or “1”, that is, the ground potential or the power supply You may make it short-circuit to an electric potential.
- the polarity of the signal is not limited.
- the row adder 106 and the accumulation adder 110 of the parallel processing device shown in FIG. A row adder 106b, a carry adder 1601, a register 1602, and a CS adder 1603 may be used.
- the ll type adder 1101, the CS type adder 1401, and the carry type adder 1601 are the same as those shown in Figs. 12, 15, and 17.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04711019A EP1643356B1 (en) | 2003-05-23 | 2004-02-13 | Parallel processing device and parallel processing method |
US10/505,718 US7480785B2 (en) | 2003-05-23 | 2004-02-13 | Parallel processing device and parallel processing method |
JP2004567189A JP3788804B2 (ja) | 2003-05-23 | 2004-02-13 | 並列処理装置及び並列処理方法 |
DE602004024995T DE602004024995D1 (de) | 2003-05-23 | 2004-02-13 | Parallelverarbeitungseinrichtung und parallelverarbeitungsverfahren |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003-146723 | 2003-05-23 | ||
JP2003146723 | 2003-05-23 | ||
JP2003-271037 | 2003-07-04 | ||
JP2003271037 | 2003-07-04 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004104819A1 true WO2004104819A1 (ja) | 2004-12-02 |
Family
ID=33478989
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2004/001526 WO2004104819A1 (ja) | 2003-05-23 | 2004-02-13 | 並列処理装置及び並列処理方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7480785B2 (ja) |
EP (1) | EP1643356B1 (ja) |
JP (1) | JP3788804B2 (ja) |
DE (1) | DE602004024995D1 (ja) |
WO (1) | WO2004104819A1 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9348642B2 (en) | 2012-06-15 | 2016-05-24 | International Business Machines Corporation | Transaction begin/end instructions |
US9384004B2 (en) | 2012-06-15 | 2016-07-05 | International Business Machines Corporation | Randomized testing within transactional execution |
US20130339680A1 (en) | 2012-06-15 | 2013-12-19 | International Business Machines Corporation | Nontransactional store instruction |
US9448796B2 (en) | 2012-06-15 | 2016-09-20 | International Business Machines Corporation | Restricted instructions in transactional execution |
US9436477B2 (en) | 2012-06-15 | 2016-09-06 | International Business Machines Corporation | Transaction abort instruction |
US9740549B2 (en) | 2012-06-15 | 2017-08-22 | International Business Machines Corporation | Facilitating transaction completion subsequent to repeated aborts of the transaction |
US10437602B2 (en) | 2012-06-15 | 2019-10-08 | International Business Machines Corporation | Program interruption filtering in transactional execution |
CN105389541B (zh) * | 2015-10-19 | 2018-05-01 | 广东欧珀移动通信有限公司 | 指纹图像的识别方法及装置 |
US11424621B2 (en) | 2020-01-28 | 2022-08-23 | Qualcomm Incorporated | Configurable redundant systems for safety critical applications |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06187405A (ja) * | 1993-08-01 | 1994-07-08 | Hitachi Ltd | 画像データ処理装置及びそれを用いたシステム |
US6075876A (en) * | 1997-05-07 | 2000-06-13 | Draganoff; Georgi Hristoff | Sliding yardsticks fingerprint enrollment and verification system and method |
JP2001084370A (ja) * | 1999-09-13 | 2001-03-30 | Nippon Telegr & Teleph Corp <Ntt> | 指紋認識装置およびデータ処理方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4399517A (en) * | 1981-03-19 | 1983-08-16 | Texas Instruments Incorporated | Multiple-input binary adder |
US4660165A (en) * | 1984-04-03 | 1987-04-21 | Trw Inc. | Pyramid carry adder circuit |
EP0257362A1 (de) * | 1986-08-27 | 1988-03-02 | Siemens Aktiengesellschaft | Addierer |
CA2021192A1 (en) * | 1989-07-28 | 1991-01-29 | Malcolm A. Mumme | Simplified synchronous mesh processor |
US5054090A (en) * | 1990-07-20 | 1991-10-01 | Knight Arnold W | Fingerprint correlation system with parallel FIFO processor |
US5148388A (en) * | 1991-05-17 | 1992-09-15 | Advanced Micro Devices, Inc. | 7 to 3 counter circuit |
US5187679A (en) * | 1991-06-05 | 1993-02-16 | International Business Machines Corporation | Generalized 7/3 counters |
US5291443A (en) * | 1991-06-26 | 1994-03-01 | Micron Technology, Inc. | Simultaneous read and refresh of different rows in a dram |
JP3724014B2 (ja) * | 1994-08-25 | 2005-12-07 | ソニー株式会社 | 画像認識装置および画像認識方法 |
US5963679A (en) * | 1996-01-26 | 1999-10-05 | Harris Corporation | Electric field fingerprint sensor apparatus and related methods |
KR100198662B1 (ko) * | 1996-05-16 | 1999-06-15 | 구본준 | 디램 셀, 디램 및 그의 제조 방법 |
US6442286B1 (en) * | 1998-12-22 | 2002-08-27 | Stmicroelectronics, Inc. | High security flash memory and method |
DE60025435T2 (de) * | 1999-09-13 | 2006-09-21 | Nippon Telegraph And Telephone Corp. | Parallelverarbeitungsvorrichtung und -verfahren |
JP2001242771A (ja) | 2000-02-29 | 2001-09-07 | Canon Inc | 画像読取装置及び画像形成装置 |
US6728862B1 (en) * | 2000-05-22 | 2004-04-27 | Gazelle Technology Corporation | Processor array and parallel data processing methods |
US7085796B1 (en) * | 2000-06-08 | 2006-08-01 | International Business Machines Corporation | Dynamic adder with reduced logic |
US7199897B2 (en) * | 2002-02-22 | 2007-04-03 | Ricoh Company, Ltd. | Image data processing apparatus for and image data processing method of pattern matching |
-
2004
- 2004-02-13 WO PCT/JP2004/001526 patent/WO2004104819A1/ja active Application Filing
- 2004-02-13 JP JP2004567189A patent/JP3788804B2/ja not_active Expired - Lifetime
- 2004-02-13 EP EP04711019A patent/EP1643356B1/en not_active Expired - Fee Related
- 2004-02-13 DE DE602004024995T patent/DE602004024995D1/de not_active Expired - Lifetime
- 2004-02-13 US US10/505,718 patent/US7480785B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06187405A (ja) * | 1993-08-01 | 1994-07-08 | Hitachi Ltd | 画像データ処理装置及びそれを用いたシステム |
US6075876A (en) * | 1997-05-07 | 2000-06-13 | Draganoff; Georgi Hristoff | Sliding yardsticks fingerprint enrollment and verification system and method |
JP2001084370A (ja) * | 1999-09-13 | 2001-03-30 | Nippon Telegr & Teleph Corp <Ntt> | 指紋認識装置およびデータ処理方法 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1643356A4 * |
Also Published As
Publication number | Publication date |
---|---|
JPWO2004104819A1 (ja) | 2006-07-20 |
US7480785B2 (en) | 2009-01-20 |
US20050259502A1 (en) | 2005-11-24 |
DE602004024995D1 (de) | 2010-02-25 |
EP1643356A1 (en) | 2006-04-05 |
JP3788804B2 (ja) | 2006-06-21 |
EP1643356A4 (en) | 2009-04-01 |
EP1643356B1 (en) | 2010-01-06 |
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