WO2004070781A3 - Asynchronous system-on-a-chip interconnect - Google Patents

Asynchronous system-on-a-chip interconnect Download PDF

Info

Publication number
WO2004070781A3
WO2004070781A3 PCT/US2004/002216 US2004002216W WO2004070781A3 WO 2004070781 A3 WO2004070781 A3 WO 2004070781A3 US 2004002216 W US2004002216 W US 2004002216W WO 2004070781 A3 WO2004070781 A3 WO 2004070781A3
Authority
WO
WIPO (PCT)
Prior art keywords
clock domain
asynchronous
synchronous
converters
domain
Prior art date
Application number
PCT/US2004/002216
Other languages
French (fr)
Other versions
WO2004070781A2 (en
Inventor
Uri Cummings
Andrew Lines
Original Assignee
Fulcrum Microsystems Inc
Uri Cummings
Andrew Lines
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fulcrum Microsystems Inc, Uri Cummings, Andrew Lines filed Critical Fulcrum Microsystems Inc
Priority to DE602004031925T priority Critical patent/DE602004031925D1/en
Priority to AT04705329T priority patent/ATE503329T1/en
Priority to EP04705329A priority patent/EP1590835B1/en
Publication of WO2004070781A2 publication Critical patent/WO2004070781A2/en
Publication of WO2004070781A3 publication Critical patent/WO2004070781A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/005—Correction by an elastic buffer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/0004—Selecting arrangements using crossbar selectors in the switching stages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling
    • H04L2012/5674—Synchronisation, timing recovery or alignment
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/101—Packet switching elements characterised by the switching fabric construction using crossbar or matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13034—A/D conversion, code compression/expansion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13214—Clock signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13322—Integrated circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13361—Synchronous systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13362—Asynchronous systems

Abstract

Methods and apparatus are described relating to a system-on-a-chip which includes a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate, the data rates comprising a plurality of different data rates. The system-on-a-chip also includes a plurality of clock domain converters. Each clock domain converter is coupled to a corresponding one of the synchronous modules, and is operable to convert data between the clock domain of the corresponding synchronous module and an asynchronous domain characterized by transmission of data according to an asynchronous handshake protocol. An asynchronous crossbar is coupled to the plurality of clock domain converters, and is operable in the asynchronous domain to implement a first-in-first-out (FIFO) channel between any two of the clock domain converters, thereby facilitating communication between any two of the synchronous modules.
PCT/US2004/002216 2003-02-03 2004-01-26 Asynchronous system-on-a-chip interconnect WO2004070781A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE602004031925T DE602004031925D1 (en) 2003-02-03 2004-01-26 ASYNCHRONOUS SYSTEM ON A CHIP CONNECTION
AT04705329T ATE503329T1 (en) 2003-02-03 2004-01-26 ASYNCHRONOUS SYSTEM-ON-A-CHIP CONNECTION
EP04705329A EP1590835B1 (en) 2003-02-03 2004-01-26 Asynchronous system-on-a-chip interconnect

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US44482003P 2003-02-03 2003-02-03
US60/444,820 2003-02-03
US10/634,597 2003-08-04
US10/634,597 US7239669B2 (en) 2002-04-30 2003-08-04 Asynchronous system-on-a-chip interconnect

Publications (2)

Publication Number Publication Date
WO2004070781A2 WO2004070781A2 (en) 2004-08-19
WO2004070781A3 true WO2004070781A3 (en) 2005-06-09

Family

ID=32776255

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/002216 WO2004070781A2 (en) 2003-02-03 2004-01-26 Asynchronous system-on-a-chip interconnect

Country Status (5)

Country Link
US (2) US7239669B2 (en)
EP (1) EP1590835B1 (en)
AT (1) ATE503329T1 (en)
DE (1) DE602004031925D1 (en)
WO (1) WO2004070781A2 (en)

Families Citing this family (77)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7231621B1 (en) * 2004-04-30 2007-06-12 Xilinx, Inc. Speed verification of an embedded processor in a programmable logic device
US20060041693A1 (en) * 2004-05-27 2006-02-23 Stmicroelectronics S.R.L. Asynchronous decoupler
US7577847B2 (en) * 2004-11-03 2009-08-18 Igt Location and user identification for online gaming
US7584449B2 (en) * 2004-11-22 2009-09-01 Fulcrum Microsystems, Inc. Logic synthesis of multi-level domino asynchronous pipelines
US7415030B2 (en) * 2005-02-10 2008-08-19 International Business Machines Corporation Data processing system, method and interconnect fabric having an address-based launch governor
EP1859575A1 (en) * 2005-03-04 2007-11-28 Koninklijke Philips Electronics N.V. Electronic device and a method for arbitrating shared resources
US7990983B2 (en) * 2005-03-31 2011-08-02 Intel Corporation Modular interconnect structure
FR2884035B1 (en) * 2005-04-04 2007-06-22 St Microelectronics Sa INTERFACING CICCUITS IN AN INTEGRATED ELECTRONIC CIRCUIT
US7318126B2 (en) * 2005-04-11 2008-01-08 International Business Machines Corporation Asynchronous symmetric multiprocessing
US8112654B2 (en) * 2005-06-01 2012-02-07 Teklatech A/S Method and an apparatus for providing timing signals to a number of circuits, and integrated circuit and a node
US7779286B1 (en) 2005-10-28 2010-08-17 Altera Corporation Design tool clock domain crossing management
US7769929B1 (en) 2005-10-28 2010-08-03 Altera Corporation Design tool selection and implementation of port adapters
EP1859372B1 (en) * 2006-02-23 2019-03-27 Mentor Graphics Corporation Cross-bar switching in an emulation environment
US7447620B2 (en) * 2006-02-23 2008-11-04 International Business Machines Corporation Modeling asynchronous behavior from primary inputs and latches
US20080005402A1 (en) * 2006-04-25 2008-01-03 Samsung Electronics Co., Ltd. Gals-based network-on-chip and data transfer method thereof
US7504851B2 (en) * 2006-04-27 2009-03-17 Achronix Semiconductor Corporation Fault tolerant asynchronous circuits
US7505304B2 (en) * 2006-04-27 2009-03-17 Achronix Semiconductor Corporation Fault tolerant asynchronous circuits
DE102006025133A1 (en) * 2006-05-30 2007-12-06 Infineon Technologies Ag Storage and storage communication system
US8031819B2 (en) * 2006-10-27 2011-10-04 Hewlett-Packard Development Company, L.P. Systems and methods for synchronizing an input signal
US7783808B2 (en) * 2006-11-08 2010-08-24 Honeywell International Inc. Embedded self-checking asynchronous pipelined enforcement (escape)
US9026692B2 (en) 2007-01-09 2015-05-05 Aeroflex Colorado Springs Inc. Data throttling circuit and method for a spacewire application
US7782991B2 (en) * 2007-01-09 2010-08-24 Freescale Semiconductor, Inc. Fractionally related multirate signal processor and method
US7746724B2 (en) * 2007-01-31 2010-06-29 Qimonda Ag Asynchronous data transmission
KR100850270B1 (en) * 2007-02-08 2008-08-04 삼성전자주식회사 Semiconductor memory device with fail bit latch
ES2883587T3 (en) 2007-04-12 2021-12-09 Rambus Inc Memory system with peer-to-peer request interconnect
US7594047B2 (en) * 2007-07-09 2009-09-22 Hewlett-Packard Development Company, L.P. Buffer circuit
US7912068B2 (en) * 2007-07-20 2011-03-22 Oracle America, Inc. Low-latency scheduling in large switches
EP2026493A1 (en) * 2007-08-16 2009-02-18 STMicroelectronics S.r.l. Method and systems for mesochronous communications in multiple clock domains and corresponding computer program product
US7995618B1 (en) * 2007-10-01 2011-08-09 Teklatech A/S System and a method of transmitting data from a first device to a second device
US7882473B2 (en) 2007-11-27 2011-02-01 International Business Machines Corporation Sequential equivalence checking for asynchronous verification
EP2227749B1 (en) * 2007-12-06 2014-08-27 Technion Research & Development Foundation Ltd. Bus enhanced network on chip
US7974278B1 (en) 2007-12-12 2011-07-05 Integrated Device Technology, Inc. Packet switch with configurable virtual channels
US8190942B2 (en) * 2008-07-02 2012-05-29 Cradle Ip, Llc Method and system for distributing a global timebase within a system-on-chip having multiple clock domains
US7907625B1 (en) * 2008-08-04 2011-03-15 Integrated Device Technology, Inc. Power reduction technique for buffered crossbar switch
US8122410B2 (en) * 2008-11-05 2012-02-21 International Business Machines Corporation Specifying and validating untimed nets
US8165255B2 (en) * 2008-12-19 2012-04-24 Freescale Semiconductor, Inc. Multirate resampling and filtering system and method
US9514074B2 (en) 2009-02-13 2016-12-06 The Regents Of The University Of Michigan Single cycle arbitration within an interconnect
US8230152B2 (en) * 2009-02-13 2012-07-24 The Regents Of The University Of Michigan Crossbar circuitry and method of operation of such crossbar circuitry
US8549207B2 (en) * 2009-02-13 2013-10-01 The Regents Of The University Of Michigan Crossbar circuitry for applying an adaptive priority scheme and method of operation of such crossbar circuitry
US8255610B2 (en) 2009-02-13 2012-08-28 The Regents Of The University Of Michigan Crossbar circuitry for applying a pre-selection prior to arbitration between transmission requests and method of operation of such crossbar circuitry
US8074193B2 (en) * 2009-03-11 2011-12-06 Institute of Computer Science (ICS) of the Foundation for Research & Technology Hellas-Foundation for Research and Technology Hellas (FORTH) Apparatus and method for mixed single-rail and dual-rail combinational logic with completion detection
US8352774B2 (en) 2010-06-23 2013-01-08 King Fahd University Of Petroleum And Minerals Inter-clock domain data transfer FIFO circuit
US8417867B2 (en) * 2010-11-17 2013-04-09 Xilinx, Inc. Multichip module for communications
WO2012077169A1 (en) * 2010-12-06 2012-06-14 富士通株式会社 Information processing system and information transmission method
US8583850B2 (en) * 2011-02-14 2013-11-12 Oracle America, Inc. Micro crossbar switch and on-die data network using the same
DE102012220488A1 (en) * 2012-11-09 2014-05-15 Robert Bosch Gmbh Subscriber station for a bus system and method for improving the reception quality of messages at a subscriber station of a bus system
CN103279442B (en) * 2013-06-14 2017-01-11 浪潮电子信息产业股份有限公司 Message filtering system and message filtering method of high-speed interconnection bus
GB2519414B (en) * 2013-08-28 2016-01-06 Imagination Tech Ltd Crossing pipelined data between circuitry in different clock domains
US9367286B2 (en) 2013-08-28 2016-06-14 Imagination Technologies Limited Crossing pipelined data between circuitry in different clock domains
US9325520B2 (en) * 2013-09-06 2016-04-26 Huawei Technologies Co., Ltd. System and method for an asynchronous processor with scheduled token passing
KR102206313B1 (en) 2014-02-07 2021-01-22 삼성전자주식회사 System interconnect and operating method of system interconnect
US9520180B1 (en) 2014-03-11 2016-12-13 Hypres, Inc. System and method for cryogenic hybrid technology computing and memory
US10073139B2 (en) * 2014-09-30 2018-09-11 Oracle International Corporation Cycle deterministic functional testing of a chip with asynchronous clock domains
CN104636253A (en) * 2015-01-13 2015-05-20 浪潮电子信息产业股份有限公司 Cross clock domain logic ASIC verification system and method based on metastable state injection
US9977852B2 (en) * 2015-11-04 2018-05-22 Chronos Tech Llc Application specific integrated circuit interconnect
US10073939B2 (en) 2015-11-04 2018-09-11 Chronos Tech Llc System and method for application specific integrated circuit design
US9977853B2 (en) * 2015-11-04 2018-05-22 Chronos Tech Llc Application specific integrated circuit link
US11550982B2 (en) 2015-11-04 2023-01-10 Chronos Tech Llc Application specific integrated circuit interconnect
US10331835B2 (en) 2016-07-08 2019-06-25 Chronos Tech Llc ASIC design methodology for converting RTL HDL to a light netlist
US10181939B2 (en) 2016-07-08 2019-01-15 Chronos Tech Llc Systems and methods for the design and implementation of an input and output ports for circuit design
US9825636B1 (en) * 2016-10-20 2017-11-21 Arm Limited Apparatus and method for reduced latency signal synchronization
CN107277914B (en) * 2017-06-15 2018-06-29 深圳市晟碟半导体有限公司 Equipment time synchronization control method and system in a kind of wireless mesh network
US10637592B2 (en) 2017-08-04 2020-04-28 Chronos Tech Llc System and methods for measuring performance of an application specific integrated circuit interconnect
KR102574580B1 (en) 2019-01-31 2023-09-06 제네럴 일렉트릭 컴퍼니 Battery charging and discharging power control in power grid
US11128742B2 (en) 2019-03-08 2021-09-21 Microsemi Storage Solutions, Inc. Method for adapting a constant bit rate client signal into the path layer of a telecom signal
US11087057B1 (en) 2019-03-22 2021-08-10 Chronos Tech Llc System and method for application specific integrated circuit design related application information including a double nature arc abstraction
US10972084B1 (en) 2019-12-12 2021-04-06 Microchip Technology Inc. Circuit and methods for transferring a phase value between circuits clocked by non-synchronous clock signals
US11323123B2 (en) 2019-12-20 2022-05-03 Microchip Technology Inc. Circuit to correct phase interpolator rollover integral non-linearity errors
US10917097B1 (en) 2019-12-24 2021-02-09 Microsemi Semiconductor Ulc Circuits and methods for transferring two differentially encoded client clock domains over a third carrier clock domain between integrated circuits
US11239933B2 (en) 2020-01-28 2022-02-01 Microsemi Semiconductor Ulc Systems and methods for transporting constant bit rate client signals over a packet transport network
US11366647B2 (en) * 2020-04-30 2022-06-21 Intel Corporation Automatic compiler dataflow optimization to enable pipelining of loops with local storage requirements
US11424902B2 (en) 2020-07-22 2022-08-23 Microchip Technology Inc. System and method for synchronizing nodes in a network device
US20220358069A1 (en) * 2021-05-07 2022-11-10 Chronos Tech Llc ADVANCED CENTRALIZED CHRONOS NoC
US11838111B2 (en) 2021-06-30 2023-12-05 Microchip Technology Inc. System and method for performing rate adaptation of constant bit rate (CBR) client data with a variable number of idle blocks for transmission over a metro transport network (MTN)
US11916662B2 (en) 2021-06-30 2024-02-27 Microchip Technology Inc. System and method for performing rate adaptation of constant bit rate (CBR) client data with a fixed number of idle blocks for transmission over a metro transport network (MTN)
US11736065B2 (en) 2021-10-07 2023-08-22 Microchip Technology Inc. Method and apparatus for conveying clock-related information from a timing device
US11799626B2 (en) 2021-11-23 2023-10-24 Microchip Technology Inc. Method and apparatus for carrying constant bit rate (CBR) client signals

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4773066A (en) * 1986-04-15 1988-09-20 The Mitre Corporation Synchronized multiple access apparatus and method for a local area network
US4849751A (en) * 1987-06-08 1989-07-18 American Telephone And Telegraph Company, At&T Bell Laboratories CMOS Integrated circuit digital crossbar switching arrangement
US6002861A (en) * 1988-10-05 1999-12-14 Quickturn Design Systems, Inc. Method for performing simulation using a hardware emulation system
US20020021694A1 (en) * 2000-08-09 2002-02-21 International Business Machines Corporation System for transmitting local area network (LAN) data frames through an asynchronous transfer mode (ATM) crossbar switch
US6374307B1 (en) * 1999-02-12 2002-04-16 Steve A. Ristau Non-intrusive DWDM billing system

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5752070A (en) 1990-03-19 1998-05-12 California Institute Of Technology Asynchronous processors
DE69230093T2 (en) * 1991-11-19 2000-04-13 Ibm Multiprocessor system
US5577204A (en) * 1993-12-15 1996-11-19 Convex Computer Corporation Parallel processing computer system interconnections utilizing unidirectional communication links with separate request and response lines for direct communication or using a crossbar switching device
US5832303A (en) 1994-08-22 1998-11-03 Hitachi, Ltd. Large scale interconnecting switch using communication controller groups with multiple input-to-one output signal lines and adaptable crossbar unit using plurality of selectors
US5517495A (en) 1994-12-06 1996-05-14 At&T Corp. Fair prioritized scheduling in an input-buffered switch
US5651137A (en) * 1995-04-12 1997-07-22 Intel Corporation Scalable cache attributes for an input/output bus
US5875338A (en) * 1995-12-14 1999-02-23 International Business Machines Corporation Method and apparatus for arbitrating resource requests utilizing independent tokens for arbiter cell selection
US5838684A (en) * 1996-02-22 1998-11-17 Fujitsu, Ltd. Low latency, high clock frequency plesioasynchronous packet-based crossbar switching chip system and method
US5802055A (en) 1996-04-22 1998-09-01 Apple Computer, Inc. Method and apparatus for dynamic buffer allocation in a bus bridge for pipelined reads
US5884100A (en) * 1996-06-06 1999-03-16 Sun Microsystems, Inc. Low-latency, high-throughput, integrated cache coherent I/O system for a single-chip processor
JPH1078934A (en) * 1996-07-01 1998-03-24 Sun Microsyst Inc Multi-size bus connection system for packet switching computer system
DE19636394A1 (en) * 1996-09-07 1998-03-12 Philips Patentverwaltung Local, ring-structured network operating according to the asynchronous transfer mode with wireless terminals
US6038656A (en) 1997-09-12 2000-03-14 California Institute Of Technology Pipelined completion for asynchronous communication
US6044061A (en) 1998-03-10 2000-03-28 Cabletron Systems, Inc. Method and apparatus for fair and efficient scheduling of variable-size data packets in an input-buffered multipoint switch
US6327253B1 (en) 1998-04-03 2001-12-04 Avid Technology, Inc. Method and apparatus for controlling switching of connections among data processing devices
US6279065B1 (en) 1998-06-03 2001-08-21 Compaq Computer Corporation Computer system with improved memory access
US6377579B1 (en) * 1998-06-11 2002-04-23 Synchrodyne Networks, Inc. Interconnecting a synchronous switching network that utilizes a common time reference with an asynchronous switching network
JP3111988B2 (en) * 1998-06-26 2000-11-27 日本電気株式会社 Switch control system for ATM exchange
US6301630B1 (en) 1998-12-10 2001-10-09 International Business Machines Corporation Interrupt response in a multiple set buffer pool bus bridge
US6230228B1 (en) 1999-04-01 2001-05-08 Intel Corporation Efficient bridge architecture for handling multiple write transactions simultaneously
US6546451B1 (en) * 1999-09-30 2003-04-08 Silicon Graphics, Inc. Method and apparatus for decoupling processor speed from memory subsystem speed in a node controller
US6175023B1 (en) * 2000-01-31 2001-01-16 Jian Liu Synthesis of water soluble 9-dihydro-paclitaxel derivatives from 9-dihydro-13-acetylbaccatin III
US7012925B2 (en) * 2000-09-08 2006-03-14 International Business Machines Corporation System for transmitting local area network (LAN) data frames
US6842728B2 (en) * 2001-03-12 2005-01-11 International Business Machines Corporation Time-multiplexing data between asynchronous clock domains within cycle simulation and emulation environments
US6763418B1 (en) * 2001-09-07 2004-07-13 Agilent Technologies, Inc. Request bus arbitration

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4773066A (en) * 1986-04-15 1988-09-20 The Mitre Corporation Synchronized multiple access apparatus and method for a local area network
US4849751A (en) * 1987-06-08 1989-07-18 American Telephone And Telegraph Company, At&T Bell Laboratories CMOS Integrated circuit digital crossbar switching arrangement
US6002861A (en) * 1988-10-05 1999-12-14 Quickturn Design Systems, Inc. Method for performing simulation using a hardware emulation system
US6374307B1 (en) * 1999-02-12 2002-04-16 Steve A. Ristau Non-intrusive DWDM billing system
US20020021694A1 (en) * 2000-08-09 2002-02-21 International Business Machines Corporation System for transmitting local area network (LAN) data frames through an asynchronous transfer mode (ATM) crossbar switch

Also Published As

Publication number Publication date
EP1590835A4 (en) 2008-10-08
EP1590835A2 (en) 2005-11-02
ATE503329T1 (en) 2011-04-15
EP1590835B1 (en) 2011-03-23
US7239669B2 (en) 2007-07-03
DE602004031925D1 (en) 2011-05-05
WO2004070781A2 (en) 2004-08-19
US20060239392A1 (en) 2006-10-26
US20040151209A1 (en) 2004-08-05

Similar Documents

Publication Publication Date Title
WO2004070781A3 (en) Asynchronous system-on-a-chip interconnect
CN1866803B (en) Method for solving clock synchronization in total Ethernet
CA2346609A1 (en) A pervasive dock and router with communication protocol converter
WO2006023567A3 (en) Gateway having an input/output scanner
TW200519389A (en) Improved communications system for implementation of synchronous, multichannel, galvanically isolated instrumentation devices
CN103916315A (en) Radio Over Ethernet for Radio Access Network and Cloud-RAN
GB2424350A (en) Method and system for virtual powerline local area networks
AU2003287964A1 (en) Methods, interface unit and nodes for using in parallel a communication network for real-time applications and non real-time applications
JP2005056426A5 (en)
HK1091339A1 (en) Connecting system, inverse multiplexer, data communication network and method
US7403548B2 (en) System for interfacing media access control module to small form factor pluggable module
CN201274482Y (en) High speed data transmission interface system
WO2003063394A3 (en) Methods and apparatuses for serial transfer of sonet framed data between components of a sonet system
CN101882959B (en) Automatic detection and application method of optical port transmission rate
CN201804988U (en) Multifunctional combiner
EP1376916A8 (en) Concatenated transmission of synchronous data
WO2003088595A3 (en) Synchronization in a communication system
CN103889008A (en) Ethernet Media Converter Supporting High-Speed Wireless Access Points
JP2004312604A (en) Cdma base station instrument
ATE310369T1 (en) SEQUENCED HIGH SPEED MULTI-CHANNEL BUS
HK1098620A1 (en) Method and arrangement for polling management
JPH11298459A (en) High speed transmission system and high speed transmitter
KR100355295B1 (en) Interface device and method between channel card and if board in bts
WO2004057821A8 (en) System and method for communicating digital information using time-and-frequency-bounded base functions
CN100473029C (en) Gigabit Ethernet data service access device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2004705329

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 2004705329

Country of ref document: EP