WO2004045869A1 - Method for improving the accuracy of an etched silicon pattern using mask compensation - Google Patents

Method for improving the accuracy of an etched silicon pattern using mask compensation Download PDF

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Publication number
WO2004045869A1
WO2004045869A1 PCT/US2003/035045 US0335045W WO2004045869A1 WO 2004045869 A1 WO2004045869 A1 WO 2004045869A1 US 0335045 W US0335045 W US 0335045W WO 2004045869 A1 WO2004045869 A1 WO 2004045869A1
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Prior art keywords
arc
mask pattern
forming
providing
compensated mask
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PCT/US2003/035045
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French (fr)
Inventor
Philip J. Koh
David T. Nemeth
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Sophia Wireless, Inc.
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Priority to AU2003290593A priority Critical patent/AU2003290593A1/en
Publication of WO2004045869A1 publication Critical patent/WO2004045869A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088Process specially adapted to improve the resolution of the mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • H01L21/30608Anisotropic liquid etching

Definitions

  • the present invention relates to a method for improving the accuracy of an etched silicon pattern. More particularly, the present invention relates to a method for improving the accuracy of an etched silicon pattern using mask compensation techniques.
  • Silicon wafers are conventionally used for semiconductor device fabrication.
  • a set of axes can be set up at right angles to represent the x, y, and z directions in a silicon cubic crystal.
  • Directional vectors which indicate the orientation of a crystal plane and the silicon wafer itself, can be derived from these axes. These directional vectors are known as the Miller Indices.
  • the Miller Indices of a crystal plane are determined by the points at which the crystal plane intersects the major (xyz) axes.
  • the most important crystal planes on a wafer are ⁇ 100>, ⁇ 110>, and ⁇ 111>. If a crystal plane intersects only the x-axis, then its direction is denoted as ⁇ 100>.
  • a silicon wafer normally has physical features to give the alignment of the crystal planes on the wafer. One typical arrangement is for the wafer surface to be parallel to the ⁇ 100> crystal plane.
  • a feature on the perimeter of the wafer further defines the crystal orientation. This can take the form of either a notch in the wafer or a flat section of the perimeter of the wafer. Typically, these features are only aligned to the crystal plane with an accuracy of about one degree. While a misalignment of one degree may not appear to be large, even a small misalignment such as this will have a significant impact on the precision of fabricated structures.
  • a critical processing requirement for making micromachined filters is the accuracy of the size of the physical structures. Because the resonant frequency of a resonator is proportional to the length, the length accuracy will be the same as the frequency accuracy. Given that resonator frequency accuracy of 100 parts per million or less is sometimes required, this means a cavity 5 millimeters long would require a dimensional accuracy of better than 0.5 microns.
  • a method for compensating for errors due to crystal plane misorientation by adjusting a patterned masking layer is provided.
  • a method for compensating for alignment errors is provided which compensates for rectangular pits. This illustrative method is able to eliminate any growth of the pit size, up to some maximum misorientation.
  • a more general method which does not eliminate dimensional errors, but reduces them substantially.
  • this method allows the width of a cantilever beam to change as the square of the misorientation angle (expressed in radians).
  • the method can be used to select which dimensional tolerances are critical and, therefore, reduce the error in the critical dimensions.
  • FIG. 1 shows the effect of having a masking layer misaligned to the crystal plane.
  • FIG. 2A shows a mask pattern for a rectangular cavity that is utilized to compensate for mask alignment errors with respect to the crystal plane according to an illustrative embodiment of the present invention.
  • FIG. 2B shows a mask pattern for a rectangular cavity that is utilized to compensate for mask alignment errors with respect to the crystal plane according to another illustrative embodiment of the present invention.
  • FIG. 2A shows a mask pattern for a rectangular cavity that is utilized to compensate for mask alignment errors with respect to the crystal plane according to another illustrative embodiment of the present invention.
  • FIG. 3 shows a masking layer and final pit shape for a cantilever wherein the masking layer is misaligned to the crystal plane.
  • FIG. 4 shows a compensated mask pattern according to an illustrative embodiment of the present invention.
  • FIG. 5 shows a compensated mask pattern according to an illustrative embodiment of the present invention.
  • FIG. 6 shows a compensated mask pattern according to an illustrative embodiment of the present invention.
  • FIG. 7 shows a compensated mask pattern according to an illustrative embodiment of the present invention.
  • Anisotropic silicon etching provides very good dimensional accuracy so long as a mask pattern for a particular etch lines up with the crystal plane of the silicon.
  • two alignment marks are used to align the mask and wafer.
  • One alignment mark is sufficient to align the mask and wafer in the x and y directions, but it requires two alignment marks to correct for rotational offsets.
  • the first pattern is typically aligned to the primary wafer flat. Even if a small error should occur in the orientation of the mask with respect to the crystal plane, the error can cause a sizeable effect. The effect becomes even more pronounced for larger structures.
  • Fig. 1 shows the effect of a final etch pit 102 when the masking layer 104 is misaligned to the crystal plane.
  • a beam can be formed by etching two pits side by side, with the beam being the gap between the two pits.
  • etching a pit with a protrusion in the side can form a cantilever.
  • a crystal plane misorientation causes a beam or a cantilever to decrease in width in proportion to sin (theta).
  • the beam width (and length) has a dimensional error proportional to the misorientation angle.
  • Silicon wafers typically have a part of the wafer that is roughly aligned to the crystal plane which is known as a "flat".
  • Standard wafers have the flat aligned to the appropriate crystal plane with an accuracy of one degree. Accuracies of one half degree are commercially available, but are more expensive. For many applications, including micromachined filters, even half a degree of misorientation can introduce more error than is acceptable.
  • Fig. 2A depicts mask patterns for a rectangular cavity that can be utilized to compensative for mask alignment errors with respect to the crystal plane.
  • a first compensated mask pattern 202 is shown as well as a second compensated mask 204 which is identical to first compensated mask pattern 202 but which has a small misorientation.
  • the mask patterns are formed such that a final etched cavity size 206 is completely independent of mask orientation relative to the crystal plane misorientation, up to some specified angle.
  • Each mask pattern shown in Fig. 2A consists of four arcs and eight straight lines.
  • the radius of each of the first two arcs is formed to be half of the rectangle width.
  • the radius of each of the other two arcs is formed to be half of the rectangle height.
  • the eight straight lines are formed so as to be tangent to the arcs at the end points of each arc.
  • a first straight line is provided tangent to the first arc at a first end of the first arc and a second straight line is provided tangent to the first arc at a second end of the first arc.
  • Straight lines are provided in a similar manner for the remaining three arcs.
  • the arcs are formed so as to sweep an angle that is twice a specified tolerance angle, and are formed so as to be tangent to the rectangle at center points of where the final pit is to be.
  • the final etch shape of a mask opening will be the smallest rectangle that completely encloses the mask opening and has edges along the crystal planes of the wafer. Rotating this shape relative to the crystal plane by an amount less than the tolerance angle will not change the dimensions of the bounding rectangle. The relative position of two rectangles will change, but the dimensions of each rectangle will be independent of the rotation.
  • This illustrative method requires time for the etchback of the fast etching crystal planes.
  • the target depth of the cavity must be greater than half the length of the resonator times the etch ratio of the fast etch plane to the etch rate of the ⁇ 100> plane.
  • TMAH tetra-methyl ammonium hydroxide
  • the contact point of the mask pattern to the rectangle wall need not be an arc.
  • Fig. 3 shows both the original masking layer 302, which is also the outline of the desired final pit shape, and the final etched pit shape 304, provided the silicon crystal plane is not aligned to the masking layer.
  • This pit has convex corners, so some form of convex corner protection is required.
  • the convex corner protection features have been omitted, as they are well known in the art and can be easily integrated with the compensation techniques as described herein.
  • a cantilever is defined.
  • the dimensional accuracy of a cantilever is of great importance.
  • an inter- digital filter design can use cantilevers or other features as resonators. The frequency of these resonators varies with the length, and a filter response can be very sensitive to variations in this length.
  • a compensated mask 402 is made so as to touch the walls of the original uncompensated mask 404 at only one point. The placement of these points on the walls is determined by which of the dimensions are most critical to preserve. The lines from this compensated mask 402 all form the same small angle ⁇ with the uncompensated mask 404.
  • This small angle ⁇ determines the amount of angular misorientation that the mask is insensitive to. As a general rule, it should be made larger than the expected tolerance. For example, if a misorientation is expected of up to one degree, it would be desirable to make the small angle ⁇ larger than one degree.
  • Fig. 4 illustrates the effects of making the angle larger than the expected tolerance. Again, any convex corner protectors have been omitted, but could easily be added by one skilled in the art.
  • Fig. 6 shows the compensated mask pattern 402 as described above and a final etch pit shape 604 for a given crystal misorientation.
  • the crystal misorientation shown is much larger than what would be routinely expected. It is exaggerated to help illustrate the effects of the misorientation. As discussed above, some sort of convex corner protection would be needed and is not shown, but could be easily added by one skilled in the art.
  • the compensation technique as described herein can greatly reduce the variation in the frequency of the resonance. It would also be more accurate than an uncompensated beam for any application that requires the beam to be a certain length. For example, the beam might act as a compliant spring. The force versus displacement constant would be closer to the designed value for the compensated beam than for the uncompensated beam.
  • Fig. 7 shows the desired final pit shape 702 in a ⁇ 110> silicon wafer, and a compensated mask structure 704.
  • an etched pit will have vertical sidewalls. This is because slow-etch planes (i.e., the ⁇ 111> planes), are perpendicular to the surface of the wafer.
  • the edges of a self-terminated pit are not perpendicular but, rather, form an angle.
  • the outer line shows the edges of the self -terminated pit.
  • a micromachined plug and socket system could be improved by these techniques by increasing the accuracy of the plug and socket dimensions, thus providing a better fit.

Abstract

A method is provided for compensating for errors due to crystal plane misorientation by adjusting a patterned masking layer. A mask pattern (202, 204) for a rectangular cavity is formed having a plurality of arcs and straight lines tangent to the ends of the arcs. The final etched cavity (206) will be the smallest rectangle that completely encloses the mask opening and has edges along the crystal plane of the wafer. In addition, a more general method is shown which does not eliminate dimensional errors, but reduces them substantially. In particular, this method allows the width of a cantilever beam to change as the square of the misorientation angle (expressed in radians). The method can be used to select which dimensional tolerances are critical and, therefore, reduce the error in the critical dimensions.

Description

METHOD FOR IMPROVING THE ACCURACY OF AN ETCHED SILICON PATTERN USING MASK COMPENSATION
CROSS-REFERENCE TO RELATED APPLICATIONS
[01] This application claims benefit of Provisional Application No. 60/426,528 filed November 15, 2002, the disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
[02] 1. Field of the Invention
[03] The present invention relates to a method for improving the accuracy of an etched silicon pattern. More particularly, the present invention relates to a method for improving the accuracy of an etched silicon pattern using mask compensation techniques.
[04] 2. Related Art
[05] Silicon wafers are conventionally used for semiconductor device fabrication.
A set of axes can be set up at right angles to represent the x, y, and z directions in a silicon cubic crystal. Directional vectors, which indicate the orientation of a crystal plane and the silicon wafer itself, can be derived from these axes. These directional vectors are known as the Miller Indices.
[06] The Miller Indices of a crystal plane are determined by the points at which the crystal plane intersects the major (xyz) axes. For semiconductor wafer processing, the most important crystal planes on a wafer are <100>, <110>, and <111>. If a crystal plane intersects only the x-axis, then its direction is denoted as <100>. A plane that intersects each of the major axes at x=l, y=l, and z=l is denoted as <111>. [07] A silicon wafer normally has physical features to give the alignment of the crystal planes on the wafer. One typical arrangement is for the wafer surface to be parallel to the <100> crystal plane. A feature on the perimeter of the wafer further defines the crystal orientation. This can take the form of either a notch in the wafer or a flat section of the perimeter of the wafer. Typically, these features are only aligned to the crystal plane with an accuracy of about one degree. While a misalignment of one degree may not appear to be large, even a small misalignment such as this will have a significant impact on the precision of fabricated structures.
[08] For example, a critical processing requirement for making micromachined filters is the accuracy of the size of the physical structures. Because the resonant frequency of a resonator is proportional to the length, the length accuracy will be the same as the frequency accuracy. Given that resonator frequency accuracy of 100 parts per million or less is sometimes required, this means a cavity 5 millimeters long would require a dimensional accuracy of better than 0.5 microns.
[09] A problem arises in that if a shape is patterned on a silicon wafer, and this pattern is misaligned with respect to the crystal plane by some small angle theta, then the final etched pit will be larger than the desired shape by an amount proportional to the angle. Therefore, what is needed is a method to compensate for errors in a final etched pit due to this type of misalignment.
SUMMARY OF THE INVENTION
[10] A method is provided for compensating for errors due to crystal plane misorientation by adjusting a patterned masking layer. In an illustrative embodiment of the present invention, a method for compensating for alignment errors is provided which compensates for rectangular pits. This illustrative method is able to eliminate any growth of the pit size, up to some maximum misorientation.
[11] In another illustrative embodiment, a more general method is shown which does not eliminate dimensional errors, but reduces them substantially. In particular, this method allows the width of a cantilever beam to change as the square of the misorientation angle (expressed in radians). The method can be used to select which dimensional tolerances are critical and, therefore, reduce the error in the critical dimensions.
[12] The above and other features of the invention including various and novel details of construction and combination of parts will now be more fully described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the particular features embodying the invention are shown by way of illustration only and not as a limitation of the invention. The principle and features of this invention may be employed in varied and numerous embodiments without departing from the scope of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[13] Aspects of illustrative, non-limiting embodiments of the present invention will become more apparent by describing in detail embodiments thereof with reference to the attached drawings in which: [14] FIG. 1 shows the effect of having a masking layer misaligned to the crystal plane. [15] FIG. 2A shows a mask pattern for a rectangular cavity that is utilized to compensate for mask alignment errors with respect to the crystal plane according to an illustrative embodiment of the present invention. [16] FIG. 2B shows a mask pattern for a rectangular cavity that is utilized to compensate for mask alignment errors with respect to the crystal plane according to another illustrative embodiment of the present invention. [17] FIG. 3 shows a masking layer and final pit shape for a cantilever wherein the masking layer is misaligned to the crystal plane. [18] FIG. 4 shows a compensated mask pattern according to an illustrative embodiment of the present invention. [19] FIG. 5 shows a compensated mask pattern according to an illustrative embodiment of the present invention. [20] FIG. 6 shows a compensated mask pattern according to an illustrative embodiment of the present invention. [21] FIG. 7 shows a compensated mask pattern according to an illustrative embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[22] The following description of illustrative non-limiting embodiments of the invention discloses specific configurations, features, and operations. However, the embodiments are merely examples of the present invention, and thus, the specific features described below are merely used to more easily describe such embodiments and to provide an overall understanding of the present invention.
[23] Accordingly, one skilled in the art will readily recognize that the present invention is not limited to the specific embodiments described below. Furthermore, the description of various configurations, features, and operations of the present invention that are known to one skilled in the art are omitted for the sake of clarity and brevity. Also, it is to be understood that the phraseology and terminology employed herein is for the purpose of description and should not be regarded as limiting.
[24] Anisotropic silicon etching provides very good dimensional accuracy so long as a mask pattern for a particular etch lines up with the crystal plane of the silicon. Typically, two alignment marks are used to align the mask and wafer. One alignment mark is sufficient to align the mask and wafer in the x and y directions, but it requires two alignment marks to correct for rotational offsets. As there is no pattern on the wafer for the first pattern to align to, the first pattern is typically aligned to the primary wafer flat. Even if a small error should occur in the orientation of the mask with respect to the crystal plane, the error can cause a sizeable effect. The effect becomes even more pronounced for larger structures.
[25] Fig. 1 shows the effect of a final etch pit 102 when the masking layer 104 is misaligned to the crystal plane. Using basic geometry, it can be determined that for a net misorientation angle of θ, the increase in the width of a cavity is the length of the cavity times the sine of θ. At small angles, the dimensional error in the cavity is
proportional to the angle, as sin (θ) ~ θ at small angles.
[26] Next, consider the effect of misorientation on a beam instead of a cavity. A beam can be formed by etching two pits side by side, with the beam being the gap between the two pits. Alternatively, etching a pit with a protrusion in the side can form a cantilever. Just as the cavity is increased in width, a crystal plane misorientation causes a beam or a cantilever to decrease in width in proportion to sin (theta). Hence, the beam width (and length) has a dimensional error proportional to the misorientation angle. [27] Silicon wafers typically have a part of the wafer that is roughly aligned to the crystal plane which is known as a "flat". Standard wafers have the flat aligned to the appropriate crystal plane with an accuracy of one degree. Accuracies of one half degree are commercially available, but are more expensive. For many applications, including micromachined filters, even half a degree of misorientation can introduce more error than is acceptable.
[28] Fig. 2A depicts mask patterns for a rectangular cavity that can be utilized to compensative for mask alignment errors with respect to the crystal plane. A first compensated mask pattern 202 is shown as well as a second compensated mask 204 which is identical to first compensated mask pattern 202 but which has a small misorientation. The mask patterns are formed such that a final etched cavity size 206 is completely independent of mask orientation relative to the crystal plane misorientation, up to some specified angle.
[29] Each mask pattern shown in Fig. 2A consists of four arcs and eight straight lines. The radius of each of the first two arcs is formed to be half of the rectangle width. Similarly, the radius of each of the other two arcs is formed to be half of the rectangle height.
[30] The eight straight lines are formed so as to be tangent to the arcs at the end points of each arc. For example, a first straight line is provided tangent to the first arc at a first end of the first arc and a second straight line is provided tangent to the first arc at a second end of the first arc. Straight lines are provided in a similar manner for the remaining three arcs. Further, the arcs are formed so as to sweep an angle that is twice a specified tolerance angle, and are formed so as to be tangent to the rectangle at center points of where the final pit is to be. [31] Because the anisotropic etches etch the <111> plane of silicon very slowly, but other planes more quickly, the final etch shape of a mask opening will be the smallest rectangle that completely encloses the mask opening and has edges along the crystal planes of the wafer. Rotating this shape relative to the crystal plane by an amount less than the tolerance angle will not change the dimensions of the bounding rectangle. The relative position of two rectangles will change, but the dimensions of each rectangle will be independent of the rotation.
[32] This illustrative method requires time for the etchback of the fast etching crystal planes. In order to accomplish this, the target depth of the cavity must be greater than half the length of the resonator times the etch ratio of the fast etch plane to the etch rate of the <100> plane. In a tetra-methyl ammonium hydroxide (TMAH)
solution (20% w/w) at 95 °C, this is typically around 6 or 7. If the etch is to go completely through the wafer, or if there is an etch stop layer, then this requirement is lifted. This is because the etch can be run long enough to completely etch back the extra material.
[33] The contact point of the mask pattern to the rectangle wall need not be an arc.
If the contact is made in the form of a point, this will also provide compensation to misorientation. The error will be proportional to the cosine of the misorientation angle, which is much smaller than an uncompensated rectangle. Point contacts can have the advantage revealing faster etch planes than an arc contact, reducing the total etching time needed to realize a rectangle. Fig. 2B depicts this variation on the compensation scheme as shown by the mask opening 208, the final etch shape 210 and a point contact 212. [34] Next, a method is described for compensating for other shapes. In an illustrative embodiment, compensation takes place for those walls of the etch pit which contain edges which are aligned to the <111> crystal plane. Looking at the mask on a <100> silicon wafer, these will be the edges that are either parallel or perpendicular to the flat. Unlike the above-mentioned compensation for rectangular pits, this method does not completely eliminate dimensional variation. It does, however, significantly reduce it, particularly for small angles such as the misorientations one would expect to find in commercially available material.
[35] Fig. 3 shows both the original masking layer 302, which is also the outline of the desired final pit shape, and the final etched pit shape 304, provided the silicon crystal plane is not aligned to the masking layer. This pit has convex corners, so some form of convex corner protection is required. The convex corner protection features have been omitted, as they are well known in the art and can be easily integrated with the compensation techniques as described herein.
[36] Note that in etching the pit as shown in Fig. 3, a cantilever is defined. The dimensional accuracy of a cantilever is of great importance. For example, an inter- digital filter design can use cantilevers or other features as resonators. The frequency of these resonators varies with the length, and a filter response can be very sensitive to variations in this length.
[37] For an uncompensated mask, the open sections of the pit increase linearly with misorientation, and the length and width of a cantilever will decrease linearly with the angle misorientation. That is to say, A' is larger than A, with the difference A' -A being linear in the misorientation angle. Similarly, B' is smaller than B, C is larger than C, and E' is larger than E. All of these errors scale linearly with the misorientation angle.
[38] In compensating a shape like the one shown in Fig. 3, the goal is to preserve, as much as possible, the dimensions of both the holes and the cantilevers. To accomplish this, as shown in Fig. 4, a compensated mask 402 is made so as to touch the walls of the original uncompensated mask 404 at only one point. The placement of these points on the walls is determined by which of the dimensions are most critical to preserve. The lines from this compensated mask 402 all form the same small angle α with the uncompensated mask 404.
[39] This small angle α determines the amount of angular misorientation that the mask is insensitive to. As a general rule, it should be made larger than the expected tolerance. For example, if a misorientation is expected of up to one degree, it would be desirable to make the small angle α larger than one degree. Fig. 4 illustrates the effects of making the angle larger than the expected tolerance. Again, any convex corner protectors have been omitted, but could easily be added by one skilled in the art.
[40] The principle behind the placement of the mask 402 is as follows. For example, suppose two points are lying on a horizontal line, a distance d apart, each with a vertical line running through it. If these lines are tilted by the same angle θ while keeping the lines parallel, the distance between the lines will be reduced by an amount of d times the cosine of θ. For small angles, the angle is proportional to the square of θ (measured in radians). The same holds true for points that lie on the same vertical line. [41] In Fig. 4, suppose it was desired to keep the dimension B as accurate as possible. To accomplish this, we would want the points P4 and PS to be horizontal from each other. Then the error in the B dimension would be proportional to the square of the misorientation angle, which is much smaller than that of the uncompensated mask shown previously in Fig. 3.
[42] Similarly, by keeping P3 horizontal with P4, dimension A is compensated as well. Consider dimensions C, D, and E. Because each wall is contacted by only one contact point, all of the distances cannot compensated using this technique. For example, if P7 and P8 are placed on the same vertical line, so that dimension E is compensated, then clearly PI and P8 cannot be vertical and dimension D will not be fully compensated. The final dimension, however, will still be closer to the design than the uncompensated mask.
[43] To see how much error is present, consider Fig. 5. Suppose that P7 and P8 have been chosen to be vertical, to provide full compensation for dimension E. To determine the error in dimension D, draw a vertical line through P8 and draw a line from P8 to PI, as shown in Fig. 5. The angle between the lines is depicted ANGl.
[44] In order to determine the final dimension D for a given crystal misorientation angle θ, it must be known how much the vertical spacing between them will change. Elementary trigonometry reveals that the vertical distance is proportional to the cosine of ANGl. For a small misorientation angle θ, the error in the distance is proportional to the sine of ANGl multiplied by θ. If uncompensated, this mask would give an error proportional to θ. Thus, it is seen that the error in dimension D due to a misorientation is reduced by a factor of sin (ANGl), which is always less than 1. This means that the compensated final dimension D will be closer to the designed dimension than the uncompensated final dimension D.
[45] Next, consider the effect on the dimensions of the final etched pit of a small crystal misorientation on a compensated mask. The difference in the width of the cantilever, as well as the difference in the width of the openings, is proportional to the length of the wall times the difference between one and the cosine of the misorientation angle. For small angles, cos (θ) ~ l-(θ) 12, so the error is proportional to θ2/2, where θ is measured in radians. A one degree angle is about 0.0 175 radians. This means that for a one degree misorientation, the variation of the dimension of the cantilever will be less than one hundredth of the variation for an uncompensated structure.
[46] Fig. 6 shows the compensated mask pattern 402 as described above and a final etch pit shape 604 for a given crystal misorientation. The crystal misorientation shown is much larger than what would be routinely expected. It is exaggerated to help illustrate the effects of the misorientation. As discussed above, some sort of convex corner protection would be needed and is not shown, but could be easily added by one skilled in the art.
[47] The final dimensions A", B" and E" differ from A, B, and E, respectively, in proportion to the cosine of the misorientation angle. As has been demonstrated above, this is vastly smaller than the error from an uncompensated mask. The dimensions D and C differ from D" and C" proportional to the misorientation angle, but by an amount reduced by some factor less than 1 depending on the exact geometry, as described above. ' [48] It can be seen that the length of the beam protruding into the pit is no longer clearly defined, as the two edges of the beam have different lengths. However, the points PI, P2 and P8, as shown in Fig. 5, can be chosen so that the average of the lengths of the two edges of the beam differs from the desired beam length by the cosine of the misorientation angle.
[49] If the beam is used as a resonator in a filter, the compensation technique as described herein can greatly reduce the variation in the frequency of the resonance. It would also be more accurate than an uncompensated beam for any application that requires the beam to be a certain length. For example, the beam might act as a compliant spring. The force versus displacement constant would be closer to the designed value for the compensated beam than for the uncompensated beam.
[50] These illustrative methods can be applied to other crystal orientations as well.
For example, Fig. 7 shows the desired final pit shape 702 in a <110> silicon wafer, and a compensated mask structure 704. With this crystal orientation wafer, an etched pit will have vertical sidewalls. This is because slow-etch planes (i.e., the <111> planes), are perpendicular to the surface of the wafer. The edges of a self-terminated pit are not perpendicular but, rather, form an angle. The outer line shows the edges of the self -terminated pit.
[51] To determine the contact points for the compensated mask 704, reference lines are drawn that are perpendicular to the final desired edges, so that each line intersects the opposing pit edges that we wish to compensate. Such a construction is shown in Fig. 7. Note that, because the pit edges are not perpendicular, a reference line drawn perpendicular to one face might not intersect a parallel face. In that case, the contact point should be the vertex of the final desired vertex. As in the case discussed above, this will still provide better dimensional tolerance than an uncompensated mask.
[52] For a simple parallelogram with sides along the <111> planes, it is possible to construct a compensated mask that should perfectly reproduce the desired dimensions. The technique is the same for a rectangular pit etched in <100> silicon. To construct this mask, two reference line segments are drawn that are perpendicular to the opposing parallel faces and that connect them. The segments should bisect each other. It is noted that this is not possible for shapes with aspect ratios that are too large.
[53] Next, four arcs are constructed that are centered on the intersection of the reference segments, and are tangent to the final desired pit at the points where said reference lines intersect the final desired pit. The ends of the arcs are extended with line segments that are tangent to the ends of the arc and which intersect. These segments and the arc form a closed contour that is the compensated mask opening 704. Small rotations of the crystal plane relative to this mask will produce a pit with the exact same dimensions.
[54] The foregoing methods of modifying the etch mask for an anisotropically etched wafer improve the dimensional tolerance of the final etched cavity for a given misorientation of the mask to the crystal plane. The methods described herein are applicable to reducing the effect of crystal plane misorientation to anisotropically etched structures, but are not limited to the micromachining applications disclose above.
[55] Indeed, the methods described herein can be used for many different micromachining applications. As an illustrative example, a micromachined plug and socket system could be improved by these techniques by increasing the accuracy of the plug and socket dimensions, thus providing a better fit.
[56] The previous description of embodiments is provided to enable a person skilled in the art to make and use the present invention. Moreover, various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles and specific examples defined herein may be applied to other embodiments without the use of inventive faculty.
[57] For example, some or all of the features of the different embodiments discussed above may be combined into a single embodiment. Conversely, some of the features of a single embodiment discussed above may be deleted from the embodiment. Therefore, the present invention is not intended to be limited to the embodiments described herein but is to be accorded the widest scope as defined by the limitations of the claims and equivalents.

Claims

WHAT IS CLAIMED IS:
1. A method or forming a compensated mask pattern for a wafer comprising: providing a first arc having a first end and a second end; providing a first straight line tangent to said first arc at the first end of said first arc; and providing a second straight line tangent to said first arc at the second end of the first arc.
2. The method for forming a compensated mask pattern according to claim 1, further comprising: providing a second arc having a first end and a second end, said second arc being provided opposite to said first arc; providing a third straight line tangent to said second arc at the first end of said second arc; and providing a fourth straight line tangent to said second arc at the second end of said second arc.
3. The method for forming a compensated mask pattern according to claim 2, further comprising: providing a third arc having a first end and a second end; providing a fifth straight line tangent to said third arc at the first end of said third arc; and providing a sixth straight line tangent to said third arc at the second end of said third arc.
4. The method for forming a compensated mask pattern according to claim 3, further comprising: providing a fourth arc having a first end and a second end, said fourth arc being provided opposite to said third arc; providing a seventh straight line tangent to said fourth arc at the first end of said fourth arc; and providing an eighth straight line tangent to said fourth arc at the second end of said fourth arc.
5. The method for forming a compensated mask pattern according to claim 4, wherein the compensated mask pattern is formed for a rectangular cavity.
6. The method for forming a compensated mask pattern according to claim 5, wherein the radius of said first arc and said second arc is half of the width of the rectangular cavity.
7. The method for forming a compensated mask pattern according to claim 5, wherein the radius of said third arc and said fourth arc is half of the length of the rectangular
cavity.
8. The method for forming a compensated mask pattern according to claim 7, wherein each of said first arc, said second arc, said third arc, and said fourth arc sweeps an angle that is greater than a tolerance angle.
9. A method for forming a compensated mask pattern for a wafer comprising: providing a plurality of interconnected lines, wherein each of the plurality of interconnected lines touches a wall of an uncompensated mask pattern at only one point.
10. The method for forming a compensated mask pattern according to claim 9, wherein each of the lines forming the compensated mask pattern forms approximately the same angle relative to each of the walls of the uncompensated mask pattern.
11. The method for forming a compensated mask pattern according to claim 10, wherein the angle is larger than a tolerance angle.
12. The method for forming a compensated mask pattern according to claim 11, wherein the tolerance angle is approximately equal to a misorientation angle relative to the crystal plane.
13. The method for forming a compensated mask pattern according to claim 12, wherein the compensated mask pattern is formed such that at least two of the points touching the walls of the uncompensated mask pattern are provided so as to be horizontal or vertical with respect to one other.
14. The method for forming a compensated mask pattern according to claim 9, wherein the compensated mask pattern is formed for a cantilever.
15. A method for forming a compensated mask pattern for a wafer comprising: providing a plurality of reference lines which intersect a desired shape, wherein each of the plurality of reference lines is perpendicular to an edge of the desired shape; and providing a plurality of arcs centered at points where said reference lines intersect the desired shape.
16. The method for forming a compensated mask pattern according to claim 15, further comprising: providing a plurality of straight lines tangent to said plurality of arcs at a first end and a second end of each of said plurality of arcs, wherein said plurality of arcs and said plurality of straight lines are connected so as to form a closed contour.
17. The method for forming a compensated mask pattern according to claim 16, wherein the plurality of arcs are tangent to an edge of the desired shape at the points at which said reference lines intersect the desired shape.
18. The method for forming a compensated mask pattern according to claim 15, wherein the compensated mask pattern is formed for a parallelogram.
PCT/US2003/035045 2002-11-15 2003-11-13 Method for improving the accuracy of an etched silicon pattern using mask compensation WO2004045869A1 (en)

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CN103035477A (en) * 2011-09-30 2013-04-10 中国科学院上海微系统与信息技术研究所 Method for fabricating monocrystalline silicon nanostructure
CN115620626A (en) * 2022-08-12 2023-01-17 荣耀终端有限公司 Electronic equipment, display screen, display module and dislocation quantity testing method thereof

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JPS58200238A (en) * 1982-05-19 1983-11-21 Toshiba Corp Photomask
JPH0289054A (en) * 1988-09-26 1990-03-29 Nec Corp Mask for exposing
JPH04181755A (en) * 1990-11-16 1992-06-29 Shin Etsu Handotai Co Ltd Dielectric isolation substrate and its manufacture
US5772902A (en) * 1995-01-27 1998-06-30 Carnegie Mellon University Method to prevent adhesion of micromechanical structures
US6177285B1 (en) * 1996-03-01 2001-01-23 Siemens Aktiengesellschaft Process for determining the crystal orientation in a wafer

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Publication number Priority date Publication date Assignee Title
JPS58200238A (en) * 1982-05-19 1983-11-21 Toshiba Corp Photomask
JPH0289054A (en) * 1988-09-26 1990-03-29 Nec Corp Mask for exposing
JPH04181755A (en) * 1990-11-16 1992-06-29 Shin Etsu Handotai Co Ltd Dielectric isolation substrate and its manufacture
US5772902A (en) * 1995-01-27 1998-06-30 Carnegie Mellon University Method to prevent adhesion of micromechanical structures
US6177285B1 (en) * 1996-03-01 2001-01-23 Siemens Aktiengesellschaft Process for determining the crystal orientation in a wafer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035477A (en) * 2011-09-30 2013-04-10 中国科学院上海微系统与信息技术研究所 Method for fabricating monocrystalline silicon nanostructure
CN115620626A (en) * 2022-08-12 2023-01-17 荣耀终端有限公司 Electronic equipment, display screen, display module and dislocation quantity testing method thereof
CN115620626B (en) * 2022-08-12 2023-10-20 荣耀终端有限公司 Electronic equipment, display screen, display module and dislocation amount testing method of display module

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