WO2004017209A3 - Optimized write back for context switching - Google Patents
Optimized write back for context switching Download PDFInfo
- Publication number
- WO2004017209A3 WO2004017209A3 PCT/IB2003/003262 IB0303262W WO2004017209A3 WO 2004017209 A3 WO2004017209 A3 WO 2004017209A3 IB 0303262 W IB0303262 W IB 0303262W WO 2004017209 A3 WO2004017209 A3 WO 2004017209A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- cache
- main memory
- references
- difference
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
Abstract
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2003247098A AU2003247098A1 (en) | 2002-08-14 | 2003-07-17 | Optimized write back for context switching |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02078363.5 | 2002-08-14 | ||
EP02078363 | 2002-08-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2004017209A2 WO2004017209A2 (en) | 2004-02-26 |
WO2004017209A3 true WO2004017209A3 (en) | 2004-08-05 |
Family
ID=31725455
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2003/003262 WO2004017209A2 (en) | 2002-08-14 | 2003-07-17 | Optimized write back for context switching |
Country Status (3)
Country | Link |
---|---|
AU (1) | AU2003247098A1 (en) |
TW (1) | TW200415467A (en) |
WO (1) | WO2004017209A2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5622251B2 (en) * | 2012-06-26 | 2014-11-12 | 東芝三菱電機産業システム株式会社 | Data management apparatus, data management method, and data management program |
GB2533768B (en) * | 2014-12-19 | 2021-07-21 | Advanced Risc Mach Ltd | Cleaning a write-back cache |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5119485A (en) * | 1989-05-15 | 1992-06-02 | Motorola, Inc. | Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation |
US6209061B1 (en) * | 1998-03-02 | 2001-03-27 | Hewlett-Packard Co. | Integrated hierarchical memory overlay having invariant address space span that inactivates a same address space span in main memory |
-
2003
- 2003-07-17 AU AU2003247098A patent/AU2003247098A1/en not_active Abandoned
- 2003-07-17 WO PCT/IB2003/003262 patent/WO2004017209A2/en not_active Application Discontinuation
- 2003-08-11 TW TW092121987A patent/TW200415467A/en unknown
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5119485A (en) * | 1989-05-15 | 1992-06-02 | Motorola, Inc. | Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation |
US6209061B1 (en) * | 1998-03-02 | 2001-03-27 | Hewlett-Packard Co. | Integrated hierarchical memory overlay having invariant address space span that inactivates a same address space span in main memory |
Non-Patent Citations (2)
Title |
---|
CHARLESWORTH A: "The Sun Fireplane System Interconnect", CONFERENCE ON HIGH PERFORMANCE NETWORKING AND COMPUTING, PROCEEDINGS OF THE 2001 ACM/IEEE CONFERENCE ON SUPERCOMPUTING, ACM PRESS, NEW YORK, NY, USA, 10 November 2001 (2001-11-10) - 16 November 2001 (2001-11-16), Denver, Colorado, pages 1 - 14, XP002281147, ISBN: 0-7695-1357-3 * |
PHILIPS: "Data Book - TM 1300 Media Processor - Product Specification - ToC - Chapters 4, 5, Appendix A-1,2,20,21,79", 30 September 2000, PHILIPS SEMICONDUCTORS, SUNNYVALE,CA 94088, XP002281148 * |
Also Published As
Publication number | Publication date |
---|---|
WO2004017209A2 (en) | 2004-02-26 |
AU2003247098A1 (en) | 2004-03-03 |
TW200415467A (en) | 2004-08-16 |
AU2003247098A8 (en) | 2004-03-03 |
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