WO2003098439A3 - Method and apparatus for providing error correction within a register file of a cpu - Google Patents

Method and apparatus for providing error correction within a register file of a cpu Download PDF

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Publication number
WO2003098439A3
WO2003098439A3 PCT/US2003/012137 US0312137W WO03098439A3 WO 2003098439 A3 WO2003098439 A3 WO 2003098439A3 US 0312137 W US0312137 W US 0312137W WO 03098439 A3 WO03098439 A3 WO 03098439A3
Authority
WO
WIPO (PCT)
Prior art keywords
dataword
register file
instruction
cpu
register
Prior art date
Application number
PCT/US2003/012137
Other languages
French (fr)
Other versions
WO2003098439A2 (en
Inventor
Marc Tremblay
Shailender Chaudhry
Quinn Jacobson
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Priority to AU2003222650A priority Critical patent/AU2003222650A1/en
Publication of WO2003098439A2 publication Critical patent/WO2003098439A2/en
Publication of WO2003098439A3 publication Critical patent/WO2003098439A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level

Abstract

One embodiment of the present invention provides a system that facilitates error correction within a register file in a central processing unit (CPU). During execution of an instruction by the CPU, the system retrieves a dataword and an associated syndrome from a source register in the register file. Next, the system uses information in the dataword and the associated syndrome to detect, and if necessary correct, an error in the dataword or associated syndrome. Note that this error detection and correction takes place in parallel with using the dataword to perform a computational operation specified by the instruction. If an error is detected, the system prevents the instruction from performing a writeback to a destination register in the register file. The system also writes a corrected dataword to the source register in the register file. Next, the system flushes the instruction pipeline, and restarts execution of the instruction so that the corrected dataword is retrieved for the computational operation.
PCT/US2003/012137 2002-05-14 2003-04-17 Method and apparatus for providing error correction within a register file of a cpu WO2003098439A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003222650A AU2003222650A1 (en) 2002-05-14 2003-04-17 Method and apparatus for providing error correction within a register file of a cpu

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/146,100 2002-05-14
US10/146,100 US7058877B2 (en) 2002-05-14 2002-05-14 Method and apparatus for providing error correction within a register file of a CPU

Publications (2)

Publication Number Publication Date
WO2003098439A2 WO2003098439A2 (en) 2003-11-27
WO2003098439A3 true WO2003098439A3 (en) 2004-03-18

Family

ID=29418735

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/012137 WO2003098439A2 (en) 2002-05-14 2003-04-17 Method and apparatus for providing error correction within a register file of a cpu

Country Status (4)

Country Link
US (1) US7058877B2 (en)
AU (1) AU2003222650A1 (en)
TW (1) TWI242120B (en)
WO (1) WO2003098439A2 (en)

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US20060156177A1 (en) * 2004-12-29 2006-07-13 Sailesh Kottapalli Method and apparatus for recovering from soft errors in register files
US8020072B2 (en) * 2006-10-25 2011-09-13 International Business Machines Corporation Method and apparatus for correcting data errors
US7689804B2 (en) * 2006-12-20 2010-03-30 Intel Corporation Selectively protecting a register file
US7865769B2 (en) * 2007-06-27 2011-01-04 International Business Machines Corporation In situ register state error recovery and restart mechanism
US8078942B2 (en) 2007-09-04 2011-12-13 Oracle America, Inc. Register error correction of speculative data in an out-of-order processor
GB2455212B (en) * 2008-01-30 2012-03-21 Ibm Method for identifying address faults of CPU status register files during read and write accesses
US8316283B2 (en) 2009-12-23 2012-11-20 Intel Corporation Hybrid error correction code (ECC) for a processor
US9329918B2 (en) 2011-12-28 2016-05-03 Intel Corporation Resilient register file circuit for dynamic variation tolerance and method of operating the same
EP2876557B1 (en) * 2013-11-22 2016-06-01 Alcatel Lucent Detecting a read access to unallocated or uninitialized memory
FR3071122B1 (en) 2017-09-14 2019-09-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives METHOD FOR EXECUTING A BINARY CODE OF A FUNCTION SECURE BY A MICROPROCESSOR
FR3071121B1 (en) 2017-09-14 2020-09-18 Commissariat Energie Atomique PROCESS FOR EXECUTION OF A BINARY CODE OF A FUNCTION SECURE BY A MICROPROCESSOR
US10621022B2 (en) 2017-10-03 2020-04-14 Nvidia Corp. System and methods for hardware-software cooperative pipeline error detection
US11409597B2 (en) 2017-10-03 2022-08-09 Nvidia Corp. System and methods for hardware-software cooperative pipeline error detection
TWI785880B (en) * 2021-07-06 2022-12-01 阿比特電子科技股份有限公司 Error detection and correction method and circuit thereof

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Non-Patent Citations (2)

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Title
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Also Published As

Publication number Publication date
US7058877B2 (en) 2006-06-06
TWI242120B (en) 2005-10-21
WO2003098439A2 (en) 2003-11-27
US20030217325A1 (en) 2003-11-20
TW200412491A (en) 2004-07-16
AU2003222650A1 (en) 2003-12-02

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