WO2003073505A1 - Integrated circuit device and method of manufacturing thereof - Google Patents

Integrated circuit device and method of manufacturing thereof Download PDF

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Publication number
WO2003073505A1
WO2003073505A1 PCT/SG2003/000040 SG0300040W WO03073505A1 WO 2003073505 A1 WO2003073505 A1 WO 2003073505A1 SG 0300040 W SG0300040 W SG 0300040W WO 03073505 A1 WO03073505 A1 WO 03073505A1
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WIPO (PCT)
Prior art keywords
wafer
die
dies
routers
contacts
Prior art date
Application number
PCT/SG2003/000040
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French (fr)
Inventor
Gautham Viswanadam
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Gautham Viswanadam
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Publication date
Application filed by Gautham Viswanadam filed Critical Gautham Viswanadam
Priority to AU2003217142A priority Critical patent/AU2003217142A1/en
Publication of WO2003073505A1 publication Critical patent/WO2003073505A1/en

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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Definitions

  • This invention relates generally to an integrated circuit (IC) device and a method of manufacturing the IC device. More particularly, this invention relates to an IC device including one die or two or more dies arranged in a stacked configuration so as to have a footprint approximately the size of a single die, and to a method of manufacturing such an IC device.
  • IC integrated circuit
  • this invention relates to an IC device including one die or two or more dies arranged in a stacked configuration so as to have a footprint approximately the size of a single die, and to a method of manufacturing such an IC device.
  • IC devices including one die or two or more dies arranged in a stacked configuration so as to have a footprint approximately the size of a single die, and to a method of manufacturing such an IC device.
  • r0002 With the miniaturization of electronic products, there is a need to also reduce the footprint of IC devices so that more of these IC devices can be packed into a given area of a substrate. Two approaches have been taken to meet such
  • Figures 1-3 show prior art IC devices with multiple dies in a stacked configuration.
  • Figure 1 shows an IC device including two dies, a first die stacked on top of a second die.
  • the first die has a footprint smaller than that of the second die.
  • the two-die stack is then attached to a pre-fabricated substrate. Bond pads on both dies are then connected to connectors of the substrate using wire bonding.
  • Such a stacked-die configuration can be extended to include a third die as shown in Figure 2.
  • Such IC devices suffer from a notable disadvantage.
  • FIG. 1 shows yet another IC device with multiple dies in a stacked configuration.
  • the footprint of such an IC device is independent of the number of dies in the stack and thus is an improvement over the IC devices in Figures 1 and 2.
  • connection pads on the different dies are interconnected by holes or vias etched through the dies that are filled with metal.
  • the dies in such an IC device need to be precisely aligned and bonded using sophisticated and expensive front-end fabrication equipment.
  • 6,040,235 discloses an IC device having a footprint approximately the size of a die of the IC device.
  • the steps for manufacturing the IC device includes: (1) providing a wafer that includes multiple dies wherein each die includes multiple connection pads, (2) sandwiching the wafer between two protective layers, (3) cutting notches through one of the protective layers along outlines of the dies to expose portions of the connection pads, (4) forming metal contacts on the surface of the notched protective layer that are electrically connected to the exposed portions of the connection pads, and (5) separating the dies to form individual dies.
  • Such a manufacturing process suffers from a number of disadvantages.
  • the step of cutting notches is sequential and therefore is time-consuming. That step also requires an accurate fixed angular shaped cutting blade for cutting the notches.
  • U.S. Patent No. 6,117,707 discloses another IC device having multiple dies similar to that disclosed in U.S. Patent No. 6,040,235. The dies are arranged in a stacked configuration. Interconnections between the dies of such an IC device are formed only after the stacks of dies are separated to form individualized IC devices. That is, the process of interconnecting the dies in a device is performed on a device level and is thus slow.
  • a method of manufacturing an integrated circuit (IC) device According to the method, a first wafer including multiple dies separated by separation zones is first provided. Each die includes connection pads on a first active side of the wafer. Cavities corresponding to the connection pads are formed along the separation zones. Routers are also formed for electrically connecting with the connection pads to route the connection pads to an interior of the corresponding cavities. Wafer material is then removed from a second side of the wafer, opposite the first side, to expose the routers in the cavities. Contacts are formed on the second side of the wafer. These contacts are electrically connected to the routers in the interior of the cavities to thereby electrically connect with the connection pads on the first side.
  • the method may further include forming a passivation layer prior to forming the routers so that the routers are separated from the dies by the passivation layer.
  • removing wafer material includes removing wafer material from a second side of the wafer, opposite the first side, to expose the passivation layer under the routers in the interior of the cavities.
  • a second passivation layer is then formed on the second side of the wafer to contact the passivation layer in the interior of the cavities.
  • portions of the passivation layers are removed from the second side of the wafer to expose the routers in the interior of the cavities.
  • the method may further include forming terminals electrically connected to the contacts.
  • forming terminals includes forming a solder mask over the passivation layer and contacts on the second side of the wafer, removing portions of the solder mask over the contacts to expose the contacts and forming solder bumps over the exposed contacts.
  • the method may further include attaching a packaging layer to the first side of the wafer after forming the routers. In such a case, separating the dies includes separating the packaging layer.
  • the method may further include providing a second wafer of dies processed in a manner similar to the first wafer to include routers that route connection pads on a first side of the second wafer to corresponding contacts on the second side of the second wafer.
  • the second wafer is then attached to the first wafer by aligning and attaching the first side of the second wafer to the second side of the first wafer to thereby electrically connect connection pads on the dies of the second wafer to the contacts on the second side of corresponding dies of the first wafer to define stacks of dies.
  • the second side of the second wafer is processed in a similar manner to the first wafer to produce contacts thereon.
  • separating the dies includes separating the stacks of dies to produce individualized integrated circuit devices, each of which includes a stack of dies.
  • the method further includes providing at least one intermediate wafer interconnected between the first wafer and the second wafer.
  • an integrated circuit (IC) device manufactured according to the method described above.
  • This IC device includes a first die having multiple connection pads on a first active side of the first die and multiple contacts on a second side of the first die, opposite the first side.
  • the IC device also includes multiple routers, each of which electrically connects a connection pad to a corresponding contact, wherein the routers run along recesses formed on at least one sidewall of the first die.
  • the recesses are formed on an upper portion of the sidewall adjacent to the first side of the die, leaving a lower portion of the sidewall adjacent to the second side of the die substantially planar.
  • the IC device further includes a passivation layer on the first side of the first die between the die and the routers.
  • the IC device further includes a second passivation layer on the second side of the first die between the die and the routers.
  • the IC device further includes terminals electrically connected to the contacts. In such a case, the IC device may further include a solder mask on the second side of the first die covering areas on the second side exposed by the terminals.
  • the IC device may further include a packaging layer attached to the first side of the die.
  • the IC device may further include a second die having routers that route connection pads on a first side of the second die to contacts on a second side, opposite the first side, of the second die.
  • the first side of the second die is attached to the second side of the first die to thereby electrically connect connection pads on the second die to the contacts on the second side of the first die to define a stack of dies.
  • the IC device may further include at least one intermediate die interconnected between the first die and the second die.
  • Figure 1 is a sectioned drawing of a prior art IC device having two dies in a stacked configuration and connected to a substrate using wire bonding;
  • Figure 2 is a sectioned drawing of a prior art IC device having three dies, stacked and connected to a substrate in a similar manner as the IC device in Figure 1 ;
  • Figure 3 is a sectioned drawing of another prior art IC device having multiple dies in a stacked configuration and interconnected using metal-filled through holes;
  • Figure 4 is a flow diagram of a sequence of steps for manufacturing an IC device according to an embodiment of the present invention.
  • Figure 5 is a drawing of a wafer and a packaging layer for attaching to the wafer according to the sequence in Figure 4;
  • Figure 6 is an isometric drawing of an active surface of a portion of the wafer in Figure 5 showing cavities formed according to the sequence in Figure 4;
  • Figures 7A-7O are sectioned drawings, taken along a line X-X in Figure 6, showing two adjacent dies of the wafer at different stages of manufacturing according to the sequence in Figure 4;
  • Figure 8 is an isometric drawing of a portion of the IC device manufactured according to the sequence in Figure 4; and Figures 9A-9C are sectioned drawings similar to Figures 7A-7O showing adjacent dies of two stacked wafers at different stages of manufacturing according to an extension of the sequence in Figure 4.
  • Figure 4 is a flow diagram showing a sequence 2 of steps for manufacturing an integrated circuit (IC) device 4 ( Figures 7O) according to an embodiment of the present invention.
  • the sequence 2 starts in a PROVIDE WAFER step 6, wherein a wafer 8 ( Figure 5) including an array of finished dies
  • the wafer 8 may be a six, eight or twelve-inch wafer. Separation zones, generally known as scribe lines
  • Each die 10 has multiple bond pads or connection pads 14 ( Figure 6) on a first active surface 12 of the die 10. These connection pads 14 are electrically connected to an electronic circuitry (not shown) formed in each die 10.
  • a side of the wafer 8, which defines the first active surfaces 12 of the dies 10, is referred herein as the first active side 16 of the wafer 8.
  • the other side of the wafer 8, opposite the first side 16, is referred to herein as the second side 18 of the wafer 8.
  • Figure 7A shows a cross sectional view of two adjacent dies 10 of the wafer 8 prior to processing.
  • the sequence 2 next proceeds to a FORM CAVITiES step 20, wherein cavities 22 are formed adjacent to corresponding connection pads 14 along the scribe lines 11 as shown in Figures 6 and 7B.
  • the cavities 22 have a depth in the range of 10-200 microns and preferably have a square opening on a surface of the first side 16 of the wafer 8, with each side of the square opening measuring between 75-200 microns. Cavity openings of a circular, rectangular or any other shape may also be used.
  • These cavities 22 can be formed using . any conventional technique, such as photolithography followed by etching, or direct laser scoring.
  • the cavities 22 extend deeper into the first side 16 of the wafer 8 than the connection pads 14.
  • connection pads 14 of two adjacent dies 10 share a single cavity 22 in the scribe line 11 separating the two dies 10. It is possible to have a single cavity 22 for each corresponding connection pad 14.
  • the sequence 2 next proceeds to a first FORM PROTECTIVE LAYER step 24, wherein a passivation layer 26 is formed on the active surface 12 of the dies 10.
  • a passivation layer 26 is preferably formed by first depositing a layer of silicon nitride, silicon dioxide, benzo cyclo butene (BCB) or any other suitable insulating material onto the entire surface of the first side 16 of the wafer 8 according to a DEPOSIT LAYER step 28.
  • FIG. 7C shows the surface on the first side 16 of the wafer 8 covered by the passivation layer 26.
  • the passivation layer 26 also extends into the cavities 22 to cover the interior surfaces of the cavities 22.
  • portions of the passivation layer 26 over the connection pads 14 are removed using conventional techniques, such as photolithography and etching, in a REMOVE PASSIVATION LAYER PORTIONS step 30 to expose the connection pads 14.
  • Figure 7D shows the passivation. layer covered dies 10 after such a step 30.
  • a layer 32 of metal such as aluminum is deposited over the passivation layer covered surface of the wafer 8 in a FORM ROUTERS step 34.
  • the metal layer 32 is deposited using any conventional technique, such as sputter deposition, to cover the surface of the first side 16 of the wafer 8.
  • the layer 32 of metal covers the exposed surfaces 36 of the connection pads 14 and extends into the cavities 22 to also cover the interior surfaces of the cavities 22.
  • the metal layer 32 is then patterned, again, using. any conventional technique, such as photolithography patterning to form mutually electrically insulated interconnections or routers 38 that route the connection pads 14 to the interior of their corresponding cavities 22 as shown in Figure 7E.
  • these routers 38 are treated, for example by plating with nickel or copper, to increase their thickness to about 3-5 microns.
  • the metal layer 32 may also be of a metal alloy in the form of a paste that is screen printed as routers 38.
  • the sequence 2 next proceeds to an APPLY EPOXY step 42, wherein an epoxy layer 44 is applied, for example by spin-coating or screen- printing, onto the router patterned surface of the wafer 8, as shown in Figure 7F.
  • a packaging layer 46 such as of glass, alumina, beryllium, sapphire, ceramic, silicon, germanium or other suitable materials, is attached to the epoxy layer 44 in an ATTACH PACKAGING LAYER step 48.
  • the epoxy layer may be required to be patterned using lithography when manufacturing optically sensitive devices.
  • the epoxy layer 44 cures to rigidly bond the packaging layer 46 to the wafer 8 as shown in Figure 7G. [0027] After attachment of the packaging layer 46, wafer material on the second side 18 of the wafer 8 is removed in a REMOVE WAFER MATERIAL step 50.
  • the wafer material on the second side 18 of the wafer 8 is preferably first ground, by backgrinding and/or polishing in a GRIND WAFER step 52, to reduce the thickness of the wafer 8 to leave about 10 - 50 microns thick (shown as distance "d" in Figure 7G) of wafer material between the ground surface on the second side 18 of the wafer 8 and the bottom of the cavities 22. Thereafter, the 10 - 50 micron thick wafer material on the second side 18 of the wafer 8 is preferably etched, in a ETCH WAFER step 54, to further remove the remaining wafer material until the passivation layer 26 at the bottom of the cavities 22 is exposed as shown in Figure 7H.
  • the etched surface at the second side 18 of the wafer 8 is coated with a second passivation layer 56 in a second FORM PROTECTION LAYER step 58 as shown in Figure 71.
  • This second passivation layer 56 comes into contact with the exposed passivation layer 26 in the cavities 22.
  • Portions of the passivation layers 26, 56 on the second side of the wafer covering the metal layer 32 in the cavities 22 are then removed in a second REMOVE PASSIVATION LAYER PORTIONS step 60 to expose the metal layer 32 in the cavities 22 as shown in Figure 7J.
  • a FORM CONTACTS step 62 wherein mutually electrically insulated contacts 70 (Figures 7L) are formed on the processed second side 18 of the wafer 8. These contacts 70 are electrically connected to the metal layer 32 in the corresponding cavities 22 to thereby route the connection pads 14 on the first side 16 to the second side 18 of the wafer.
  • a step 62 preferably includes first forming, such as by depositing, a second metal layer 64 over the passivation layer 56 at the second side 18 of the wafer in a FORM METAL LAYER step 66.
  • Figure 7K shows the second metal layer 64 covering the surface of the second side 18 of the wafer 8.
  • This second metal layer 64 comes into contact with the metal layer 32 in the cavities 22 to thereby electrically connect therewith. Thereafter, the second metal layer 64 is patterned in a PATTERNING METAL LAYER step 68 using any conventional technique to define mutually electrically insulated routers that functions as contacts 70 on the surface of the second side 18 of the wafer 8. In this manner, the connection pads 38 on the first side 16 of the wafer 8 are electrically routed to the contacts 70 on the second side 18 of the wafer 8 as shown in Figure 7L.
  • the contacts 70 are coated with a layer of nickel followed by a layer of gold using an under bump metallization (UBM) process.
  • UBM under bump metallization
  • a FORM TERMINALS step 72 wherein the wafer 8 is further processed to include electrical terminals such as solder bumps 74 ( Figure 7N).
  • this step 72 includes a FORM SOLDER MASK step 76, wherein the surface on the second side 18 of the wafer is coated with a layer of solder mask 78 or a third passivation layer, preferably 1 to 25 micron thick as shown in Figure 7M. Portions of the solder mask 78 or the third passivation layer covering the contacts 70 are next removed using any conventional technique in a REMOVE SOLDER MASK PORTIONS step 80 to expose the contacts 70.
  • solder bumps 74 are then formed in a FORM SOLDER BUMPS step 82 over the contacts 70 on the second side 18 of the wafer 8 to function as terminals for the dies 10, as shown in Figure 7N.
  • the sequence 2 finally ends in a SEPARATE DIES step 84, wherein the wafer 8 with the attached packaging layer 46 is diced along the scribe lines 11 , through the cavities 22, to produce individualized IC devices 4 ready for mounting on a substrate (not shown).
  • Figure 7O shows two resultant individualized IC devices 4. [0031] It should be noted that the IC device 4 produced according to the sequence 2 is only one possible embodiment of the present invention.
  • the IC device 86 includes a single finished die 10.
  • This single die 10 includes multiple connection pads 14 on a first active side 16 thereof.
  • the single die 10 further includes multiple contacts 70, on a second side 18 of the die 10, opposite the first side 16.
  • the number of contacts 70 may be as many as a hundred for a die having a footprint area of as small as 25 mm 2 .
  • the single die 10 includes a set of mutually electrically insulated routers 38, each of which electrically connects a connection pad 14 to a corresponding contact 70.
  • These routers 38 run from the surface of the first side 16 of the die 10, along recesses 88 formed on at least one sidewall 90 of the die 10, to the second side 18 of the die 10. These recesses 88 are formed on an upper portion of the sidewall 90 adjacent to the first side 16. A lower portion of the sidewall, adjacent to the second side 18, is not recessed and is thus substantially planar. It should be noted that the contacts 70 need not be directly aligned with the corresponding connection pads 14 as shown in Figure 8. Such an IC device 86, without any further processing, is suitable for direct chip attach (DCA). [0032] This IC device 86 may preferably include a passivation layer 26 on the first side 16 of the die 10 between the die surface and the routers 38 as shown in Figure 7E.
  • the IC device 86 may also preferably include another passivation layer 56 on the second side 18 of the die 10 between the die 10 and the contacts 70 as shown in Figure 7L.
  • the IC device 86 includes terminals electrically connected to the contacts 70. These terminals may for example be solder bumps 74 as shown in Figure 7N, in which case, the surface of the second side 18 of the die is pre-coated with a layer of solder mask 78 or yet another passivation layer, portions of which are subsequently removed for forming the solder bumps 74.
  • the IC device 86 may also preferably include an outermost packaging layer 46 attached to the first side 16 of the die 10 as shown in Figure 7G if the die needs to be mechanically strengthened or protected.
  • FIG. 9A and 9B show electrically interconnected wafers, including a first wafer 94 and a second wafer 96, after a number of intermediate steps in the modified sequence.
  • the first wafer 94 and the second wafer 96 should preferably be of the same material or materials of about the same thermal coefficient of expansion.
  • Each of the wafers 94, 96 includes two or more dies 10 arranged in a stacked configuration.
  • the first wafer 94 includes two adjacent dies 10 manufactured according to selected steps in the sequence 2 to result in the structure shown in Figure 7L.
  • the second wafer 96 includes another two dies 10 manufactured according to selected steps in the sequence 2 to result in a structure similar to that shown in Figure 7E.
  • the routers 38 on the first side 16 of the second wafer 96 are aligned and electrically connected with the contacts 70 on the second side 18 of the first wafer 96.
  • the electrical connection between the routers 38 and the contacts 70 may be effected by anodic bonding, frit glass bonding, application of an anisotropic conductive film (ACF) or other bonding techniques.
  • ACF anisotropic conductive film
  • the second side 18 of the second wafer 96 is then processed according to further selected steps in the sequence 2 to result in the stacked structure shown in Figure 9B.
  • the stack structure is separated according to the SEPARATE DIES step 84 in the sequence 2 to result in the individualized stacked-die IC devices 92 as shown in Figure 9C.
  • the IC device 92 includes a first die 10 and a second die 10 in a stacked configuration.
  • the first die 10 is similar to the IC device 4 ( Figure 7O) without the solder mask 78 and solder bumps 74.
  • the second die 10 is similar to the IC device 86 shown in Figure 8.
  • the second die 10 has multiple connection pads 14 on a first active side 16 that are routed to contacts 70 on a second side 18 of the second die 10, opposite the first side 16.
  • the first side 16 of the second die 10 is attached to the second side 18 of the preceding first die 10 to thereby electrically connect the routers 38. on the second die 10 to the contacts 70 on the second side 18 of the first die 10 to define a stack of dies.
  • the IC device 92 includes terminals, such as solder bumps 74 on the second side 18 of the second die 10. As previously described, there may be as many as a hundred solder bumps 74 for a die having a footprint area of as small as 25 mm 2 . For such a die, the number of interconnections defined by such connections of routers 38 and contacts 70 between the dies 10 may even reach a number larger than the number of solder bumps 74. It should be appreciated that such an IC device 92 may include three or more dies 10, including a top die, a bottom die and one or more intermediate dies interconnected between the top die and the bottom die. The one or more intermediate dies are similar to the IC device shown in Figure 8.
  • an IC device with 4 or 5 dies may be less than 1 mm thick.
  • the dies of a stacked-die IC device 92 may be of the same function or of different functions.
  • An example of a stacked-die IC device having dies of different functions includes a processor die, a memory die and an image sensor die in a stacked configuration to produce a system-on-a-chip (SOC) device.
  • SOC system-on-a-chip
  • These stacked-die IC devices may be used for implementing optical type of devices, such as image sensors, as well as non-optical type of devices, such as micro electro and mechanical system (MEMS) and surface acoustic wave (SAW) devices.
  • MEMS micro electro and mechanical system
  • SAW surface acoustic wave
  • the IC device has a small footprint no larger than the size of the die. Additional dies may also be provided in a stacked configuration to, for example, increase the functionality of the IC device without increasing the size of its footprint.
  • the passivation layer of the IC device also covers substantially all active surfaces of a die and therefore provides a better seal of the die than in prior art devices.
  • expensive flip chip bonders are not required for mounting such an IC device to a substrate; standard die bonding machines can be used to pick and place such an IC device.
  • the terminals can be arranged according to chip-scale package (CSP) pitches so that under fill material is not required when mounting the IC device to a substrate.
  • CSP chip-scale package
  • the method for producing the IC device requires less process steps as compared to that required for prior art IC devices.
  • the method allows for the use of a low-cost screen printing method for solder bumping.
  • the method also allows for the use of the commonly-available lead-free solder paste for solder bumping.
  • the method is flexible and thus modifiable for manufacturing aluminum and copper device.
  • the method further allows for forming of integrated passives, such as resistors, capacitors and inductors, on the second side of a die prior to interconnection with another die or mounting onto a substrate.
  • integrated passives such as resistors, capacitors and inductors
  • the method also allows fine pitch bumping for high input-output (IO) count, optically sensitive devices that may accept underfill materials at the board assembly levels.
  • the present invention is described as implemented in the above-described embodiments, it is not to be construed to be limited as such.
  • the method can also be used to manufacture inductor coils for high Q, radio frequency (RF) applications.
  • each die is formed to include one or more turns of a coil and several of such dies are interconnected as described to form the complete coil.
  • the REMOVE WAFER MATERIAL step can be implemented entirely by etching, i.e., without backgrinding and/or polishing. In such a case, the method has the added advantage that it can be performed entirely in a clean room environment.

Abstract

A method of manufacturing an integrated circuit (IC) device is disclosed. A wafer including multiple dies is processed to form cavities along scribe lines that separate the dies. The cavities correspond to connection pads of the dies. Routers are formed to electrically route a connection pad to the interior of its corresponding cavity. Wafer material is then removed from a second side of the wafer, opposite the first side, to expose the routers in the cavities. Contacts are formed on the second side that electrically connect with the routers in the interior of the cavities to thereby electrically connect with the connection pads on the first side. The dies are separated along the scribe lines to produce individualized dies. An IC device including a separated die is also disclosed.

Description

INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING
THEREOF
BACKGROUND [0001] This invention relates generally to an integrated circuit (IC) device and a method of manufacturing the IC device. More particularly, this invention relates to an IC device including one die or two or more dies arranged in a stacked configuration so as to have a footprint approximately the size of a single die, and to a method of manufacturing such an IC device. r0002] With the miniaturization of electronic products, there is a need to also reduce the footprint of IC devices so that more of these IC devices can be packed into a given area of a substrate. Two approaches have been taken to meet such a need. A first approach is to reduce the size of packaging of existing IC devices. The second approach is focused on increasing the functionalities provided by each IC device, for example to form system-on-a-chip (SOC) and system-in-package (SIP) devices. r0003] Figures 1-3 show prior art IC devices with multiple dies in a stacked configuration. Figure 1 shows an IC device including two dies, a first die stacked on top of a second die. The first die has a footprint smaller than that of the second die. The two-die stack is then attached to a pre-fabricated substrate. Bond pads on both dies are then connected to connectors of the substrate using wire bonding. Such a stacked-die configuration can be extended to include a third die as shown in Figure 2. Such IC devices suffer from a notable disadvantage. The largest die at the bottom of the stack of dies governs the size of the footprint of the IC device. The more dies there are, the larger will be the size of the footprint of the IC device. r00041 Figure 3 shows yet another IC device with multiple dies in a stacked configuration. The footprint of such an IC device is independent of the number of dies in the stack and thus is an improvement over the IC devices in Figures 1 and 2. Instead of interconnecting the different dies by wire bonding, connection pads on the different dies are interconnected by holes or vias etched through the dies that are filled with metal. The dies in such an IC device need to be precisely aligned and bonded using sophisticated and expensive front-end fabrication equipment. 1O0051 U.S. Patent No. 6,040,235 discloses an IC device having a footprint approximately the size of a die of the IC device. The steps for manufacturing the IC device includes: (1) providing a wafer that includes multiple dies wherein each die includes multiple connection pads, (2) sandwiching the wafer between two protective layers, (3) cutting notches through one of the protective layers along outlines of the dies to expose portions of the connection pads, (4) forming metal contacts on the surface of the notched protective layer that are electrically connected to the exposed portions of the connection pads, and (5) separating the dies to form individual dies. Such a manufacturing process suffers from a number of disadvantages. The step of cutting notches is sequential and therefore is time-consuming. That step also requires an accurate fixed angular shaped cutting blade for cutting the notches. As cutting produces debris, the cutting step has to be performed outside of a clean room. A cut wafer is then transported into the clean room for further processing, making-handling of the wafer cumbersome. The two protective layers on a resultant die also make it costly. rOOOβl U.S. Patent No. 6,117,707 discloses another IC device having multiple dies similar to that disclosed in U.S. Patent No. 6,040,235. The dies are arranged in a stacked configuration. Interconnections between the dies of such an IC device are formed only after the stacks of dies are separated to form individualized IC devices. That is, the process of interconnecting the dies in a device is performed on a device level and is thus slow.
SUMMARY [0007] According to an aspect of the present invention, there is provided a method of manufacturing an integrated circuit (IC) device. According to the method, a first wafer including multiple dies separated by separation zones is first provided. Each die includes connection pads on a first active side of the wafer. Cavities corresponding to the connection pads are formed along the separation zones. Routers are also formed for electrically connecting with the connection pads to route the connection pads to an interior of the corresponding cavities. Wafer material is then removed from a second side of the wafer, opposite the first side, to expose the routers in the cavities. Contacts are formed on the second side of the wafer. These contacts are electrically connected to the routers in the interior of the cavities to thereby electrically connect with the connection pads on the first side. The dies are separated along the separation zones to produce individualized dies, each of which serves as an IC device. [0008] Preferably, the method may further include forming a passivation layer prior to forming the routers so that the routers are separated from the dies by the passivation layer.
[0009] Preferably, removing wafer material includes removing wafer material from a second side of the wafer, opposite the first side, to expose the passivation layer under the routers in the interior of the cavities. A second passivation layer is then formed on the second side of the wafer to contact the passivation layer in the interior of the cavities. Thereafter, portions of the passivation layers are removed from the second side of the wafer to expose the routers in the interior of the cavities. [0010] The method may further include forming terminals electrically connected to the contacts. Preferably, forming terminals includes forming a solder mask over the passivation layer and contacts on the second side of the wafer, removing portions of the solder mask over the contacts to expose the contacts and forming solder bumps over the exposed contacts. [0011] Preferably, the method may further include attaching a packaging layer to the first side of the wafer after forming the routers. In such a case, separating the dies includes separating the packaging layer. [0012] The method may further include providing a second wafer of dies processed in a manner similar to the first wafer to include routers that route connection pads on a first side of the second wafer to corresponding contacts on the second side of the second wafer. The second wafer is then attached to the first wafer by aligning and attaching the first side of the second wafer to the second side of the first wafer to thereby electrically connect connection pads on the dies of the second wafer to the contacts on the second side of corresponding dies of the first wafer to define stacks of dies. The second side of the second wafer is processed in a similar manner to the first wafer to produce contacts thereon. In such a case, separating the dies includes separating the stacks of dies to produce individualized integrated circuit devices, each of which includes a stack of dies. [0013] Preferably, the method further includes providing at least one intermediate wafer interconnected between the first wafer and the second wafer. [0014] According to another aspect of the present invention, there is provided an integrated circuit (IC) device manufactured according to the method described above. This IC device includes a first die having multiple connection pads on a first active side of the first die and multiple contacts on a second side of the first die, opposite the first side. The IC device also includes multiple routers, each of which electrically connects a connection pad to a corresponding contact, wherein the routers run along recesses formed on at least one sidewall of the first die. [0015] Preferably, the recesses are formed on an upper portion of the sidewall adjacent to the first side of the die, leaving a lower portion of the sidewall adjacent to the second side of the die substantially planar. [0016] Preferably, the IC device further includes a passivation layer on the first side of the first die between the die and the routers. [0017] Preferably, the IC device further includes a second passivation layer on the second side of the first die between the die and the routers. [0018] Preferably, the IC device further includes terminals electrically connected to the contacts. In such a case, the IC device may further include a solder mask on the second side of the first die covering areas on the second side exposed by the terminals.
[0019] Preferably, the IC device may further include a packaging layer attached to the first side of the die.
[0020] Preferably, the IC device may further include a second die having routers that route connection pads on a first side of the second die to contacts on a second side, opposite the first side, of the second die. The first side of the second die is attached to the second side of the first die to thereby electrically connect connection pads on the second die to the contacts on the second side of the first die to define a stack of dies. The IC device may further include at least one intermediate die interconnected between the first die and the second die.
BRIEF DESCRIPTION OF DRAWINGS
[0021] The invention will be better understood with reference to the drawings, in which: Figure 1 is a sectioned drawing of a prior art IC device having two dies in a stacked configuration and connected to a substrate using wire bonding;
Figure 2 is a sectioned drawing of a prior art IC device having three dies, stacked and connected to a substrate in a similar manner as the IC device in Figure 1 ;
Figure 3 is a sectioned drawing of another prior art IC device having multiple dies in a stacked configuration and interconnected using metal-filled through holes;
Figure 4 is a flow diagram of a sequence of steps for manufacturing an IC device according to an embodiment of the present invention;
Figure 5 is a drawing of a wafer and a packaging layer for attaching to the wafer according to the sequence in Figure 4;
Figure 6 is an isometric drawing of an active surface of a portion of the wafer in Figure 5 showing cavities formed according to the sequence in Figure 4; Figures 7A-7O are sectioned drawings, taken along a line X-X in Figure 6, showing two adjacent dies of the wafer at different stages of manufacturing according to the sequence in Figure 4;
Figure 8 is an isometric drawing of a portion of the IC device manufactured according to the sequence in Figure 4; and Figures 9A-9C are sectioned drawings similar to Figures 7A-7O showing adjacent dies of two stacked wafers at different stages of manufacturing according to an extension of the sequence in Figure 4.
DETAILED DESCRIPTION [0022] Figure 4 is a flow diagram showing a sequence 2 of steps for manufacturing an integrated circuit (IC) device 4 (Figures 7O) according to an embodiment of the present invention. The sequence 2 starts in a PROVIDE WAFER step 6, wherein a wafer 8 (Figure 5) including an array of finished dies
10 formed therein by conventional techniques is provided. The wafer 8 may be a six, eight or twelve-inch wafer. Separation zones, generally known as scribe lines
11 that are typically more than 100 microns wide, separate the dies 10. Each die 10 has multiple bond pads or connection pads 14 (Figure 6) on a first active surface 12 of the die 10. These connection pads 14 are electrically connected to an electronic circuitry (not shown) formed in each die 10. A side of the wafer 8, which defines the first active surfaces 12 of the dies 10, is referred herein as the first active side 16 of the wafer 8. The other side of the wafer 8, opposite the first side 16, is referred to herein as the second side 18 of the wafer 8. Figure 7A shows a cross sectional view of two adjacent dies 10 of the wafer 8 prior to processing.
[0023] The sequence 2 next proceeds to a FORM CAVITiES step 20, wherein cavities 22 are formed adjacent to corresponding connection pads 14 along the scribe lines 11 as shown in Figures 6 and 7B. The cavities 22 have a depth in the range of 10-200 microns and preferably have a square opening on a surface of the first side 16 of the wafer 8, with each side of the square opening measuring between 75-200 microns. Cavity openings of a circular, rectangular or any other shape may also be used. These cavities 22 can be formed using . any conventional technique, such as photolithography followed by etching, or direct laser scoring. The cavities 22 extend deeper into the first side 16 of the wafer 8 than the connection pads 14. In this embodiment, two or more connection pads 14 of two adjacent dies 10 share a single cavity 22 in the scribe line 11 separating the two dies 10. It is possible to have a single cavity 22 for each corresponding connection pad 14. [0024] The sequence 2 next proceeds to a first FORM PROTECTIVE LAYER step 24, wherein a passivation layer 26 is formed on the active surface 12 of the dies 10. Such a passivation layer 26 is preferably formed by first depositing a layer of silicon nitride, silicon dioxide, benzo cyclo butene (BCB) or any other suitable insulating material onto the entire surface of the first side 16 of the wafer 8 according to a DEPOSIT LAYER step 28. Any appropriate passivation process having an operating temperature between 50 to 450 degree Celcius may be used in this step 28, depending on the application of the IC device. Figure 7C shows the surface on the first side 16 of the wafer 8 covered by the passivation layer 26. The passivation layer 26 also extends into the cavities 22 to cover the interior surfaces of the cavities 22. After the passivation layer 26 has been deposited, portions of the passivation layer 26 over the connection pads 14 are removed using conventional techniques, such as photolithography and etching, in a REMOVE PASSIVATION LAYER PORTIONS step 30 to expose the connection pads 14. Figure 7D shows the passivation. layer covered dies 10 after such a step 30. [0025] Next, a layer 32 of metal, such as aluminum, is deposited over the passivation layer covered surface of the wafer 8 in a FORM ROUTERS step 34. The metal layer 32 is deposited using any conventional technique, such as sputter deposition, to cover the surface of the first side 16 of the wafer 8. The layer 32 of metal covers the exposed surfaces 36 of the connection pads 14 and extends into the cavities 22 to also cover the interior surfaces of the cavities 22. The metal layer 32 is then patterned, again, using. any conventional technique, such as photolithography patterning to form mutually electrically insulated interconnections or routers 38 that route the connection pads 14 to the interior of their corresponding cavities 22 as shown in Figure 7E. Preferably, these routers 38 are treated, for example by plating with nickel or copper, to increase their thickness to about 3-5 microns. Depending on the application of the IC device, the metal layer 32 may also be of a metal alloy in the form of a paste that is screen printed as routers 38. [0026] Preferably, the sequence 2 next proceeds to an APPLY EPOXY step 42, wherein an epoxy layer 44 is applied, for example by spin-coating or screen- printing, onto the router patterned surface of the wafer 8, as shown in Figure 7F. After the epoxy layer 44 is applied, a packaging layer 46, such as of glass, alumina, beryllium, sapphire, ceramic, silicon, germanium or other suitable materials, is attached to the epoxy layer 44 in an ATTACH PACKAGING LAYER step 48. The epoxy layer may be required to be patterned using lithography when manufacturing optically sensitive devices. The epoxy layer 44 cures to rigidly bond the packaging layer 46 to the wafer 8 as shown in Figure 7G. [0027] After attachment of the packaging layer 46, wafer material on the second side 18 of the wafer 8 is removed in a REMOVE WAFER MATERIAL step 50. In this step 50, the wafer material on the second side 18 of the wafer 8 is preferably first ground, by backgrinding and/or polishing in a GRIND WAFER step 52, to reduce the thickness of the wafer 8 to leave about 10 - 50 microns thick (shown as distance "d" in Figure 7G) of wafer material between the ground surface on the second side 18 of the wafer 8 and the bottom of the cavities 22. Thereafter, the 10 - 50 micron thick wafer material on the second side 18 of the wafer 8 is preferably etched, in a ETCH WAFER step 54, to further remove the remaining wafer material until the passivation layer 26 at the bottom of the cavities 22 is exposed as shown in Figure 7H. [0028] Next, the etched surface at the second side 18 of the wafer 8 is coated with a second passivation layer 56 in a second FORM PROTECTION LAYER step 58 as shown in Figure 71. This second passivation layer 56 comes into contact with the exposed passivation layer 26 in the cavities 22. Portions of the passivation layers 26, 56 on the second side of the wafer covering the metal layer 32 in the cavities 22 are then removed in a second REMOVE PASSIVATION LAYER PORTIONS step 60 to expose the metal layer 32 in the cavities 22 as shown in Figure 7J. [0029] The sequence 2 next proceeds to a FORM CONTACTS step 62, wherein mutually electrically insulated contacts 70 (Figures 7L) are formed on the processed second side 18 of the wafer 8. These contacts 70 are electrically connected to the metal layer 32 in the corresponding cavities 22 to thereby route the connection pads 14 on the first side 16 to the second side 18 of the wafer. Such a step 62 preferably includes first forming, such as by depositing, a second metal layer 64 over the passivation layer 56 at the second side 18 of the wafer in a FORM METAL LAYER step 66. Figure 7K shows the second metal layer 64 covering the surface of the second side 18 of the wafer 8. This second metal layer 64 comes into contact with the metal layer 32 in the cavities 22 to thereby electrically connect therewith. Thereafter, the second metal layer 64 is patterned in a PATTERNING METAL LAYER step 68 using any conventional technique to define mutually electrically insulated routers that functions as contacts 70 on the surface of the second side 18 of the wafer 8. In this manner, the connection pads 38 on the first side 16 of the wafer 8 are electrically routed to the contacts 70 on the second side 18 of the wafer 8 as shown in Figure 7L. Preferably, the contacts 70 are coated with a layer of nickel followed by a layer of gold using an under bump metallization (UBM) process.
[0030] The sequence 2 next proceeds to a FORM TERMINALS step 72, wherein the wafer 8 is further processed to include electrical terminals such as solder bumps 74 (Figure 7N). Preferably, this step 72 includes a FORM SOLDER MASK step 76, wherein the surface on the second side 18 of the wafer is coated with a layer of solder mask 78 or a third passivation layer, preferably 1 to 25 micron thick as shown in Figure 7M. Portions of the solder mask 78 or the third passivation layer covering the contacts 70 are next removed using any conventional technique in a REMOVE SOLDER MASK PORTIONS step 80 to expose the contacts 70. The solder bumps 74 are then formed in a FORM SOLDER BUMPS step 82 over the contacts 70 on the second side 18 of the wafer 8 to function as terminals for the dies 10, as shown in Figure 7N. The sequence 2 finally ends in a SEPARATE DIES step 84, wherein the wafer 8 with the attached packaging layer 46 is diced along the scribe lines 11 , through the cavities 22, to produce individualized IC devices 4 ready for mounting on a substrate (not shown). Figure 7O shows two resultant individualized IC devices 4. [0031] It should be noted that the IC device 4 produced according to the sequence 2 is only one possible embodiment of the present invention. IC devices, such as IC device 86 shown in Figure 8, according to other embodiments can also be manufactured by doing away with some steps in the sequence 2. The structure of the IC device 86 produced according to a modified sequence is next described. The IC device 86 includes a single finished die 10. This single die 10 includes multiple connection pads 14 on a first active side 16 thereof. The single die 10 further includes multiple contacts 70, on a second side 18 of the die 10, opposite the first side 16. The number of contacts 70 may be as many as a hundred for a die having a footprint area of as small as 25 mm2. The single die 10 includes a set of mutually electrically insulated routers 38, each of which electrically connects a connection pad 14 to a corresponding contact 70. These routers 38 run from the surface of the first side 16 of the die 10, along recesses 88 formed on at least one sidewall 90 of the die 10, to the second side 18 of the die 10. These recesses 88 are formed on an upper portion of the sidewall 90 adjacent to the first side 16. A lower portion of the sidewall, adjacent to the second side 18, is not recessed and is thus substantially planar. It should be noted that the contacts 70 need not be directly aligned with the corresponding connection pads 14 as shown in Figure 8. Such an IC device 86, without any further processing, is suitable for direct chip attach (DCA). [0032] This IC device 86 may preferably include a passivation layer 26 on the first side 16 of the die 10 between the die surface and the routers 38 as shown in Figure 7E. The IC device 86 may also preferably include another passivation layer 56 on the second side 18 of the die 10 between the die 10 and the contacts 70 as shown in Figure 7L. Preferably, the IC device 86 includes terminals electrically connected to the contacts 70. These terminals may for example be solder bumps 74 as shown in Figure 7N, in which case, the surface of the second side 18 of the die is pre-coated with a layer of solder mask 78 or yet another passivation layer, portions of which are subsequently removed for forming the solder bumps 74. The IC device 86 may also preferably include an outermost packaging layer 46 attached to the first side 16 of the die 10 as shown in Figure 7G if the die needs to be mechanically strengthened or protected. [0033] A modified sequence (not shown), involving steps from the sequence 2, for manufacturing an IC device 92 (Figure 9C) having a stack of dies 10 is next described. Figures 9A and 9B show electrically interconnected wafers, including a first wafer 94 and a second wafer 96, after a number of intermediate steps in the modified sequence. The first wafer 94 and the second wafer 96 should preferably be of the same material or materials of about the same thermal coefficient of expansion. Each of the wafers 94, 96 includes two or more dies 10 arranged in a stacked configuration. The first wafer 94 includes two adjacent dies 10 manufactured according to selected steps in the sequence 2 to result in the structure shown in Figure 7L. The second wafer 96 includes another two dies 10 manufactured according to selected steps in the sequence 2 to result in a structure similar to that shown in Figure 7E. The routers 38 on the first side 16 of the second wafer 96 are aligned and electrically connected with the contacts 70 on the second side 18 of the first wafer 96. The electrical connection between the routers 38 and the contacts 70 may be effected by anodic bonding, frit glass bonding, application of an anisotropic conductive film (ACF) or other bonding techniques. The second side 18 of the second wafer 96 is then processed according to further selected steps in the sequence 2 to result in the stacked structure shown in Figure 9B. Finally, the stack structure is separated according to the SEPARATE DIES step 84 in the sequence 2 to result in the individualized stacked-die IC devices 92 as shown in Figure 9C.
[0034] Accordingly, the IC device 92 includes a first die 10 and a second die 10 in a stacked configuration. The first die 10 is similar to the IC device 4 (Figure 7O) without the solder mask 78 and solder bumps 74. The second die 10 is similar to the IC device 86 shown in Figure 8. As previously described, the second die 10 has multiple connection pads 14 on a first active side 16 that are routed to contacts 70 on a second side 18 of the second die 10, opposite the first side 16. The first side 16 of the second die 10 is attached to the second side 18 of the preceding first die 10 to thereby electrically connect the routers 38. on the second die 10 to the contacts 70 on the second side 18 of the first die 10 to define a stack of dies. The IC device 92 includes terminals, such as solder bumps 74 on the second side 18 of the second die 10. As previously described, there may be as many as a hundred solder bumps 74 for a die having a footprint area of as small as 25 mm2. For such a die, the number of interconnections defined by such connections of routers 38 and contacts 70 between the dies 10 may even reach a number larger than the number of solder bumps 74. It should be appreciated that such an IC device 92 may include three or more dies 10, including a top die, a bottom die and one or more intermediate dies interconnected between the top die and the bottom die. The one or more intermediate dies are similar to the IC device shown in Figure 8. With the reduction of thickness of each die according to the sequence 2, an IC device with 4 or 5 dies may be less than 1 mm thick. [0035] The dies of a stacked-die IC device 92 may be of the same function or of different functions. An example of a stacked-die IC device having dies of different functions includes a processor die, a memory die and an image sensor die in a stacked configuration to produce a system-on-a-chip (SOC) device. These stacked-die IC devices may be used for implementing optical type of devices, such as image sensors, as well as non-optical type of devices, such as micro electro and mechanical system (MEMS) and surface acoustic wave (SAW) devices.
[0036] Advantageously, with terminals located on an undersurface of a die, the IC device has a small footprint no larger than the size of the die. Additional dies may also be provided in a stacked configuration to, for example, increase the functionality of the IC device without increasing the size of its footprint. The passivation layer of the IC device also covers substantially all active surfaces of a die and therefore provides a better seal of the die than in prior art devices. As terminals are found only on the undersurface of the IC device, expensive flip chip bonders are not required for mounting such an IC device to a substrate; standard die bonding machines can be used to pick and place such an IC device. Moreover, the terminals can be arranged according to chip-scale package (CSP) pitches so that under fill material is not required when mounting the IC device to a substrate. [0037] Also advantageously, the method for producing the IC device, especially one with a multiple dies in a stacked configuration, requires less process steps as compared to that required for prior art IC devices. The method allows for the use of a low-cost screen printing method for solder bumping. The method also allows for the use of the commonly-available lead-free solder paste for solder bumping. The method is flexible and thus modifiable for manufacturing aluminum and copper device. The method further allows for forming of integrated passives, such as resistors, capacitors and inductors, on the second side of a die prior to interconnection with another die or mounting onto a substrate. The method also allows fine pitch bumping for high input-output (IO) count, optically sensitive devices that may accept underfill materials at the board assembly levels.
[0038] Although the present invention is described as implemented in the above-described embodiments, it is not to be construed to be limited as such. For example, the method can also be used to manufacture inductor coils for high Q, radio frequency (RF) applications. In such a case, each die is formed to include one or more turns of a coil and several of such dies are interconnected as described to form the complete coil. [0039] As another example, the REMOVE WAFER MATERIAL step can be implemented entirely by etching, i.e., without backgrinding and/or polishing. In such a case, the method has the added advantage that it can be performed entirely in a clean room environment.

Claims

CLAIMSI claim:
1. A method of manufacturing an integrated circuit (IC) device comprising: providing a first wafer including a plurality of dies separated by separation zones, each of the plurality of dies including connection pads on a first active side of the wafer; forming a plurality of cavities along the separation zones, the plurality of cavities corresponding to the connection pads; forming routers that electrically connect the connection pads to route the connection pads to an interior of the corresponding cavities; removing wafer material from a second side, opposite the first side, to expose the routers in the cavities; forming contacts on the second side of the wafer, the contacts being electrically connected to the routers in the interior of the cavities to thereby electrically connect with the connection pads on the first side; and separating the dies along the separation zones to produce individualized dies, each of which serves as an IC device.
2. A method according to Claim 1 , further comprising forming a passivation layer prior to forming the routers so that the routers are separated from the dies by the passivation layer.
3. A method according to Claim 2, wherein removing wafer material includes: removing wafer material from a second side of the wafer, opposite the first side, to expose the passivation layer under the routers in the interior of the cavities; forming a second passivation layer on the second side of the wafer to contact the passivation layer in the interior of the cavities; and removing portions of the passivation layers from the second side of the wafer to expose the routers in the interior of the cavities.
4. A method according to Claim 3, further comprising forming terminals electrically connected to the contacts.
5. A method according to Claim 4, wherein forming terminals includes: forming one of a solder mask and a third passivation layer over the second passivation layer and contacts on the second side of the wafer; removing portions of the one of the solder mask and the third passivation layer over the contacts to expose the contacts; and forming solder bumps over the exposed contacts.
6. A method according to Claim 1 , further comprising attaching a packaging layer to the first side of the wafer after forming of the routers.
7. A method of claim 6, wherein separating the dies includes separating the packaging layer.
8. A method according to Claim 1, further comprising: providing a second wafer of dies processed in a manner similar to the first wafer to include routers that route connection pads on a first side of the second wafer to corresponding contacts on the second side of the second wafer; aligning and attaching the first side of the second wafer to the second side of the first wafer to thereby electrically connect connection pads on the dies of the second wafer to the contacts on the second side of corresponding dies of the first wafer to define stacks of dies; processing the second side of the second wafer in a similar manner to the first wafer to produce contacts thereon; and wherein separating the dies includes separating the stacks of dies to produce individualized integrated circuit devices, each of which includes a stack of dies.
9. A method according to Claim 8, further comprising providing at least one intermediate wafer interconnected between the first wafer and the second wafer.
10. An integrated circuit device comprising: a first die having: a plurality of connection pads on a first active side of the first die; a plurality of contacts on a second side of the first die, opposite the first side; and a plurality of routers, each of which electrically connects a connection pad to a corresponding contact, wherein the routers run along recesses formed on at least one sidewall of the first die.
11. An integrated circuit device according to Claim 10, further comprising a passivation layer on the first side of the first die between the die and the routers.
12. An integrated circuit device according to Claim 11, further comprising a second passivation layer on the second side of the first die between the die and the routers.
13. An integrated circuit device according to Claim 12, further comprising terminals electrically connected to the contacts.
14. An integrated circuit device according to Claim 13, further comprising one of a solder mask and a third passivation layer on the second side of the first die covering areas on the second side exposed by the terminals.
15. An integrated circuit device according to Claim 10, further comprising a packaging layer attached to the first side of the die.
16. An integrated circuit device according to Claim 10, further comprising a second die having routers that route connection pads on a first side of the second die to contacts on a second side, opposite the first side, of the second die; wherein the first side of the second die is attached to the second side of the first die to thereby electrically connect connection pads on the second die to the contacts on the second side of the first die to define a stack of dies.
17. An integrated circuit device according to Claim 16, further comprising at least one intermediate die interconnected between the first die and the second die.
18. An integrated circuit device according to Claim 10, wherein the recesses are formed on an upper portion of the sidewall adjacent to the first side of the die, and wherein a lower portion of the sidewall adjacent to the second side of the die is substantially planar.
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