WO2003058630A1 - Multi-mode synchronous memory device and method of operating and testing same - Google Patents
Multi-mode synchronous memory device and method of operating and testing same Download PDFInfo
- Publication number
- WO2003058630A1 WO2003058630A1 PCT/US2002/040447 US0240447W WO03058630A1 WO 2003058630 A1 WO2003058630 A1 WO 2003058630A1 US 0240447 W US0240447 W US 0240447W WO 03058630 A1 WO03058630 A1 WO 03058630A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- accordance
- asynchronous
- mode
- normal mode
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/109—Control signal input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003558855A JP2005514721A (en) | 2001-12-26 | 2002-12-18 | Multi-mode synchronous memory device and its operation method and test method |
KR1020047010154A KR100592648B1 (en) | 2001-12-26 | 2002-12-18 | Multi-mode synchronous memory device and method of operating and testing same |
DE60224727T DE60224727T2 (en) | 2001-12-26 | 2002-12-18 | MULTIMODE SYNCHRONOUS MEMORY DEVICE AND METHOD FOR OPERATING AND TESTING THE SAME |
AU2002361761A AU2002361761A1 (en) | 2001-12-26 | 2002-12-18 | Multi-mode synchronous memory device and method of operating and testing same |
EP02797398A EP1459323B1 (en) | 2001-12-26 | 2002-12-18 | Multi-mode synchronous memory device and method of operating and testing same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/036,141 US6678205B2 (en) | 2001-12-26 | 2001-12-26 | Multi-mode synchronous memory device and method of operating and testing same |
US10/036,141 | 2001-12-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2003058630A1 true WO2003058630A1 (en) | 2003-07-17 |
Family
ID=21886877
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2002/040447 WO2003058630A1 (en) | 2001-12-26 | 2002-12-18 | Multi-mode synchronous memory device and method of operating and testing same |
Country Status (10)
Country | Link |
---|---|
US (3) | US6678205B2 (en) |
EP (1) | EP1459323B1 (en) |
JP (1) | JP2005514721A (en) |
KR (1) | KR100592648B1 (en) |
CN (1) | CN100424781C (en) |
AT (1) | ATE384328T1 (en) |
AU (1) | AU2002361761A1 (en) |
DE (1) | DE60224727T2 (en) |
TW (1) | TWI222068B (en) |
WO (1) | WO2003058630A1 (en) |
Families Citing this family (35)
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US7058799B2 (en) * | 2001-06-19 | 2006-06-06 | Micron Technology, Inc. | Apparatus and method for clock domain crossing with integrated decode |
JP2003045200A (en) * | 2001-08-02 | 2003-02-14 | Mitsubishi Electric Corp | Semiconductor module and semiconductor memory used for the same |
ITRM20010556A1 (en) * | 2001-09-12 | 2003-03-12 | Micron Technology Inc | DECODER TO DECODE SWITCHING COMMANDS IN INTEGRATED CIRCUIT TEST MODE. |
US6678205B2 (en) * | 2001-12-26 | 2004-01-13 | Micron Technology, Inc. | Multi-mode synchronous memory device and method of operating and testing same |
US7142461B2 (en) * | 2002-11-20 | 2006-11-28 | Micron Technology, Inc. | Active termination control though on module register |
DE10305837B4 (en) * | 2003-02-12 | 2009-03-19 | Qimonda Ag | Memory module with a plurality of integrated memory devices |
JP4327482B2 (en) * | 2003-03-18 | 2009-09-09 | 富士通マイクロエレクトロニクス株式会社 | Synchronous semiconductor memory device |
KR100522433B1 (en) | 2003-04-29 | 2005-10-20 | 주식회사 하이닉스반도체 | Domain crossing circuit |
US6961269B2 (en) * | 2003-06-24 | 2005-11-01 | Micron Technology, Inc. | Memory device having data paths with multiple speeds |
KR100543925B1 (en) * | 2003-06-27 | 2006-01-23 | 주식회사 하이닉스반도체 | Delay Locked Loop and its method for delaying locked a clock |
JP2005049970A (en) * | 2003-07-30 | 2005-02-24 | Renesas Technology Corp | Semiconductor integrated circuit |
JP2007527091A (en) * | 2004-03-05 | 2007-09-20 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | DFT technology to enhance self-timing memory for detecting delay faults |
KR100612952B1 (en) * | 2004-04-30 | 2006-08-14 | 주식회사 하이닉스반도체 | Synchronous semiconductor memory deivce decreased power consumption |
US7519877B2 (en) * | 2004-08-10 | 2009-04-14 | Micron Technology, Inc. | Memory with test mode output |
US7536570B2 (en) * | 2006-10-02 | 2009-05-19 | Silicon Laboratories Inc. | Microcontroller unit (MCU) with suspend mode |
WO2008041974A2 (en) * | 2006-10-02 | 2008-04-10 | Kafai Leung | Microcontroller unit (mcu) with suspend mode |
US8185771B2 (en) * | 2006-12-20 | 2012-05-22 | Nxp B.V. | Clock generation for memory access without a local oscillator |
US7685542B2 (en) * | 2007-02-09 | 2010-03-23 | International Business Machines Corporation | Method and apparatus for shutting off data capture across asynchronous clock domains during at-speed testing |
JP2008217947A (en) * | 2007-03-07 | 2008-09-18 | Elpida Memory Inc | Semiconductor memory |
US7779375B2 (en) * | 2007-10-17 | 2010-08-17 | International Business Machines Corporation | Design structure for shutting off data capture across asynchronous clock domains during at-speed testing |
US7936637B2 (en) * | 2008-06-30 | 2011-05-03 | Micron Technology, Inc. | System and method for synchronizing asynchronous signals without external clock |
KR101166800B1 (en) * | 2010-05-28 | 2012-07-26 | 에스케이하이닉스 주식회사 | Delay circuit |
TWI460728B (en) * | 2010-12-29 | 2014-11-11 | Silicon Motion Inc | Memory controller, memory device and method for determining type of memory device |
US8522089B2 (en) * | 2011-01-21 | 2013-08-27 | Freescale Semiconductor, Inc. | Method of testing asynchronous modules in semiconductor device |
CN102081965B (en) * | 2011-02-21 | 2013-04-10 | 西安华芯半导体有限公司 | Circuit for generating inner write clock of dynamic random access memory (DRAM) |
CN102394633B (en) * | 2011-08-31 | 2013-08-21 | 华南理工大学 | Low power consumption asynchronous comparison gate for low density parity code (LDPC) decoder |
KR102291505B1 (en) * | 2014-11-24 | 2021-08-23 | 삼성전자주식회사 | Storage device and operating method of storage device |
CN105913868B (en) * | 2016-03-31 | 2018-09-21 | 华为技术有限公司 | A kind of method, system on chip and the terminal of adjustment frequency |
CN111381148B (en) * | 2018-12-29 | 2023-02-21 | 华润微集成电路(无锡)有限公司 | System and method for realizing chip test |
WO2020154989A1 (en) * | 2019-01-30 | 2020-08-06 | 华为技术有限公司 | Method for adjusting duty cycle, controller chip, and flash memory |
CN109872744A (en) * | 2019-03-19 | 2019-06-11 | 济南德欧雅安全技术有限公司 | A kind of cell memory facilitating test |
CN112088523B (en) * | 2019-03-27 | 2023-04-28 | 京东方科技集团股份有限公司 | Internet of things system, central control equipment, application equipment and communication method |
CN110843529B (en) * | 2019-10-10 | 2020-12-18 | 珠海格力电器股份有限公司 | High-voltage interlocking fault self-diagnosis circuit, control method and new energy automobile |
CN116203400B (en) * | 2023-04-27 | 2023-07-28 | 湖南大学 | Test method and system based on chip initialization |
CN116879725B (en) * | 2023-09-06 | 2023-12-08 | 西安紫光国芯半导体股份有限公司 | Sampling circuit, self-test circuit and chip |
Citations (4)
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US5796673A (en) * | 1994-10-06 | 1998-08-18 | Mosaid Technologies Incorporated | Delay locked loop implementation in a synchronous dynamic random access memory |
US5875153A (en) * | 1997-04-30 | 1999-02-23 | Texas Instruments Incorporated | Internal/external clock option for built-in self test |
US6266294B1 (en) * | 1998-06-30 | 2001-07-24 | Fujitsu Limited | Integrated circuit device |
US6301190B1 (en) * | 2000-01-06 | 2001-10-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device with a rapid packet data input, capable of operation check with low speed tester |
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US5384737A (en) | 1994-03-08 | 1995-01-24 | Motorola Inc. | Pipelined memory having synchronous and asynchronous operating modes |
US5696917A (en) | 1994-06-03 | 1997-12-09 | Intel Corporation | Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory |
US6205514B1 (en) * | 1995-02-21 | 2001-03-20 | Micron Technology, Inc. | Synchronous SRAM having global write enable |
US5548560A (en) | 1995-04-19 | 1996-08-20 | Alliance Semiconductor Corporation | Synchronous static random access memory having asynchronous test mode |
US5655105A (en) * | 1995-06-30 | 1997-08-05 | Micron Technology, Inc. | Method and apparatus for multiple latency synchronous pipelined dynamic random access memory |
US5666321A (en) | 1995-09-01 | 1997-09-09 | Micron Technology, Inc. | Synchronous DRAM memory with asynchronous column decode |
US5920518A (en) * | 1997-02-11 | 1999-07-06 | Micron Technology, Inc. | Synchronous clock generator including delay-locked loop |
US6172935B1 (en) * | 1997-04-25 | 2001-01-09 | Micron Technology, Inc. | Synchronous dynamic random access memory device |
US5995424A (en) * | 1997-07-16 | 1999-11-30 | Tanisys Technology, Inc. | Synchronous memory test system |
US5926047A (en) * | 1997-08-29 | 1999-07-20 | Micron Technology, Inc. | Synchronous clock generator including a delay-locked loop signal loss detector |
DE19830571C2 (en) * | 1998-07-08 | 2003-03-27 | Infineon Technologies Ag | Integrated circuit |
US6081477A (en) * | 1998-12-03 | 2000-06-27 | Micron Technology, Inc. | Write scheme for a double data rate SDRAM |
DE10005161A1 (en) * | 1999-04-30 | 2000-11-02 | Fujitsu Ltd | Semiconductor circuit with test function activated according to state of specific connection when supply switched on |
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KR100316023B1 (en) * | 1999-11-01 | 2001-12-12 | 박종섭 | Analog-digital mixed type delay locked loop combining voltage controlled oscillator and shift register type delay locked loop |
JP2001202773A (en) * | 2000-01-20 | 2001-07-27 | Mitsubishi Electric Corp | Semiconductor memory |
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JP3627647B2 (en) * | 2000-10-27 | 2005-03-09 | セイコーエプソン株式会社 | Activation of word lines in semiconductor memory devices |
US6678205B2 (en) * | 2001-12-26 | 2004-01-13 | Micron Technology, Inc. | Multi-mode synchronous memory device and method of operating and testing same |
-
2001
- 2001-12-26 US US10/036,141 patent/US6678205B2/en not_active Expired - Lifetime
-
2002
- 2002-12-10 TW TW091135716A patent/TWI222068B/en not_active IP Right Cessation
- 2002-12-18 AU AU2002361761A patent/AU2002361761A1/en not_active Abandoned
- 2002-12-18 CN CNB02828299XA patent/CN100424781C/en not_active Expired - Fee Related
- 2002-12-18 DE DE60224727T patent/DE60224727T2/en not_active Expired - Lifetime
- 2002-12-18 AT AT02797398T patent/ATE384328T1/en not_active IP Right Cessation
- 2002-12-18 KR KR1020047010154A patent/KR100592648B1/en not_active IP Right Cessation
- 2002-12-18 JP JP2003558855A patent/JP2005514721A/en active Pending
- 2002-12-18 EP EP02797398A patent/EP1459323B1/en not_active Expired - Lifetime
- 2002-12-18 WO PCT/US2002/040447 patent/WO2003058630A1/en active IP Right Grant
-
2003
- 2003-11-07 US US10/703,275 patent/US6842398B2/en not_active Expired - Fee Related
-
2004
- 2004-12-01 US US11/001,231 patent/US7057967B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5796673A (en) * | 1994-10-06 | 1998-08-18 | Mosaid Technologies Incorporated | Delay locked loop implementation in a synchronous dynamic random access memory |
US5875153A (en) * | 1997-04-30 | 1999-02-23 | Texas Instruments Incorporated | Internal/external clock option for built-in self test |
US6266294B1 (en) * | 1998-06-30 | 2001-07-24 | Fujitsu Limited | Integrated circuit device |
US6301190B1 (en) * | 2000-01-06 | 2001-10-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device with a rapid packet data input, capable of operation check with low speed tester |
Also Published As
Publication number | Publication date |
---|---|
CN100424781C (en) | 2008-10-08 |
KR20040074105A (en) | 2004-08-21 |
ATE384328T1 (en) | 2008-02-15 |
US20050094432A1 (en) | 2005-05-05 |
AU2002361761A1 (en) | 2003-07-24 |
US6842398B2 (en) | 2005-01-11 |
DE60224727D1 (en) | 2008-03-06 |
US20040090821A1 (en) | 2004-05-13 |
TW200301482A (en) | 2003-07-01 |
EP1459323A1 (en) | 2004-09-22 |
US6678205B2 (en) | 2004-01-13 |
DE60224727T2 (en) | 2009-01-15 |
US20030117881A1 (en) | 2003-06-26 |
KR100592648B1 (en) | 2006-06-26 |
EP1459323B1 (en) | 2008-01-16 |
CN1620696A (en) | 2005-05-25 |
JP2005514721A (en) | 2005-05-19 |
US7057967B2 (en) | 2006-06-06 |
TWI222068B (en) | 2004-10-11 |
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