WO2003054722A3 - Method and system for managing hardware resources to implement system functions using an adaptive computing architecture - Google Patents

Method and system for managing hardware resources to implement system functions using an adaptive computing architecture Download PDF

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Publication number
WO2003054722A3
WO2003054722A3 PCT/US2002/039566 US0239566W WO03054722A3 WO 2003054722 A3 WO2003054722 A3 WO 2003054722A3 US 0239566 W US0239566 W US 0239566W WO 03054722 A3 WO03054722 A3 WO 03054722A3
Authority
WO
WIPO (PCT)
Prior art keywords
computational elements
operations
architectures
adaptive
functions
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Application number
PCT/US2002/039566
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French (fr)
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WO2003054722A2 (en
Inventor
Robert Plunkett
Ghobad Heindari
Paul L Master
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Quicksilver Tech Inc
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Publication date
Application filed by Quicksilver Tech Inc filed Critical Quicksilver Tech Inc
Priority to AU2002351355A priority Critical patent/AU2002351355A1/en
Publication of WO2003054722A2 publication Critical patent/WO2003054722A2/en
Publication of WO2003054722A3 publication Critical patent/WO2003054722A3/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The exemplary IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. In an exemplary embodiment, some or all of the computational elements are alternately configured to implement two or more functions.
PCT/US2002/039566 2001-12-12 2002-12-10 Method and system for managing hardware resources to implement system functions using an adaptive computing architecture WO2003054722A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002351355A AU2002351355A1 (en) 2001-12-12 2002-12-10 Method and system for managing hardware resources to implement system functions using an adaptive computing architecture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/015,530 2001-12-12
US10/015,530 US7752419B1 (en) 2001-03-22 2001-12-12 Method and system for managing hardware resources to implement system functions using an adaptive computing architecture

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US10/021,589 Continuation US6566341B1 (en) 2001-12-13 2001-12-13 Derivative of isoindigo, indigo and indirubin for the treatment of cancer
US13/791,314 Continuation US9023885B2 (en) 2001-12-13 2013-03-08 Methods of treating an inflammatory-related disease

Related Child Applications (1)

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US10/864,458 Continuation-In-Part US6933315B2 (en) 2001-12-13 2004-06-10 Derivatives of isoindigo, indigo and indirubin and methods of treating cancer

Publications (2)

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WO2003054722A2 WO2003054722A2 (en) 2003-07-03
WO2003054722A3 true WO2003054722A3 (en) 2004-05-06

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PCT/US2002/039566 WO2003054722A2 (en) 2001-12-12 2002-12-10 Method and system for managing hardware resources to implement system functions using an adaptive computing architecture

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US (4) US7752419B1 (en)
AU (1) AU2002351355A1 (en)
WO (1) WO2003054722A2 (en)

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