WO2003032150A1

WO2003032150A1 - Improved random variable generator

Info

Publication number: WO2003032150A1
Application number: PCT/FR2002/003356
Authority: WO
Inventors: Nicolas Sendrier; André SEZNEC
Original assignee: Inria Institut National De Recherche En Informatique Et En Automatique
Priority date: 2001-10-11
Filing date: 2002-10-02
Publication date: 2003-04-17
Also published as: FR2830952A1; FR2830952B1

Abstract

The invention concerns generating random variables by computer means, in particular for cryptography. It concerns in particular a computer comprising a processor ( mu P), capable of interacting with peripherals by interruptions and a random number generator, operating by time measurement on events, related to interruptions. The invention is characterized in that the random variable generator measures time on sequences of instructions whereof the duration of execution depends at least partly on internal states (CD, CN2, CI, TLB) of the processor, not directly accessible to the user and which are modified by interruptions.

Description

Improved hazard generator

The invention relates to the generation of hazards by computer means, in particular for cryptography.

Devices for generating hazards are in the form of computers equipped with a processor, memories and peripherals such as a screen, input devices (keyboard, mouse), a sound card, a graphics card, or else a remote network access card. The exchanges of the processor with these peripherals, generally via a motherboard and a random access memory, are carried out by means of interrupts.

In known devices, hazard generators include a module comprising instructions for detecting interruptions and for measuring the time between these interruptions. The hazard generator derives a random expression from this time measurement since, in conventional computers, it is rare for a processor to cooperate with the same peripherals, regularly following the same sequence.

Even if such random generators are sufficiently reliable for certain cryptographic applications, they have the disadvantage of being slow since the rate of generation of the hazard depends on the operations carried out by a user. In addition, they are not completely inviolable since the hazard comes from external physical phenomena. The hazard remains determinable, even if it requires very heavy means to determine it.

The present invention improves the situation.

To this end, it offers a computer comprising: a processor capable of interacting with peripherals by means of interrupts, comprising at least an internal cache memory and a given hardware counter, and

- a hazard generator, operating by time measurement on sequences of instructions, linked to interruptions.

According to a characteristic of the invention, the hazard generator performs the time measurement, from at least the given hardware counter, on sequences of instructions whose execution time depends at least in part on states internal of the processor, not directly accessible to the user and which are modified by interrupts, the internal states being related inter alia to the presence or absence of data in at least the internal cache memory, this data being sought in at least the internal cache memory when executing at least one sequence of instructions.

The internal states of the processor preferentially relate to volatile non-architectural states, such as states:

- the first level data cache,

- the second level cache,

- the instruction cache, - the write buffer,

- the branch prediction table,

- the cycle counter.

Typically, the cycle counter increments its current value at each cycle. The other elements above include memories whose contents can only be read indirectly.

The term "non-architectural state" is opposed to the term "architectural state" which relates to the content of computer memories (random access memory, read only memory), the content of registers and the program counter (or ordinal counter), which remain accessible and can be manipulated by a set of instructions from an appropriate program.

In a preferred embodiment, the hazard generator performs the time measurement from the cycle counter that includes the processor.

As a variant, other counters can be used, in particular event counters such as fault counters on the covers or fault prediction counters for connection.

Advantageously, the hazard generator, in the computer of the invention, comprises a module executing instructions to modify at least part of the internal states of the processor by accessing it.

As such, this module is an important means for implementing the present invention. The module can be in the form of a computer program product capable of controlling the processor to perform a time measurement whose execution time depends at least in part on internal states of the processor, not directly accessible to the user. and which are modified by interruptions.

Preferably, the module includes an instruction to declare a table of selected memory size at least equal to the capacity of an internal cache memory of the processor, as well as a pointer in the table.

In one embodiment, the processor comprises a first level cache memory and a second level volatile cache memory, and the memory size of the table is chosen to be greater than the memory capacity of the first cache. level, so as to address the first level cache or the second level cache.

In addition or as a variant, the processor comprises a branch prediction table, of volatile content, the abovementioned internal states of the processor further concerning addresses of the prediction table. Advantageously, the module comprises an instruction for testing the value of the pointer, so as to modify the content of the branch prediction table.

Preferably, the test relates to a most significant bit to exercise the branch prediction table.

Advantageously, the module comprises at least one instruction for reading a value of the cycle counter, and the random generator is arranged to provide a random expression from a combination of the value read from the pointer and the value of the cycle counter, which makes it possible to add up the generated hazard.

In an advantageous embodiment, the hazard generator is arranged to be put into service permanently, with a low level priority.

Advantageously, the module includes an instruction loop comprising an update of the table with the assignment of a value as a function of the random expression, with a view to propagating a hazard in the table. Preferably, the module is arranged to reiterate the instruction loop a number of times chosen to saturate the instruction cache of the processor.

To address the volatile address indication buffer that the processor includes in one embodiment, the module advantageously includes an instruction to declare a second table of memory size chosen at least equal to the capacity of the buffer memory, as well as a pointer in the second table.

As a variant, the module comprises an instruction for playing the address translation buffer memory by implementing a sufficient number of pages in the first declared table.

Other characteristics and advantages of the invention will appear on examining the detailed description below, and the appended drawings in which:

FIG. 1 schematically represents a conventional computer, equipped with peripherals,

FIG. 2 schematically represents the interactions between the processor and the equipment of a central unit UC of the computer of FIG. 1,

FIG. 3 represents the operations executed during an interrupt routine which requests the processor μP,

FIG. 4 represents the interactions between different registers and memories of the processor, as well as the cycle counter, and

- Figure 5 shows a flow diagram of a process for generating a random expression, in a device of one invention.

In the appendix are transcribed program instructions (in C language) that the computer of the invention implements, in a preferred embodiment. This document may contain elements that may be protected by copyright. The rights holder has no objection to the identical reproduction by anyone of this patent document, as it appears in the files and / or publications of patent offices. On the other hand, it reserves for the rest all of its author's rights and / or copyright.

The description below, the drawings and the annex essentially contain elements of a certain nature. They can therefore not only serve to better understand

—Description, but - also — contribute to the definition of the invention, if necessary.

We first refer to Figure 1 to describe a computer equipped with peripherals. The computer comprises a central processing unit UC, equipped with an LEC reader for, where appropriate, 1-ire — data — on a medium of the CD-ROM, floppy or other type, in particular instruction instruction data. programs. The computer further includes an ECR display screen, as well as several input devices such as a SOU mouse and a CLA keyboard. In the example shown, the computer is equipped with a link to a remote network (COM arrow). The LEC reader, the SOU and CLA input devices, the COM link are peripherals capable of communicating with the processor of the central unit by means of interruptions. They send interrupt requests to the μP processor and the μP processor performs tasks in response to these requests.

Referring to FIG. 2, the central processing unit UC comprises, in the example described, a processor μP capable of cooperating with a working memory MT (a RAM memory, for example), with a motherboard CM and a disk hard DD. The CM motherboard communicates with most peripherals, such as the COM link (L3 output) via a CMO modem card, a card its CS (output L2) and, if necessary, the ECR screen via a graphics card CG (output L1). The gripping devices CLA and SOU are connected by the links L4 and L5. The μP processor can communicate with peripherals such as input devices, the COM link, the DD hard disk and the CS sound card, by interruptions.

Referring to Figure 3, a PGM program is executed (arrow EXE). During this execution, a PERI device (or even a system clock) requires a temporary interruption INT of the execution of the current PGM program.

The RINT interrupt routine then proceeds as follows:

- the routine begins first with a SAV1 backup of the registers in progress, in a cache memory CH of the processor and, if necessary in a random access memory RAM of the computer, in the event of exceeding the capacities of the cache memory CH;

- the routine, continues with the effective development TRA of the task required by the peripheral, during which only the architectural states (for example the ordinal program counter) are saved;

- and, when the task is carried out, the interruption routine continues with a restoration of the registers RES with respect to the initial state SAV1, then - with a backup SAV2 of the registers and architectural states which have been used during the interruption.

At the end of the RINT interrupt routine, we return (arrow RT) to the execution of the PGM program.

In known random generation techniques and verifying the RFC 1750 standard (IETF, RFC 1750: Randomness recommendations for security, 1994), the computer includes an interrupt controller which is accessed to measure a time difference between two interrupts. From the time difference between different interruptions, we construct a random expression. However, in service, these interruptions are required by peripherals generally according to the request of a user. This technique has the disadvantage of being slow since the generation of the random expression depends mainly on the activity of the user. In addition, as the hazard generated thus depends on external physical conditions, it is rather a "pseudo-hazard", within the meaning of the reference:

Oded Goldreich, Modem Cryptography Probabilistic Proofs and P-se dorandomness. Number- 17 in Algorithm and Combinatorics. Spri-nger, 1999. - - - - _

The present invention proposes to do otherwise.

Referring to FIG. 4, the processor μP, capable of cooperating with a working memory MT, comprises in -1- example described-: -— -

a CD data cache memory, a second level CN2 cache memory,

- a CI instruction cache memory,

- a PB branch predictor,

- a TLB address translation cache memory ("Translation Lookaside Buffer"), and - a CC cycle counter.

In the example, the computer is a workstation marketed by the company SUN (Registered trademark) and the processor is of the ULTRASPARC II (Registered trademark) type at 300 MHz clock frequency. The processor is implemented by the SOLARIS operating system (registered trademark).

In the diagram shown in FIG. 4, the volatile memories and / or the volatile internal states of the processor are represented by solid lines. So the memories

CI, CD, CN2, as well as the PB and TLB tables correspond to memories which include volatile data relating to internal states of the processor. The cycle counter, which increments its value on each cycle, corresponds to a volatile internal state of the processor.

UF functional units cooperate, on the one hand, with the data cache memory CD, to recover and transmit the data and, on the other hand with a REG register file, regularly updated.

The branch predictor PB controls the instruction cache memory CI. To use this instruction data, a hardware mechanism called a DR decoder translates and renames this instruction data. This translated data is then processed by hardware queues Q, which apply them to the functional units UF of the processor.

The second level cache memory CN2 can store simple data, in which case it cooperates with the data cache memory CD, or also instruction data, in which case it cooperates with the instruction cache memory CI.

The TLB address translation cache can store the physical addresses of the pages of a process.

In the example described where the processor is of the ULTRASPARC II type: - the first level data cache memory CD comprises 16 kb with direct access (512 cache sectors at 32 bytes);

- the instruction cache memory is 16 KB, with 32-byte cache blocks;

- the second level CN2 caches are 1 MB with blocks of 64 bytes; - the TLB table includes 64 entries and the requester has found that for one hundred consecutive invocations by the operating system, the minimum cumulative number of block displacements systematically exceeds 4500 for the data and 600 for the instructions;

- the PB branching predictor has a memory size of 2K 2-bit inputs.

Reference is now made to FIG. 5 to describe, in a preferred embodiment, a processing allowing _generation of random expressions using a computer _ equipped with a processor of the type represented in FIG. 4.

Processing begins with the initialization and declaration of a WALK table, in step 10. Preferably, the table

WALK is of dimensions corresponding to a memory size twice as large as the first level cache memory.

If necessary, in step 12, an ARRAY table is initialized and declared. It is chosen to have dimensions using a memory size twice as large as the memory that can be translated by the TLB translation cache, in order to exercise all of the TLB entries.

The processing continues at 14 by reading a datum from the WALK table, through a pointer value PT. Preferably, in step 14, the old pointer read previously was also kept in the loop for updating in step 24, as will be seen below.

Thus, by reading the value of a pointer in the WALK table, we implement:

- either the first level CD data cache memory;

- either the second level cache memory CN2 when the data is absent at the first level; - or the main memory when the data is absent on the first and second level.

As the dimensions of the WALK table are twice as large, in memory size, as the first level cache memory CD, the probability of the presence of the data in the first level cache is 1/2: the time of the reading will be different depending on the presence or not of the data in the cache.

In step 16, a most significant bit of the value of the pointer PT is tested, with the aim of exceeding the size of the WALK table and rather exercising the branch prediction table PB. Here, the result of test 16 has no influence on the continuation of the treatment and, moreover, is not taken into account for the rest. However, the test execution time differs depending on whether the test was well predicted or poorly predicted.

A l ^L step 20, it reads the value T of the .mu.P CPU cycle counter.

In step 22, a new value of the pointer PT is assigned, as a function of its old value and of the current value T of the cycle counter, read in step 20. This function of the old value of the pointer PT and of the value T is a combination which, in a preferred embodiment, corresponds to the "or exclusive" function (XOR). This modification of the value of the pointer by an "or exclusive" with the cycle counter makes it possible to amplify the hazard. Thus, a user who would try to access the value of PT to resume processing and obtain the random expression generated would not find the same values since they depend on the cycle counter, which advantageously reinforces the security of the hazard. generated. In step 24, the WALK table is updated by assigning to it the value of the pointer PT newly defined in step 22. Advantageously, the hazard is thus propagated in the WALK table, when the processing has carried out several loops, as we will see later.

At step 26, a random datum RES [i] is output, as a function of the value of the pointer PT established in step 22.

The processing continues with an incrementation (step 30) of the loop index i, which is incremented in step 30, as long as this value does not exceed the number N (step 28). Advantageously, the number N is chosen as a function of the memory size of the instruction cache CI, so as to saturate it when the loop index i reaches the value N.

Thus, at each loop of index i, we read at 14 the previous value of the pointer PT, established in step 22 for the previous loop index and, on the one hand, the hazard is propagated gradually at each step 24, for all the loop indices, and, on the other hand, the successive random expressions RES [i] are recovered in step 26.

Finally, when the value of the loop index i reaches the value N, a random expression Ω is recovered, in step 32, as a function of the different hazards RES [1], RES [2], .., RES [ NOT] .

A loop for deducing the random expression, also as a function of a pointer value in the ARRAY spreadsheet defined in step 12, is not represented in FIG. 5. Of course, the random expression RES [i] can be drawn, both from a reading of a pointer on the WALK table and from a reading of another pointer on the ARRAY table. We now refer to the processing transcribed in the appendix, corresponding to instructions for a computer program, in C language.

The code is compiled using the SOLARIS operating system compiler from the company SUN (Trademarks), with the options cc-x05-FAST-XARCH = v =PLUS.

The "HardTick ()" function provides the number of cycles that have elapsed since the last call (this is therefore a difference between the number of current cycles and the number of cycles read during the previous consultation).

The sign corresponds to the "or exclusive" (XOR) function.

The program begins with the declarations:

- from the Walk table,

- pointers PT, PT and PT2,

- of the loop index i which is an integer, and - of a loop ("loop" instruction of line 1).

The Walk table is initialized by the short Walk instruction [512 * 1024], so as to give it a memory size of 1 MB, which corresponds to the capacity of the second level cache CN2 and which, in any event, exceeds the capacity of the first level cache.

On line 2, test bit 14 of the pointer pt (4000 in hexadecimal corresponding to 2 ¹⁴ ). The test on the most significant bit 14 makes it possible to exceed the memory size allocated to the Walk table and thus to exercise the branch predictor PB. If necessary, a current value X is incremented, as a function of the test. Similarly, line 5 tests the most significant bit 15 of the pointer pt (8000 in hexadecimal corresponding to 2 ¹⁵ ) to further exercise the branch predictor. The results of these tests, as well as the variable current X, have no importance here. In fact, these test instructions are followed by a combination operation "or exclusive" (sign " ^Λ " on lines 4 and 7), involving the pointer pt, in order to add the hazard and prevent an observer from d 'access the random expression RESULT [i] (corresponding to the random expression RES [i] in Figure 5) and the value of the pointer pt, as we will see below.

On line 3, the least significant bits (less than 14) of the pointer pt (3fff in hexadecimal corresponding to 2 ¹⁴ -1) are saved in the pointer PT. At the second instruction in line 3, the pointer pt reads its new values from the table. The third instruction concerns the pointer PT2 which randomly takes its values at the addresses corresponding to the bits of weight less than 14.

Here, the operation on the pointer PT2 of ^" line 3 mainly aims at combining" or exclusive "with the pointer pt of line 4 which follows, from which the random expression RESULT [i] is taken.

In line 6, we extract from the processor cycle counter ("HardTick ()" function) the current value of the cycle counter, then we combine this value with "or exclusive" and circular offset with a variable T.

In line 7, the pointer pt takes the value of the "or exclusive" combination of itself with the variable T, with the aim of adding the hazard, as described above. The result of this combination is applied to the Walk table (line 8). By thus modifying the Walk table on the fly, the hazard is propagated in the table.

Then increment the loop counter i (line 9). In the example described, 132 other copies of lines 2 to 9 of the body are present, so that the instruction volume of the (compiled) loop is substantially equal (preferably, by lower value) to the size of the CI instruction cache.

In the example in the appendix, it will be noted that the ARRAY table in Figure 5 has not been declared. We proceed differently here to exercise the TLB buffer. On line 11, we play all the TLB buffer by implementing the 128 pages in the Walk table.

Advantageously, this program is intended to be put into service permanently in the computer of the invention, with a relatively low execution priority compared to the other tasks of the processor μP. Thus, each time the μP processor is available, the program in the appendix takes over to prepare random expressions Ω. It is interrupted when the processor is requested by another application, in particular by interrupts, in which case the content of the addresses of the first level, second level caches, instructions, the TLB buffer, etc., is modified after the interruption, which further increases the hazard generated when the hazard generator program resumes execution thereafter.

Of course, the present invention is not limited to the embodiment described above by way of example; it extends to other variants.

Thus, it will be understood that the use of the cycle counter, above, is described only by way of example. Alternatively, one can use an event counter, such as the clock counter or the like.

In the program transcribed in the appendix, an ARRAY table is not declared to exercise the TLB buffer. Of course, this variant can be provided, as in the processing shown in FIG. 5.

The declarations and initializations of the tables at the start of processing depend on the capacities of memories such as the first level, second level data cache, the TLB buffer. The declaration of these tables is liable to change as a function of the memories used in the processor of the computer according to the invention.

Finally, in the foregoing, the processing involves all — the internal states—— for the cache memories and the predictors of connections of the current processors. In simplified variants, provision may be made to use only part of these internal states to generate random expressions, at least one type of internal state. Other internal states not accessible to the user can also be used (states of different buffers, etc.).

The present invention also relates to the software code which it involves, particularly when it is made available on any medium readable on a computer. The term "computer-readable medium" covers a storage medium, for example magnetic or optical, as well as a means of transmission, such as a digital or analog signal.

ANNEX

short Walk [512 * 1024]; register short pt, PT, pT2; register integer i;

1 loop {

2 if (pt & 0x4000) X ++;

3 PT = pt &0x3fff; pt = Walk [PT]; PT2 = Walk [PT2 &0x3fff];

4 RESULT [i] = PT2 ^Λ pt; 5 if (pt & 0x8000) X ++;

6 T = ((T "l) ^Λ HardTick ()) ^Λ (T"15);

7 pt = pt ^Λ T;

8 Walk [PT] = pt;

9 i ++; 10 ** same sequence repeated 132 times **

11 X + = Walk [(PT & 127) “12];

12}

Claims

claims

1. Computer including:

- a processor (μP), capable of interacting with peripherals by means of interrupts, comprising at least one internal cache memory and a given hardware counter, and

- a hazard generator, operating by time measurement (T) on sequences of instructions, linked to interruptions, characterized in that the hazard generator performs the time measurement, from at least the counter given hardware, on sequences of instructions whose execution time depends at least on .. part of internal states (CD, CN2, CI, TLB, PB, T) of the processor, not directly accessible to the user and which are modified by interruptions, the internal states are related inter alia to the presence or absence of data in at least the internal cache memory, this data being retrieved from the at least _^ internal cache _memory. when executing at least one sequence of instructions.

2. Computer according to claim 1, characterized in that the hazard generator performs the time measurement (T) from at least one cycle counter that includes the processor.

3. Computer according to one of claims 1 and 2, in which the internal states of the processor include memory addresses for at least the internal, volatile cache memory of the processor (CD, CN2, CI, TLB), characterized in that the hazard generator comprises a module comprising —instructions capable of modifying the content of the internal cache memory by accessing it.

4. Computer according to claim 3, characterized in that the module comprises an instruction to declare a table

(Walk) of selected memory size at least equal to the capacity of the internal cache memory of the processor, as well as at least one pointer (pt; PT) to address the table.

5. Computer according to claim 4, in which the processor comprises a first level cache (CD) and a second level cache (CN2), characterized in that the memory size of the table (Walk) is chosen to be greater than the capacity first level cache memory (CD), so that the table cannot be contained in the first level cache.

6. Computer according to one of claims 4 and 5, characterized in that the module comprises at least one instruction for reading the value of the pointer (pt), and in that the random generator is arranged to provide an expression random (RES [i]) from the value read (pt).

7. Computer according to claim 6, taken in combination with claim 2, characterized in that the module comprises at least one instruction for reading a value of the cycle counter (T), and in that the random generator is arranged to provide a random expression (RES [i]) from a combination (XOR) of the value read from the pointer (pt) and the value of the cycle counter (T).

8. Computer according to one of the preceding claims, in which the processor comprises a branch prediction table (PB), of volatile content, characterized in that the hazard generator comprises a module comprising instructions for modifying the content of the prediction table by accessing it.

9. Computer according to claim 8, taken in combination with claim 6, characterized in that the module further comprises an instruction for testing the value of pointer (pt), so as to modify the content of the branch prediction table.

10. Computer according to one of the preceding claims, characterized in that the hazard generator is arranged to be put into service permanently, with a low level priority.

11. Computer according to claim 10, taken in combination with one of claims 6 and 7, characterized in that the module comprises an instruction loop comprising one _. updating the table with the assignment of a value based on the random expression (PT2 ^Λ pt; pt ^Λ T), in order to propagate a hazard in the table.

12. Computer according to one of the preceding claims, in which the processor further comprises an instruction cache (CI), of volatile content, while the internal states of the processor further relate to the content of the instruction cache, characterized in that the hazard generator comprises a module comprising instructions for modifying the content of the instruction cache by accessing it.

13. The computer as claimed in claim 12, taken in combination with claim 11, characterized in that the module is arranged so that the size of the instruction loop is substantially equal to the size of the instruction cache.

14. Computer according to one of the preceding claims, -characterized in that the-module- includes --- an -instruction to declare a table (ARRAY) of selected memory size at least equal to the capacity of the translation cache memory address (TLB), as well as a pointer to the table.

15. Computer program product, characterized in that it includes instruction data capable of controlling the processor for performing a time measurement, from a given hardware counter, on sequences of instructions whose execution time depends at least in part on internal states of the processor, which are not directly accessible to the user and which are modified by interrupts, and generate random events from said measurement, the internal states being related inter alia to the presence or absence of data in at least one internal cache memory during the execution of at least one sequence of instructions.