WO2003025948A1 - Variable level memory - Google Patents
Variable level memory Download PDFInfo
- Publication number
- WO2003025948A1 WO2003025948A1 PCT/US2002/025092 US0225092W WO03025948A1 WO 2003025948 A1 WO2003025948 A1 WO 2003025948A1 US 0225092 W US0225092 W US 0225092W WO 03025948 A1 WO03025948 A1 WO 03025948A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- cell
- memory
- levels
- data
- density
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5641—Multilevel memory having cells with different number of storage levels
Definitions
- This invention relates generally to memory devices and particularly to memory devices with a multi-level cell architecture.
- a multi-level cell memory is comprised of multi-level cells, each of which is able to store multiple charge states or levels. Each of the charge states is associated with a memory element bit pattern.
- a flash EEPROM memory cell is configurable to store multiple threshold levels (V t ) . In a memory cell capable of storing two bits per cell, for example, four threshold levels (V t ) are used. Consequently, two bits are designated for each threshold level.
- the multi-level cell may store four charge states. Level three maintains a higher charge than level two. Level two maintains a higher charge than level one and level one maintains a higher charge than level zero.
- a reference voltage may separate the various charge states. For example, a first voltage reference may separate level three from level two, a second voltage reference may separate level two from level one and a third reference voltage may separate level one from level zero.
- a multi-level cell memory is able to store more than one bit of data based on the number of charge states. For example, multi-level cell memory that can store four charge states can store two bits of data, a multi-level cell memory that can store eight charge states can store three bits of data, and a multi-level cell memory that can store sixteen charge states can store four bits of data. For each of the N-bit multi-level cell memories, various memory element bit patterns can be associated with each of the different charge states .
- the number of charge states storable in a multi-level cell is not limited to powers of two.
- a multi-level cell memory with three charge states stores 1.5 bits of data.
- this multi-level cell is combined with additional decoding logic and coupled to a second similar multi-level cell, three bits of data are provided as the output of the two-cell combination.
- Various other multi-level cell combinations are possible as well.
- the nonvolatile memories store a large amount of data that is tolerant to a small number of bit errors .
- Applications may also have a small amount of data that is not tolerant to bit errors . Examples of such applications may include control structures, header information, to mention a few examples.
- These typical applications, where a relatively small amount of the overall storage requires higher fidelity, may include digital audio players, digital cameras, digital video recorders, to mention a few examples.
- Figure 1 is a block depiction of one embodiment of the present invention
- Figure 2 is a depiction of a cell in accordance with one embodiment of the present invention.
- Figure 3 is a depiction of another cell in accordance with another embodiment of the present invention.
- Figure 4 is a depiction of still another cell in accordance with one embodiment of the present invention.
- Figure 5 is a flow chart for software in accordance with one embodiment of the present invention.
- a processor 100 may be coupled through a bus 102 to a multi-level cell memory 104.
- the memory 104 contains an interface controller 105, a write state machine 106 and a multi-level cell memory array 150.
- the processor 100 is coupled by the bus 102 to both the interface controller 105 and the memory array 150 in one embodiment of the present invention.
- the interface controller 105 provides control over the multi-level cell memory array 150.
- the write state machine 106 communicates with the interface controller 105 and the memory array 150.
- the interface controller 105 passes data to be written into the array 150 to the state machine 106.
- the state machine 106 executes a sequence of events to write data into the array 150.
- the interface controller 105, the write state machine 106 and the multi-level cell memory array 150 are located on a single integrated circuit die.
- a cell may include only one bit of data at the first and last states of the cell.
- the number of bits per cell may be changed to increase the fidelity of the stored data.
- the scheme shown in Figure 4 or other higher density schemes may be utilized.
- the data may be spread in the cell, decreasing the density per cell and increasing the number of cells required to store all of the data.
- the integrity of the data storage will be improved. This is because it is easier to discern the differential voltage between significantly nonadjacent levels. In fact, the greater the distance between the levels, the easier it is to discern a differential voltage.
- only two levels are used, and in the embodiment shown in Figure 3, four levels are used. In the embodiment shown in Figure 4, all sixteen levels are utilized in accordance with some embodiments of the present invention.
- data may be stored in varying numbers of bits per cell depending on the type of data involved.
- some data may be packed closely as indicated for example in Figure 4 and other data may be spread farther apart, requiring additional numbers of cells to complete the data storage.
- the write algorithm 122 which may be implemented in software or hardware, initially identifies the number of bits per cell.
- the number of bits per cell may be derived from information included with the data indicating the desired fidelity. Based on the number of bits per cell, the packing of bits into each given cell may be adjusted. Thus, in some cases, denser packing may be utilized, for example as shown in Figure 4, and in other cases, looser or more spread apart packing may be utilized as shown in Figure 2.
- the packing of bits into each cell is adjusted as indicated in block 126.
- the bits are written to the cells as indicated in block 128. The number of bits per cell may be changed on the fly from cell to cell.
- the read process simply reverses the flow, ignoring the missing levels, and simply reading the actual data out of each cell.
- the spread apart data may then be repacked into a continuous data string.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02757016A EP1428221B1 (en) | 2001-09-18 | 2002-08-06 | Variable level memory |
KR1020047003885A KR100580017B1 (en) | 2001-09-18 | 2002-08-06 | Variable level memory |
DE60220931T DE60220931T2 (en) | 2001-09-18 | 2002-08-06 | MEMORY WITH VARIABLE LEVELS |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/955,282 | 2001-09-18 | ||
US09/955,282 US6643169B2 (en) | 2001-09-18 | 2001-09-18 | Variable level memory |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2003025948A1 true WO2003025948A1 (en) | 2003-03-27 |
Family
ID=25496611
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2002/025092 WO2003025948A1 (en) | 2001-09-18 | 2002-08-06 | Variable level memory |
Country Status (8)
Country | Link |
---|---|
US (2) | US6643169B2 (en) |
EP (1) | EP1428221B1 (en) |
KR (1) | KR100580017B1 (en) |
CN (1) | CN100585737C (en) |
AT (1) | ATE365967T1 (en) |
DE (1) | DE60220931T2 (en) |
TW (1) | TWI268511B (en) |
WO (1) | WO2003025948A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2028661A1 (en) | 2007-08-20 | 2009-02-25 | Marvell International Ltd. | Method and system for object-oriented data storage |
US8583857B2 (en) | 2007-08-20 | 2013-11-12 | Marvell World Trade Ltd. | Method and system for object-oriented data storage |
US9575886B2 (en) | 2013-01-29 | 2017-02-21 | Marvell World Trade Ltd. | Methods and apparatus for storing data to a solid state storage device based on data classification |
Families Citing this family (95)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7554842B2 (en) * | 2001-09-17 | 2009-06-30 | Sandisk Corporation | Multi-purpose non-volatile memory card |
US7178004B2 (en) * | 2003-01-31 | 2007-02-13 | Yan Polansky | Memory array programming circuit and a method for using the circuit |
US7117326B2 (en) * | 2003-06-26 | 2006-10-03 | Intel Corporation | Tracking modifications to a memory |
US7356755B2 (en) * | 2003-10-16 | 2008-04-08 | Intel Corporation | Error correction for multi-level cell memory with overwrite capability |
US7257033B2 (en) | 2005-03-17 | 2007-08-14 | Impinj, Inc. | Inverter non-volatile memory cell and array system |
US7715236B2 (en) * | 2005-03-30 | 2010-05-11 | Virage Logic Corporation | Fault tolerant non volatile memories and methods |
US7679957B2 (en) | 2005-03-31 | 2010-03-16 | Virage Logic Corporation | Redundant non-volatile memory cell |
US7272041B2 (en) | 2005-06-30 | 2007-09-18 | Intel Corporation | Memory array with pseudo single bit memory cell and method |
KR101202537B1 (en) | 2006-05-12 | 2012-11-19 | 애플 인크. | Combined distortion estimation and error correction coding for memory devices |
CN103258572B (en) | 2006-05-12 | 2016-12-07 | 苹果公司 | Distortion estimation in storage device and elimination |
WO2007132452A2 (en) | 2006-05-12 | 2007-11-22 | Anobit Technologies | Reducing programming error in memory devices |
US8239735B2 (en) | 2006-05-12 | 2012-08-07 | Apple Inc. | Memory Device with adaptive capacity |
US7568135B2 (en) | 2006-05-15 | 2009-07-28 | Apple Inc. | Use of alternative value in cell detection |
US7639542B2 (en) * | 2006-05-15 | 2009-12-29 | Apple Inc. | Maintenance operations for multi-level data storage cells |
US7613043B2 (en) | 2006-05-15 | 2009-11-03 | Apple Inc. | Shifting reference values to account for voltage sag |
US8000134B2 (en) | 2006-05-15 | 2011-08-16 | Apple Inc. | Off-die charge pump that supplies multiple flash devices |
US8060806B2 (en) * | 2006-08-27 | 2011-11-15 | Anobit Technologies Ltd. | Estimation of non-linear distortion in memory devices |
US7821826B2 (en) | 2006-10-30 | 2010-10-26 | Anobit Technologies, Ltd. | Memory cell readout using successive approximation |
WO2008053472A2 (en) | 2006-10-30 | 2008-05-08 | Anobit Technologies Ltd. | Reading memory cells using multiple thresholds |
US7924648B2 (en) | 2006-11-28 | 2011-04-12 | Anobit Technologies Ltd. | Memory power and performance management |
WO2008068747A2 (en) | 2006-12-03 | 2008-06-12 | Anobit Technologies Ltd. | Automatic defect management in memory devices |
US7593263B2 (en) | 2006-12-17 | 2009-09-22 | Anobit Technologies Ltd. | Memory device with reduced reading latency |
US7900102B2 (en) | 2006-12-17 | 2011-03-01 | Anobit Technologies Ltd. | High-speed programming of memory devices |
US8151166B2 (en) | 2007-01-24 | 2012-04-03 | Anobit Technologies Ltd. | Reduction of back pattern dependency effects in memory devices |
US7751240B2 (en) | 2007-01-24 | 2010-07-06 | Anobit Technologies Ltd. | Memory device with negative thresholds |
US7646636B2 (en) * | 2007-02-16 | 2010-01-12 | Mosaid Technologies Incorporated | Non-volatile memory with dynamic multi-mode operation |
CN101715595A (en) | 2007-03-12 | 2010-05-26 | 爱诺彼得技术有限责任公司 | Adaptive estimation of memory cell read thresholds |
US7958301B2 (en) * | 2007-04-10 | 2011-06-07 | Marvell World Trade Ltd. | Memory controller and method for memory pages with dynamically configurable bits per cell |
US8001320B2 (en) | 2007-04-22 | 2011-08-16 | Anobit Technologies Ltd. | Command interface for memory devices |
US7719896B1 (en) | 2007-04-24 | 2010-05-18 | Virage Logic Corporation | Configurable single bit/dual bits memory |
US8234545B2 (en) | 2007-05-12 | 2012-07-31 | Apple Inc. | Data storage with incremental redundancy |
US8429493B2 (en) | 2007-05-12 | 2013-04-23 | Apple Inc. | Memory device with internal signap processing unit |
US7925936B1 (en) | 2007-07-13 | 2011-04-12 | Anobit Technologies Ltd. | Memory device with non-uniform programming levels |
US7920423B1 (en) | 2007-07-31 | 2011-04-05 | Synopsys, Inc. | Non volatile memory circuit with tailored reliability |
US8259497B2 (en) | 2007-08-06 | 2012-09-04 | Apple Inc. | Programming schemes for multi-level analog memory cells |
US7802132B2 (en) * | 2007-08-17 | 2010-09-21 | Intel Corporation | Technique to improve and extend endurance and reliability of multi-level memory cells in a memory device |
US8174905B2 (en) | 2007-09-19 | 2012-05-08 | Anobit Technologies Ltd. | Programming orders for reducing distortion in arrays of multi-level analog memory cells |
US7773413B2 (en) | 2007-10-08 | 2010-08-10 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells in the presence of temperature variations |
US8527819B2 (en) | 2007-10-19 | 2013-09-03 | Apple Inc. | Data storage in analog memory cell arrays having erase failures |
US8068360B2 (en) | 2007-10-19 | 2011-11-29 | Anobit Technologies Ltd. | Reading analog memory cells using built-in multi-threshold commands |
US8000141B1 (en) | 2007-10-19 | 2011-08-16 | Anobit Technologies Ltd. | Compensation for voltage drifts in analog memory cells |
KR101509836B1 (en) | 2007-11-13 | 2015-04-06 | 애플 인크. | Optimized selection of memory units in multi-unit memory devices |
US8225181B2 (en) | 2007-11-30 | 2012-07-17 | Apple Inc. | Efficient re-read operations from memory devices |
US8209588B2 (en) | 2007-12-12 | 2012-06-26 | Anobit Technologies Ltd. | Efficient interference cancellation in analog memory cell arrays |
US8456905B2 (en) | 2007-12-16 | 2013-06-04 | Apple Inc. | Efficient data storage in multi-plane memory devices |
US8085586B2 (en) | 2007-12-27 | 2011-12-27 | Anobit Technologies Ltd. | Wear level estimation in analog memory cells |
US8156398B2 (en) | 2008-02-05 | 2012-04-10 | Anobit Technologies Ltd. | Parameter estimation based on error correction code parity check equations |
US7924587B2 (en) | 2008-02-21 | 2011-04-12 | Anobit Technologies Ltd. | Programming of analog memory cells using a single programming pulse per state transition |
US7864573B2 (en) | 2008-02-24 | 2011-01-04 | Anobit Technologies Ltd. | Programming analog memory cells for reduced variance after retention |
US8230300B2 (en) | 2008-03-07 | 2012-07-24 | Apple Inc. | Efficient readout from analog memory cells using data compression |
US8400858B2 (en) | 2008-03-18 | 2013-03-19 | Apple Inc. | Memory device with reduced sense time readout |
US8059457B2 (en) | 2008-03-18 | 2011-11-15 | Anobit Technologies Ltd. | Memory device with multiple-accuracy read commands |
KR20100010355A (en) | 2008-07-22 | 2010-02-01 | 삼성전자주식회사 | Multi-bit flash memory device and program and erase methods for the same |
US7924613B1 (en) | 2008-08-05 | 2011-04-12 | Anobit Technologies Ltd. | Data storage in analog memory cells with protection against programming interruption |
US8498151B1 (en) | 2008-08-05 | 2013-07-30 | Apple Inc. | Data storage in analog memory cells using modified pass voltages |
US8169825B1 (en) | 2008-09-02 | 2012-05-01 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells subjected to long retention periods |
US8949684B1 (en) | 2008-09-02 | 2015-02-03 | Apple Inc. | Segmented data storage |
US8000135B1 (en) | 2008-09-14 | 2011-08-16 | Anobit Technologies Ltd. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
US8482978B1 (en) | 2008-09-14 | 2013-07-09 | Apple Inc. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
US8239734B1 (en) | 2008-10-15 | 2012-08-07 | Apple Inc. | Efficient data storage in storage device arrays |
US8713330B1 (en) | 2008-10-30 | 2014-04-29 | Apple Inc. | Data scrambling in memory devices |
US8208304B2 (en) | 2008-11-16 | 2012-06-26 | Anobit Technologies Ltd. | Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N |
US8174857B1 (en) | 2008-12-31 | 2012-05-08 | Anobit Technologies Ltd. | Efficient readout schemes for analog memory cell devices using multiple read threshold sets |
US8248831B2 (en) | 2008-12-31 | 2012-08-21 | Apple Inc. | Rejuvenation of analog memory cells |
US8924661B1 (en) | 2009-01-18 | 2014-12-30 | Apple Inc. | Memory system including a controller and processors associated with memory devices |
US8228701B2 (en) | 2009-03-01 | 2012-07-24 | Apple Inc. | Selective activation of programming schemes in analog memory cell arrays |
US8259506B1 (en) | 2009-03-25 | 2012-09-04 | Apple Inc. | Database of memory read thresholds |
US8832354B2 (en) | 2009-03-25 | 2014-09-09 | Apple Inc. | Use of host system resources by memory controller |
US8238157B1 (en) | 2009-04-12 | 2012-08-07 | Apple Inc. | Selective re-programming of analog memory cells |
US8479080B1 (en) | 2009-07-12 | 2013-07-02 | Apple Inc. | Adaptive over-provisioning in memory systems |
US8495465B1 (en) | 2009-10-15 | 2013-07-23 | Apple Inc. | Error correction coding over multiple memory pages |
US8677054B1 (en) | 2009-12-16 | 2014-03-18 | Apple Inc. | Memory management schemes for non-volatile memory devices |
US8694814B1 (en) | 2010-01-10 | 2014-04-08 | Apple Inc. | Reuse of host hibernation storage space by memory controller |
US20110173462A1 (en) * | 2010-01-11 | 2011-07-14 | Apple Inc. | Controlling and staggering operations to limit current spikes |
US8572311B1 (en) | 2010-01-11 | 2013-10-29 | Apple Inc. | Redundant data storage in multi-die memory systems |
US8773925B2 (en) | 2010-02-23 | 2014-07-08 | Rambus Inc. | Multilevel DRAM |
US8402243B2 (en) | 2010-02-25 | 2013-03-19 | Apple Inc. | Dynamically allocating number of bits per cell for memory locations of a non-volatile memory |
US8694853B1 (en) | 2010-05-04 | 2014-04-08 | Apple Inc. | Read commands for reading interfering memory cells |
US8572423B1 (en) | 2010-06-22 | 2013-10-29 | Apple Inc. | Reducing peak current in memory systems |
US8595591B1 (en) | 2010-07-11 | 2013-11-26 | Apple Inc. | Interference-aware assignment of programming levels in analog memory cells |
US9104580B1 (en) | 2010-07-27 | 2015-08-11 | Apple Inc. | Cache memory for hybrid disk drives |
US8645794B1 (en) | 2010-07-31 | 2014-02-04 | Apple Inc. | Data storage in analog memory cells using a non-integer number of bits per cell |
US8856475B1 (en) | 2010-08-01 | 2014-10-07 | Apple Inc. | Efficient selection of memory blocks for compaction |
US8694854B1 (en) | 2010-08-17 | 2014-04-08 | Apple Inc. | Read threshold setting based on soft readout statistics |
US9021181B1 (en) | 2010-09-27 | 2015-04-28 | Apple Inc. | Memory management for unifying memory cell conditions by using maximum time intervals |
US8089807B1 (en) * | 2010-11-22 | 2012-01-03 | Ge Aviation Systems, Llc | Method and system for data storage |
US20120140556A1 (en) * | 2010-12-07 | 2012-06-07 | Macronix International Co., Ltd. | Method of operating flash memory |
KR20130060791A (en) * | 2011-11-30 | 2013-06-10 | 삼성전자주식회사 | Memory system, data storage device, memory card, and ssd including wear level control logic |
KR101949987B1 (en) * | 2012-12-18 | 2019-02-20 | 에스케이하이닉스 주식회사 | Data storage device and operating method thereof |
US9047211B2 (en) | 2013-03-15 | 2015-06-02 | SanDisk Technologies, Inc. | Managing data reliability |
US9690656B2 (en) * | 2015-02-27 | 2017-06-27 | Microsoft Technology Licensing, Llc | Data encoding on single-level and variable multi-level cell storage |
US9786386B2 (en) | 2015-02-27 | 2017-10-10 | Microsoft Technology Licensing, Llc | Dynamic approximate storage for custom applications |
US11081168B2 (en) * | 2019-05-23 | 2021-08-03 | Hefei Reliance Memory Limited | Mixed digital-analog memory devices and circuits for secure storage and computing |
US11556416B2 (en) | 2021-05-05 | 2023-01-17 | Apple Inc. | Controlling memory readout reliability and throughput by adjusting distance between read thresholds |
US11847342B2 (en) | 2021-07-28 | 2023-12-19 | Apple Inc. | Efficient transfer of hard data and confidence levels in reading a nonvolatile memory |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0788113A1 (en) * | 1996-01-31 | 1997-08-06 | STMicroelectronics S.r.l. | Multilevel memory circuits and corresponding reading and writing methods |
US5812447A (en) * | 1995-08-02 | 1998-09-22 | Sanyo Electric Co., Ltd. | Method and apparatus to write and/or read two types of data from memory |
US6097637A (en) * | 1994-06-02 | 2000-08-01 | Intel Corporation | Dynamic single bit per cell to multiple bit per cell memory |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5424978A (en) * | 1993-03-15 | 1995-06-13 | Nippon Steel Corporation | Non-volatile semiconductor memory cell capable of storing more than two different data and method of using the same |
US5828601A (en) * | 1993-12-01 | 1998-10-27 | Advanced Micro Devices, Inc. | Programmed reference |
US5515317A (en) * | 1994-06-02 | 1996-05-07 | Intel Corporation | Addressing modes for a dynamic single bit per cell to multiple bit per cell memory |
KR100327421B1 (en) * | 1997-12-31 | 2002-07-27 | 주식회사 하이닉스반도체 | Program system of non-volatile memory device and programming method thereof |
US6215697B1 (en) * | 1999-01-14 | 2001-04-10 | Macronix International Co., Ltd. | Multi-level memory cell device and method for self-converged programming |
US6205057B1 (en) * | 2000-02-15 | 2001-03-20 | Advanced Micro Devices | System and method for detecting flash memory threshold voltages |
US6363008B1 (en) * | 2000-02-17 | 2002-03-26 | Multi Level Memory Technology | Multi-bit-cell non-volatile memory with maximized data capacity |
US6396744B1 (en) * | 2000-04-25 | 2002-05-28 | Multi Level Memory Technology | Flash memory with dynamic refresh |
US6396742B1 (en) * | 2000-07-28 | 2002-05-28 | Silicon Storage Technology, Inc. | Testing of multilevel semiconductor memory |
-
2001
- 2001-09-18 US US09/955,282 patent/US6643169B2/en not_active Expired - Lifetime
-
2002
- 2002-08-06 CN CN02822880A patent/CN100585737C/en not_active Expired - Lifetime
- 2002-08-06 DE DE60220931T patent/DE60220931T2/en not_active Expired - Lifetime
- 2002-08-06 EP EP02757016A patent/EP1428221B1/en not_active Expired - Lifetime
- 2002-08-06 WO PCT/US2002/025092 patent/WO2003025948A1/en active IP Right Grant
- 2002-08-06 KR KR1020047003885A patent/KR100580017B1/en active IP Right Grant
- 2002-08-06 AT AT02757016T patent/ATE365967T1/en not_active IP Right Cessation
- 2002-08-28 TW TW091119529A patent/TWI268511B/en not_active IP Right Cessation
-
2003
- 2003-09-18 US US10/666,988 patent/US6870767B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6097637A (en) * | 1994-06-02 | 2000-08-01 | Intel Corporation | Dynamic single bit per cell to multiple bit per cell memory |
US5812447A (en) * | 1995-08-02 | 1998-09-22 | Sanyo Electric Co., Ltd. | Method and apparatus to write and/or read two types of data from memory |
EP0788113A1 (en) * | 1996-01-31 | 1997-08-06 | STMicroelectronics S.r.l. | Multilevel memory circuits and corresponding reading and writing methods |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2028661A1 (en) | 2007-08-20 | 2009-02-25 | Marvell International Ltd. | Method and system for object-oriented data storage |
US8583857B2 (en) | 2007-08-20 | 2013-11-12 | Marvell World Trade Ltd. | Method and system for object-oriented data storage |
US9575886B2 (en) | 2013-01-29 | 2017-02-21 | Marvell World Trade Ltd. | Methods and apparatus for storing data to a solid state storage device based on data classification |
US10157022B2 (en) | 2013-01-29 | 2018-12-18 | Marvell World Trade Ltd. | Methods and apparatus for storing data to a solid state storage device based on data classification |
Also Published As
Publication number | Publication date |
---|---|
ATE365967T1 (en) | 2007-07-15 |
US20040057355A1 (en) | 2004-03-25 |
KR20040044938A (en) | 2004-05-31 |
CN100585737C (en) | 2010-01-27 |
US6870767B2 (en) | 2005-03-22 |
CN1589480A (en) | 2005-03-02 |
DE60220931T2 (en) | 2007-10-18 |
EP1428221B1 (en) | 2007-06-27 |
DE60220931D1 (en) | 2007-08-09 |
US6643169B2 (en) | 2003-11-04 |
EP1428221A1 (en) | 2004-06-16 |
KR100580017B1 (en) | 2006-05-12 |
US20030053333A1 (en) | 2003-03-20 |
TWI268511B (en) | 2006-12-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6643169B2 (en) | Variable level memory | |
US8788908B2 (en) | Data storage system having multi-bit memory device and on-chip buffer program method thereof | |
US8964468B2 (en) | Data storage system having multi-bit memory device and operating method thereof | |
EP1199725B1 (en) | Method for storing and reading data in a multibit nonvolatile memory with a non-binary number of bits per cell | |
CN104934062B (en) | Nonvolatile memory and wiring method | |
EP1807841B1 (en) | Memory device and method providing an average threshold based refresh mechanism | |
US20050086574A1 (en) | Error correction for multi-level cell memory with overwrite capability | |
US8677056B2 (en) | Methods and apparatus for interfacing between a flash memory controller and a flash memory array | |
KR20210020964A (en) | Accelerated soft read for multi-level cell nonvolatile memories | |
JP2005100527A (en) | Semiconductor nonvolatile storage device | |
US8812777B2 (en) | Nonvolatile memory device | |
US4679196A (en) | Semiconductor memory device with a bit error detecting function | |
US20040088502A1 (en) | Method and apparatus for virtually partitioning an integrated multilevel nonvolatile memory circuit | |
US6785860B1 (en) | Error-correcting code adapted for memories that store multiple bits per storage cell | |
US6483743B1 (en) | Multilevel cell memory architecture | |
US8583857B2 (en) | Method and system for object-oriented data storage | |
JP2005063662A (en) | Method for combining multilevel memory cells and providing error correction mechanism for them | |
JP4079458B2 (en) | Multilevel data storage / reproduction method and multilevel data storage / reproduction apparatus | |
TWI795819B (en) | semiconductor memory, non-volatile memory |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BY BZ CA CH CN CO CR CU CZ DE DM DZ EC EE ES FI GB GD GE GH HR HU ID IL IN IS JP KE KG KP KR LC LK LR LS LT LU LV MA MD MG MN MW MX MZ NO NZ OM PH PL PT RU SD SE SG SI SK SL TJ TM TN TR TZ UA UG UZ VN YU ZA ZM |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GH GM KE LS MW MZ SD SL SZ UG ZM ZW AM AZ BY KG KZ RU TJ TM AT BE BG CH CY CZ DK EE ES FI FR GB GR IE IT LU MC PT SE SK TR BF BJ CF CG CI GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 1020047003885 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2002757016 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 20028228804 Country of ref document: CN |
|
WWP | Wipo information: published in national office |
Ref document number: 2002757016 Country of ref document: EP |
|
NENP | Non-entry into the national phase |
Ref country code: JP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: JP |
|
WWG | Wipo information: grant in national office |
Ref document number: 2002757016 Country of ref document: EP |