WO2003021495A3 - Model-based logic design - Google Patents

Model-based logic design Download PDF

Info

Publication number
WO2003021495A3
WO2003021495A3 PCT/US2002/027005 US0227005W WO03021495A3 WO 2003021495 A3 WO2003021495 A3 WO 2003021495A3 US 0227005 W US0227005 W US 0227005W WO 03021495 A3 WO03021495 A3 WO 03021495A3
Authority
WO
WIPO (PCT)
Prior art keywords
model
data structure
logic design
based logic
architectural
Prior art date
Application number
PCT/US2002/027005
Other languages
French (fr)
Other versions
WO2003021495A9 (en
WO2003021495A2 (en
Inventor
William Wheeler
Matthew Adiletta
Timothy Fennell
Christopher Clark
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of WO2003021495A2 publication Critical patent/WO2003021495A2/en
Publication of WO2003021495A9 publication Critical patent/WO2003021495A9/en
Publication of WO2003021495A3 publication Critical patent/WO2003021495A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/323—Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Abstract

A rechnique for designing a logic circuit includes specifying a model. The model including combinatorial blocks, state elements and graphical library elements. The technique maintains a data structure representative of the model, and generates an architectural model and an implementation model from the data structure. The data structure represents a descriptive net list of the model. The architectural model includes C++ code and the implementation model includes Verilog.
PCT/US2002/027005 2001-08-28 2002-08-23 Model-based logic design WO2003021495A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/941,158 US7093224B2 (en) 2001-08-28 2001-08-28 Model-based logic design
US09/941,158 2001-08-28

Publications (3)

Publication Number Publication Date
WO2003021495A2 WO2003021495A2 (en) 2003-03-13
WO2003021495A9 WO2003021495A9 (en) 2003-09-04
WO2003021495A3 true WO2003021495A3 (en) 2004-01-29

Family

ID=25476023

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/027005 WO2003021495A2 (en) 2001-08-28 2002-08-23 Model-based logic design

Country Status (2)

Country Link
US (1) US7093224B2 (en)
WO (1) WO2003021495A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7107201B2 (en) * 2001-08-29 2006-09-12 Intel Corporation Simulating a logic design
US20050120340A1 (en) * 2003-12-01 2005-06-02 Skazinski Joseph G. Apparatus, system, and method for automated generation of embedded systems software
US8156459B1 (en) * 2009-11-10 2012-04-10 Xilinx, Inc. Detecting differences between high level block diagram models
WO2013018061A1 (en) 2011-08-03 2013-02-07 Ben Gurion University Of The Negev Research And Development Authority Device and method for dual-mode logic
WO2013118119A1 (en) * 2012-02-09 2013-08-15 B.G. Negev Technologies & Applications Ltd. Design of dual mode logic circuits
DE102014206607B3 (en) * 2014-04-04 2015-10-01 Siemens Aktiengesellschaft Method for operating an automation device, processor for use in the method and process device according to the method and system
CN112100797B (en) * 2019-12-16 2021-06-01 佛山科学技术学院 Internet topology simulation generation method and system based on structural model
CN115392160B (en) * 2022-06-10 2024-04-09 无锡芯光互连技术研究院有限公司 Format conversion method for circuit diagram description file

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0433066A2 (en) * 1989-12-15 1991-06-19 Hewlett-Packard Company Common symbol library architecture
US5220512A (en) * 1990-04-19 1993-06-15 Lsi Logic Corporation System for simultaneous, interactive presentation of electronic circuit diagrams and simulation data
WO2000065492A1 (en) * 1999-04-27 2000-11-02 Magma Design Automation, Inc. Method for storing multiple levels of design data in a common database
EP1065611A2 (en) * 1995-10-23 2001-01-03 Interuniversitair Microelektronica Centrum Vzw A design environment for hardware/software co-design

Family Cites Families (107)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4703435A (en) 1984-07-16 1987-10-27 International Business Machines Corporation Logic Synthesizer
US5267175A (en) 1986-09-12 1993-11-30 Digital Equipment Corporation Data base access mechanism for rules utilized by a synthesis procedure for logic circuit design
US5212650A (en) 1986-09-12 1993-05-18 Digital Equipment Corporation Procedure and data structure for synthesis and transformation of logic circuit designs
US5301318A (en) 1988-05-13 1994-04-05 Silicon Systems, Inc. Hierarchical netlist extraction tool
US4970664A (en) 1988-06-10 1990-11-13 Kaiser Richard R Critical path analyzer with path context window
US5128871A (en) 1990-03-07 1992-07-07 Advanced Micro Devices, Inc. Apparatus and method for allocation of resoures in programmable logic devices
US5384710A (en) 1990-03-13 1995-01-24 National Semiconductor Corporation Circuit level netlist generation
US5278769A (en) 1991-04-12 1994-01-11 Lsi Logic Corporation Automatic logic model generation from schematic data base
US5544067A (en) 1990-04-06 1996-08-06 Lsi Logic Corporation Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation
US5572437A (en) 1990-04-06 1996-11-05 Lsi Logic Corporation Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models
US5553002A (en) 1990-04-06 1996-09-03 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, using milestone matrix incorporated into user-interface
US5287289A (en) 1990-04-13 1994-02-15 Hitachi, Ltd. Logic synthesis method
US5258919A (en) 1990-06-28 1993-11-02 National Semiconductor Corporation Structured logic design method using figures of merit and a flowchart methodology
US5717928A (en) 1990-11-07 1998-02-10 Matra Hachette Sa System and a method for obtaining a mask programmable device using a logic description and a field programmable device implementing the logic description
US5297053A (en) 1991-06-04 1994-03-22 Computervision Corporation Method and apparatus for deferred package assignment for components of an electronic circuit for a printed circuit board
US5615356A (en) 1992-04-21 1997-03-25 Cpu Technology, Inc. Method and apparatus for interactively displaying signal information during computer simulation of an electrical circuit
JPH05315448A (en) 1992-04-27 1993-11-26 Nec Corp Integrated circuit device and its layout method
US5666289A (en) 1992-10-07 1997-09-09 Lsi Logic Corporation Flexible design system
US5694579A (en) 1993-02-18 1997-12-02 Digital Equipment Corporation Using pre-analysis and a 2-state optimistic model to reduce computation in transistor circuit simulation
JP2815281B2 (en) 1993-04-19 1998-10-27 株式会社ピーエフユー Digital circuit design support system and method
JP2768889B2 (en) 1993-06-07 1998-06-25 株式会社東芝 Logic simulation equipment
JP2856640B2 (en) 1993-07-08 1999-02-10 株式会社日立製作所 Logic schematic editor system
US5513119A (en) 1993-08-10 1996-04-30 Mitsubishi Semiconductor America, Inc. Hierarchical floorplanner for gate array design layout
JP3144967B2 (en) 1993-11-08 2001-03-12 株式会社日立製作所 Semiconductor integrated circuit and method of manufacturing the same
JP3154885B2 (en) 1993-12-28 2001-04-09 株式会社東芝 Application specific integrated circuit and method of configuring the same
US5506788A (en) 1994-01-13 1996-04-09 Lsi Logic Corporation Similarity-extraction force-oriented floor planner
US6044211A (en) 1994-03-14 2000-03-28 C.A.E. Plus, Inc. Method for graphically representing a digital device as a behavioral description with data and control flow elements, and for converting the behavioral description to a structural description
JP2972540B2 (en) 1994-03-24 1999-11-08 松下電器産業株式会社 LSI automatic design system and LSI automatic design method
US5937190A (en) 1994-04-12 1999-08-10 Synopsys, Inc. Architecture and methods for a hardware description language source level analysis and debugging system
US6132109A (en) 1994-04-12 2000-10-17 Synopsys, Inc. Architecture and methods for a hardware description language source level debugging system
US5475605A (en) 1994-05-26 1995-12-12 Cadence Design Systems, Inc. Timing analysis for logic optimization using target library delay values
US5604889A (en) 1994-06-15 1997-02-18 Texas Instruments Incorporated Memory management system for checkpointed logic simulator with increased locality of data
US6208954B1 (en) 1994-09-16 2001-03-27 Wind River Systems, Inc. Method for scheduling event sequences
US5903469A (en) 1994-11-08 1999-05-11 Synopsys, Inc. Method of extracting layout parasitics for nets of an integrated circuit using a connectivity-based approach
US5629857A (en) 1994-11-15 1997-05-13 International Business Machines Corporation Method and system for indicating a status of a circuit design
JP2912174B2 (en) 1994-12-27 1999-06-28 日本電気株式会社 Library group and semiconductor integrated circuit using the same
JP3351651B2 (en) 1995-04-07 2002-12-03 富士通株式会社 Interactive circuit design equipment
JPH08287111A (en) 1995-04-14 1996-11-01 Nec Ic Microcomput Syst Ltd Automatic layout system
US5706476A (en) 1995-06-05 1998-01-06 Synopsys, Inc. Method and apparatus for use of the undefined logic state and mixed multiple-state abstractions in digital logic simulation
US5841663A (en) 1995-09-14 1998-11-24 Vlsi Technology, Inc. Apparatus and method for synthesizing integrated circuits using parameterized HDL modules
US5809283A (en) 1995-09-29 1998-09-15 Synopsys, Inc. Simulator for simulating systems including mixed triggers
US5831869A (en) 1995-12-15 1998-11-03 Unisys Corporation Method of compacting data representations of hierarchical logic designs used for static timing analysis
US6117183A (en) 1996-01-08 2000-09-12 Fujitsu Limited Interactive CAD apparatus for designing packaging of logic circuit design
US5724250A (en) 1996-02-07 1998-03-03 Unisys Corporation Method and apparatus for performing drive strength adjust optimization in a circuit design
US6236956B1 (en) 1996-02-16 2001-05-22 Avant! Corporation Component-based analog and mixed-signal simulation model development including newton step manager
US5963724A (en) 1996-02-16 1999-10-05 Analogy, Inc. Component-based analog and mixed-signal simulation model development
US5673198A (en) 1996-03-29 1997-09-30 Xilinx, Inc. Concurrent electronic circuit design and implementation
US5905883A (en) 1996-04-15 1999-05-18 Sun Microsystems, Inc. Verification system for circuit simulator
US6234658B1 (en) 1996-06-07 2001-05-22 Duality Semiconductor, Inc. Method and apparatus for producing signal processing circuits in the delta sigma domain
US5892682A (en) 1996-06-17 1999-04-06 Motorola, Inc. Method and apparatus for generating a hierarchical interconnection description of an integrated circuit design and using the description to edit the integrated circuit design
US5757655A (en) 1996-08-26 1998-05-26 Micron Technology, Inc. Method and system for producing dynamic property forms and compacting property databases
US5949692A (en) 1996-08-28 1999-09-07 Synopsys, Inc. Hierarchical scan architecture for design for test applications
GB2318665B (en) 1996-10-28 2000-06-28 Altera Corp Work group computing for electronic design automation
US6120549A (en) 1997-01-06 2000-09-19 Xilinx, Inc. Method and apparatus for generating optimized functional macros
US6516456B1 (en) 1997-01-27 2003-02-04 Unisys Corporation Method and apparatus for selectively viewing nets within a database editor tool
US6233540B1 (en) * 1997-03-14 2001-05-15 Interuniversitair Micro-Elektronica Centrum Design environment and a method for generating an implementable description of a digital system
JPH10327047A (en) 1997-05-22 1998-12-08 Sony Corp Semiconductor integrated circuit and its design method
US6053947A (en) * 1997-05-31 2000-04-25 Lucent Technologies, Inc. Simulation model using object-oriented programming
US6152612A (en) * 1997-06-09 2000-11-28 Synopsys, Inc. System and method for system level and circuit level modeling and design simulation using C++
US6066179A (en) 1997-06-13 2000-05-23 University Of Edinburgh Property estimation of an integrated circuit
US6233723B1 (en) 1997-08-28 2001-05-15 Vlsi Technology, Inc. Circuit behavioral information analysis apparatus and a method of analyzing behavioral information of a circuit
US5974242A (en) 1997-09-25 1999-10-26 The United States Of America As Represented By The Secretary Of The Army Methods and computer programs for minimizing logic circuit design using identity cells
JPH11126215A (en) 1997-10-22 1999-05-11 Nec Corp Delay analytical result display device
JP4128251B2 (en) 1997-10-23 2008-07-30 富士通株式会社 Wiring density prediction method and cell placement apparatus
US6135647A (en) * 1997-10-23 2000-10-24 Lsi Logic Corporation System and method for representing a system level RTL design using HDL independent objects and translation to synthesizable RTL code
US6421815B1 (en) * 1998-01-09 2002-07-16 Synopsys, Inc. Method and apparatus for optimized partitioning of finite state machines synthesized from hierarchical high-level descriptions
US6145117A (en) 1998-01-30 2000-11-07 Tera Systems Incorporated Creating optimized physical implementations from high-level descriptions of electronic design using placement based information
US6292931B1 (en) 1998-02-20 2001-09-18 Lsi Logic Corporation RTL analysis tool
US6243851B1 (en) 1998-03-27 2001-06-05 Xilinx, Inc. Heterogeneous method for determining module placement in FPGAs
US6178541B1 (en) 1998-03-30 2001-01-23 Lsi Logic Corporation PLD/ASIC hybrid integrated circuit
JP3461443B2 (en) 1998-04-07 2003-10-27 松下電器産業株式会社 Semiconductor device, semiconductor device design method, recording medium, and semiconductor device design support device
JP4090118B2 (en) 1998-06-19 2008-05-28 富士通株式会社 LSI manufacturing method and recording medium recording layout program
US6477688B1 (en) 1998-07-17 2002-11-05 David E. Wallace Logic equivalence leveraged placement and routing of an IC design
US6473885B1 (en) 1998-07-17 2002-10-29 Mentor Graphics Corporation Digital circuit layout techniques using circuit decomposition and pin swapping
US6219822B1 (en) 1998-08-05 2001-04-17 International Business Machines Corporation Method and system for tuning of components for integrated circuits
US6381565B1 (en) 1998-08-21 2002-04-30 Nec Corporation Functional logic circuit verification device
US6480985B1 (en) * 1998-08-26 2002-11-12 Mentor Graphics Corporation Method and apparatus for graphically presenting an integrated circuit design
US6226780B1 (en) 1998-08-31 2001-05-01 Mentor Graphics Corporation Circuit design method and apparatus supporting a plurality of hardware design languages
US6272671B1 (en) 1998-09-11 2001-08-07 Lsi Logic Corporation Extractor and schematic viewer for a design representation, and associated method
US6505341B1 (en) 1998-11-10 2003-01-07 Scientronix, Inc. System and method for programming a logic control unit
US6275973B1 (en) 1998-10-30 2001-08-14 Lsi Logic Corporation Integrated circuit design with delayed cell selection
US6353806B1 (en) 1998-11-23 2002-03-05 Lucent Technologies Inc. System level hardware simulator and its automation
US6401230B1 (en) 1998-12-04 2002-06-04 Altera Corporation Method of generating customized megafunctions
US6381563B1 (en) 1999-01-22 2002-04-30 Cadence Design Systems, Inc. System and method for simulating circuits using inline subcircuits
US6477683B1 (en) 1999-02-05 2002-11-05 Tensilica, Inc. Automated processor generation system for designing a configurable processor and method for the same
US6353915B1 (en) 1999-04-01 2002-03-05 Unisys Corporation Methods for evaluating systems of electronic components
US6327693B1 (en) 1999-04-08 2001-12-04 Chung-Kuan Cheng Interconnect delay driven placement and routing of an integrated circuit design
JP3501674B2 (en) 1999-04-21 2004-03-02 日本電気株式会社 Printed circuit board characteristic evaluation apparatus, printed circuit board characteristic evaluation method, and storage medium
US6427223B1 (en) * 1999-04-30 2002-07-30 Synopsys, Inc. Method and apparatus for adaptive verification of circuit designs
US6298468B1 (en) 1999-05-04 2001-10-02 Prosper Design Systems Pte. Ltd. Placement-based pin optimization method and apparatus for computer-aided circuit design
US6366874B1 (en) 1999-05-24 2002-04-02 Novas Software, Inc. System and method for browsing graphically an electronic design based on a hardware description language specification
JP2001022816A (en) 1999-07-12 2001-01-26 Matsushita Electric Ind Co Ltd Layout method for semiconductor integrated circuit device
US6519755B1 (en) * 1999-08-16 2003-02-11 Sequence Design, Inc. Method and apparatus for logic synthesis with elaboration
US6574787B1 (en) 1999-08-16 2003-06-03 Sequence Design, Inc. Method and apparatus for logic synthesis (word oriented netlist)
US6438731B1 (en) 1999-09-13 2002-08-20 Synopsys, Inc. Integrated circuit models having associated timing exception information therewith for use in circuit design optimizations
US6449762B1 (en) 1999-10-07 2002-09-10 Synplicity, Inc. Maintaining correspondence between text and schematic representations of circuit elements in circuit synthesis
US6539536B1 (en) 2000-02-02 2003-03-25 Synopsys, Inc. Electronic design automation system and methods utilizing groups of multiple cells having loop-back connections for modeling port electrical characteristics
US6769098B2 (en) 2000-02-29 2004-07-27 Matsushita Electric Industrial Co., Ltd. Method of physical design for integrated circuit
US6591407B1 (en) 2000-03-01 2003-07-08 Sequence Design, Inc. Method and apparatus for interconnect-driven optimization of integrated circuit design
US6490545B1 (en) 2000-03-06 2002-12-03 Sony Corporation Method and apparatus for adaptive co-verification of software and hardware designs
US6519742B1 (en) 2000-03-06 2003-02-11 Synplicity, Inc. Local naming for HDL compilation
AU2001266660A1 (en) * 2000-06-02 2001-12-17 Virtio Corporation Method and system for virtual prototyping
US6487698B1 (en) * 2001-05-04 2002-11-26 Lsi Logic Corporation Process, apparatus and program for transforming program language description of an IC to an RTL description
US6523156B2 (en) 2001-06-08 2003-02-18 Library Technologies, Inc. Apparatus and methods for wire load independent logic synthesis and timing closure with constant replacement delay cell libraries
US6477689B1 (en) * 2001-06-13 2002-11-05 The Boeing Company Architectural structure of a process netlist design tool
US6868526B2 (en) * 2001-07-18 2005-03-15 The Mathworks, Inc. Graphical subclassing
US7613716B2 (en) * 2001-07-20 2009-11-03 The Mathworks, Inc. Partitioning for model-based design

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0433066A2 (en) * 1989-12-15 1991-06-19 Hewlett-Packard Company Common symbol library architecture
US5220512A (en) * 1990-04-19 1993-06-15 Lsi Logic Corporation System for simultaneous, interactive presentation of electronic circuit diagrams and simulation data
EP1065611A2 (en) * 1995-10-23 2001-01-03 Interuniversitair Microelektronica Centrum Vzw A design environment for hardware/software co-design
WO2000065492A1 (en) * 1999-04-27 2000-11-02 Magma Design Automation, Inc. Method for storing multiple levels of design data in a common database

Also Published As

Publication number Publication date
US20030046649A1 (en) 2003-03-06
US7093224B2 (en) 2006-08-15
WO2003021495A9 (en) 2003-09-04
WO2003021495A2 (en) 2003-03-13

Similar Documents

Publication Publication Date Title
WO2005045743A3 (en) System and method for rfid system integration
WO2004084086A8 (en) Data flow machine
GB0323780D0 (en) A data brokering method and system
WO2001045258A3 (en) Method for implementing a physical design for a dynamically reconfigurable logic circuit
EP1444693A4 (en) Data cartridge library
AU2002228693A1 (en) Three-dimensional model colorization during model construction from computer aided design data
AU2003223671A1 (en) Initializing, maintaining, updating and recovering secure operation within an integrated system employing a data access control function
WO2006034353A3 (en) Method and system for transferring data between a discrete event environment and an external environment
GB2367390B (en) Software for designing modelling or performing digital signal procesing
WO2005010690A3 (en) Design for manufacturability
WO2003021495A3 (en) Model-based logic design
AU2003296081A1 (en) Pattern forming method, electronic device manufacturing method, electronic device, and photomask
GB2385691B (en) Method for designing a system LSI
WO2005008725A3 (en) Nested voltage island architecture
EP1312928A4 (en) Method for making equivalent circuit model of passive element, simulator, and storage medium
AU2003220113A8 (en) System for standardizing updates of data on a plurality of electronic devices
GB2373349B (en) Data definition language
AU2003247435A1 (en) Combinatorial chemical library ii
WO2003027912A3 (en) Distributed system and method for computer aided multi-component system design
AU2003230733A8 (en) Logic analyzer data retrieving circuit and its retrieving method
GB0102706D0 (en) Data structures
WO2003021492A3 (en) Simulating a logic design
WO2006047089A3 (en) Memory output data systems and methods with feedback
EP1449055A4 (en) A system and method for communicating between a number of elements and a method for configuring and testing the system
ITRM20030012A0 (en) METHOD AND CIRCUIT SYSTEM FOR THE SYNCHRONOUS TRANSMISSION OF DIGITAL SIGNALS THROUGH A BUS.

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG UZ VN YU ZA ZM ZW

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BY BZ CA CH CN CO CR CU CZ DE DM DZ EC EE ES FI GB GD GE GH HR HU ID IL IN IS JP KE KG KP KR LC LK LR LS LT LU LV MA MD MG MN MW MX MZ NO NZ OM PH PL PT RU SD SE SG SI SK SL TJ TM TN TR TZ UA UG UZ VN YU ZA ZM

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LU MC NL PT SE SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ UG ZM ZW AM AZ BY KG KZ RU TJ TM AT BE BG CH CY CZ DK EE ES FI FR GB GR IE IT LU MC PT SE SK TR BF BJ CF CG CI GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
COP Corrected version of pamphlet

Free format text: PAGES 1/4-4/4, DRAWINGS, REPLACED BY NEW PAGES 1/2-2/2; DUE TO LATE TRANSMITTAL BY THE RECEIVING OFFICE

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP