WO2003021491A3 - Real-time connection error checking method and process - Google Patents
Real-time connection error checking method and process Download PDFInfo
- Publication number
- WO2003021491A3 WO2003021491A3 PCT/US2002/026846 US0226846W WO03021491A3 WO 2003021491 A3 WO2003021491 A3 WO 2003021491A3 US 0226846 W US0226846 W US 0226846W WO 03021491 A3 WO03021491 A3 WO 03021491A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- real
- circuitry component
- error checking
- checking method
- connection error
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
Abstract
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02768672A EP1421525A2 (en) | 2001-08-29 | 2002-08-23 | Real-time connection error checking method and process |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/941,498 | 2001-08-29 | ||
US09/941,498 US6640329B2 (en) | 2001-08-29 | 2001-08-29 | Real-time connection error checking method and process |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2003021491A2 WO2003021491A2 (en) | 2003-03-13 |
WO2003021491A3 true WO2003021491A3 (en) | 2004-03-04 |
Family
ID=25476585
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2002/026846 WO2003021491A2 (en) | 2001-08-29 | 2002-08-23 | Real-time connection error checking method and process |
Country Status (4)
Country | Link |
---|---|
US (1) | US6640329B2 (en) |
EP (1) | EP1421525A2 (en) |
TW (1) | TWI227845B (en) |
WO (1) | WO2003021491A2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4586926B2 (en) * | 2008-03-04 | 2010-11-24 | 日本電気株式会社 | Circuit verification apparatus, circuit verification program, and circuit verification method |
JP6146224B2 (en) * | 2013-09-12 | 2017-06-14 | 株式会社ソシオネクスト | Determination method, determination program, and determination apparatus |
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EP0901088A2 (en) * | 1997-09-02 | 1999-03-10 | Hewlett-Packard Company | Framework for rules checking |
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-
2001
- 2001-08-29 US US09/941,498 patent/US6640329B2/en not_active Expired - Fee Related
-
2002
- 2002-08-23 EP EP02768672A patent/EP1421525A2/en not_active Withdrawn
- 2002-08-23 WO PCT/US2002/026846 patent/WO2003021491A2/en not_active Application Discontinuation
- 2002-08-28 TW TW091119553A patent/TWI227845B/en not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5220512A (en) * | 1990-04-19 | 1993-06-15 | Lsi Logic Corporation | System for simultaneous, interactive presentation of electronic circuit diagrams and simulation data |
WO1998037475A2 (en) * | 1997-02-07 | 1998-08-27 | Morphologic, Inc. | System and method for designing electronic circuits |
EP0901088A2 (en) * | 1997-09-02 | 1999-03-10 | Hewlett-Packard Company | Framework for rules checking |
Also Published As
Publication number | Publication date |
---|---|
TWI227845B (en) | 2005-02-11 |
US20030046644A1 (en) | 2003-03-06 |
US6640329B2 (en) | 2003-10-28 |
EP1421525A2 (en) | 2004-05-26 |
WO2003021491A2 (en) | 2003-03-13 |
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