WO2003009660A1 - Method and material for manufacturing circuit-formed substrate - Google Patents

Method and material for manufacturing circuit-formed substrate Download PDF

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Publication number
WO2003009660A1
WO2003009660A1 PCT/JP2002/007262 JP0207262W WO03009660A1 WO 2003009660 A1 WO2003009660 A1 WO 2003009660A1 JP 0207262 W JP0207262 W JP 0207262W WO 03009660 A1 WO03009660 A1 WO 03009660A1
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WO
WIPO (PCT)
Prior art keywords
circuit
manufacturing
substrate material
substrate
forming
Prior art date
Application number
PCT/JP2002/007262
Other languages
French (fr)
Japanese (ja)
Inventor
Toshihiro Nishii
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Priority to DE60235301T priority Critical patent/DE60235301D1/en
Priority to JP2003514862A priority patent/JPWO2003009660A1/en
Priority to US10/380,661 priority patent/US7059044B2/en
Priority to EP02749309A priority patent/EP1408726B1/en
Publication of WO2003009660A1 publication Critical patent/WO2003009660A1/en

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0313Organic insulating material
    • H05K1/0353Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0366Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0026Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4632Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating thermoplastic or uncured resin sheets comprising printed circuits without added adhesive materials between the sheets
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H05K3/4655Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern by using a laminate characterized by the insulating layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0313Organic insulating material
    • H05K1/0353Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0373Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0183Dielectric layers
    • H05K2201/0191Dielectric layers wherein the thickness of the dielectric plays an important role
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203Fillers and particles
    • H05K2201/0206Materials
    • H05K2201/0209Inorganic, non-metallic particles
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0275Fibers and reinforcement materials
    • H05K2201/029Woven fibrous reinforcement or textile
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0335Layered conductors or foils
    • H05K2201/0355Metal foils
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09581Applying an insulating coating on the walls of holes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01Tools for processing; Objects used during processing
    • H05K2203/0191Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06Lamination
    • H05K2203/065Binding insulating layers without adhesive, e.g. by local heating or welding, before lamination of the whole PCB
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/08Treatments involving gases
    • H05K2203/083Evaporation or sublimation of a compound, e.g. gas bubble generating agent
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14Related to the order of processing steps
    • H05K2203/1461Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/002Etching of the substrate by chemical or physical means by liquid chemical etching
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126Assembling bases
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49133Assembling to base an electrical component, e.g., capacitor, etc. with component orienting
    • Y10T29/49135Assembling to base an electrical component, e.g., capacitor, etc. with component orienting and shaping, e.g., cutting or bending, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer

Definitions

  • the present invention relates to a method for manufacturing a circuit forming substrate used for various electronic devices and a material for manufacturing the circuit forming substrate.
  • the substrate material 61 shown in FIG. 6A is a pre-predator in which a glass fiber woven fabric used for a circuit forming substrate is impregnated with a thermosetting epoxy resin or the like, and is placed in a B stage state by a method such as drying.
  • a film 62 is attached to both sides of the substrate material 61 by a laminating method using a hot roll or the like.
  • via holes 63 are formed in the substrate material 61 by a processing method such as laser.
  • a conductive paste 64 formed by kneading conductive particles such as copper powder and a thermosetting resin, a curing agent, and a solvent is filled in the via hole 63.
  • the conductive paste 64 as shown in FIG.
  • copper foil 65 is placed on both sides and heated and pressed by a hot press device (not shown), the substrate material 61 is thermally cured as shown in FIG. 6E, and the conductive paste 64 is compressed.
  • the copper foil 65 on both sides is electrically connected.
  • the epoxy resin impregnated in the substrate material 61 flows and flows out to form a flow-out portion 66.
  • an extra portion of the end is cut off to obtain a shape as shown in Fig.
  • a circuit-formed substrate on both sides as shown in FIG. 6G is obtained.
  • the electrical connection between the front and back of the circuit forming substrate may be insufficient.
  • similar defects may occur in the circuit of the surface layer and the inner layer.
  • the main cause is the occurrence of outflow particles 610 in which the conductive particles in the conductive paste 64 flow out of the via holes 63 as shown in FIG. 6E.
  • the conductive paste 64 is compressed in the vertical direction in Fig. 6E, and the conductive particles in the conductive paste come into strong contact with each other efficiently. Need to be firmly in contact with them.
  • the thermosetting resin in the substrate material 61 flows outward, as can be seen from the formation of the outflow portion 66 in the process from FIG. 6D to FIG. 6E.
  • the conductive particles in the conductive paste 64 are swept away in the lateral direction of FIG. 6E, and as a result, the conductive paste 64 cannot be efficiently compressed.
  • the electrical connection becomes unstable.
  • FIGS. 7A to 7C As shown in FIG. 7A, via holes 63 are formed in a substrate material 61 using a glass fiber woven fabric 68 using a laser. When viewed from above, the via hole 63 is formed by cutting the glass fiber woven cloth 68 as shown in FIG. 7B. Thereafter, the steps as described with reference to FIGS. 6C to 6E are performed.
  • the main factors that determine the amount of compression of the conductive paste 4 are the amount by which the substrate material 61 is compressed in the thickness direction in the hot pressing process in FIGS. 6D to 6E, and the amount of the substrate material 61 in FIG. 6D. This is the amount by which the conductive paste 64 protrudes from.
  • an element that exerts a compressive action on conductive paste 64 is required in addition to controlling the two main factors described above. It is. Disclosure of the invention
  • the resin flow in the hot pressing step is restricted. Thereby, the electrical connection by the interlayer connection part such as the conductive paste is efficiently performed.
  • a resin whose flow is controlled in the hot pressing step is used. Thereby, the electrical connection by the interlayer connection part such as the conductive paste is efficiently performed.
  • FIGS. 1A to 1G show the manufacture of a circuit forming substrate according to the first embodiment of the present invention. It is a process sectional view showing a fabrication method.
  • FIGS. 2A to 2E are process cross-sectional views illustrating a method for manufacturing a circuit-formed substrate according to the second embodiment of the present invention.
  • FIG. 3A is a schematic sectional view of a via forming step in the method for manufacturing a circuit-formed substrate according to the third embodiment of the present invention.
  • FIG. 3B is a top view of a via portion before filling with a conductive paste in the method of manufacturing a circuit-formed substrate according to the third embodiment of the present invention.
  • FIG. 3C is a top view of the via portion after filling the conductive paste in the method of manufacturing the circuit-formed substrate according to the third embodiment of the present invention.
  • 4A to 4H are process cross-sectional views illustrating a method for manufacturing a circuit-formed substrate according to the fourth embodiment of the present invention.
  • FIG. 5A is a schematic cross-sectional view of a via forming step in the method for manufacturing a circuit-formed substrate according to the fifth embodiment of the present invention.
  • FIG. 5B is a top view of a via portion before filling with a conductive paste in the method of manufacturing a circuit-formed substrate according to the fifth embodiment of the present invention.
  • FIG. 5C is a top view of the via portion after filling the conductive paste in the method of manufacturing a circuit-formed substrate according to the fifth embodiment of the present invention.
  • 6A to 6G are process cross-sectional views illustrating a method for manufacturing a circuit-formed substrate according to the related art.
  • FIG. 7A is a schematic cross-sectional view of a via formation process in a conventional method for manufacturing a circuit formation substrate.
  • FIG. 7B is a top view of the via portion before filling the conductive base in the conventional method of manufacturing a circuit-formed substrate.
  • FIG. 7C is a top view of the via portion after filling the conductive base in the conventional method of manufacturing a circuit-formed substrate.
  • FIG. 1A to 1G are process cross-sectional views showing a method for manufacturing a circuit-forming substrate and materials for manufacturing the circuit-forming substrate according to the first embodiment of the present invention.
  • a board material made of a pre-predeer with a thickness of 100 0 // m and impregnated with a thermosetting epoxy resin using a glass fiber woven fabric as a reinforcing material Attach film 2 of m.
  • the film 12 uses polyethylene terephthalate (PET). If necessary, a thermosetting resin such as an epoxy resin may be coated on the film 12.
  • a via hole 13 having a diameter of about 200 m is formed using a carbon dioxide gas laser.
  • the conductive paste 14 is filled in the via hole 13 by screen printing or the like.
  • the conductive paste 14 is obtained by kneading copper powder having a diameter of about 5 m, a thermosetting resin, and a curing agent. A solvent or the like may be added to the conductive paste 4 for the purpose of adjusting viscosity or the like.
  • FIG. 1D when the films 12 on both sides of the substrate material 11 are peeled off, the substrate material 1 1
  • the conductive base 14 protrudes from the film 12 to about the thickness of the film 12. Copper foil 15 is placed on both sides.
  • thermosetting resin in the substrate material 11 flows to form a flow-out portion 16.
  • a circuit 17 is formed by patterning the copper foil 15 by a method such as etching to obtain a double-sided circuit-formed substrate as shown in FIG. 1G.
  • the mass of the resin that flows in the hot pressing process and flows out around the substrate material 11 with respect to the mass of the substrate material 11 before hot pressing in the above process, that is, the mass of the flow-out portion 16 in FIG. 1E Is the resin flow rate.
  • the resin flow rate In order to solve the problem of insufficient electrical connection by the conductive paste 14 described in the background art, the resin flow rate must be at least 20% or less.
  • Table 1 shows examples of the experimental results by the inventors have studied the resin flow quantity summarizes the following measurement results.
  • connection resistance per one point (average value) determined from the electrical resistance of a test pattern circuit in which 500 via holes are connected in series with the copper foil on the front and back of the board
  • the sample is stored for a long period of time in a high-temperature, high-humidity environment, etc., and the reliability is evaluated by measuring the change over time in the via connection resistance.
  • the heating rate is 0.5 t / min. : More preferably.
  • the heating rate is controlled to 3 or less per minute only in the time range where the fluidity increases during the hot pressing process. During the time period, the temperature may be increased at a faster rate.
  • the uncured epoxy resin is heated and dried, and the volatile components, the amount of residual solvent, and the degree of thermal curing are controlled by the heating temperature and time to change the curing time.
  • the curing time which indicates the melting and curing characteristics of the substrate material during hot pressing, is set to 110 seconds or less.
  • the curing time is preferably 10 seconds or more in order to avoid the occurrence of the above-mentioned poor filling property. Further, from the viewpoint of the adhesion between the copper foil 15 and the substrate material 11 in FIG. 1E or the absorption of the resin amount, it is more preferable to set the time to 50 seconds or more.
  • Embodiment 1 is an example of a double-sided circuit-formed substrate, it is preferable to apply the present invention also to manufacture a multilayer circuit-formed substrate as shown in FIGS. 2A to 2E.
  • a double-sided circuit forming substrate as shown in FIG. 2A is prepared.
  • the board material 11 filled with the conductive paste 14 and the copper foil 15 are aligned and placed on the front and back of the double-sided circuit board, and heated and pressed by a heat press device or the like. .
  • the substrate material 11 is molded and cured as shown in FIG. 2C.
  • the component of the flowing substrate material 1 flows out to form a flow-out portion 26.
  • the weight of the flow-out portion 26 (the amount of resin flow) becomes 20% or less with respect to the weight of the two substrate materials 11 by the method described in the first embodiment. To do.
  • the copper foil 15 is patterned by etching or the like to form a circuit 27, and Fig. 2E Obtain a 4-layer circuit forming substrate as shown.
  • the electrical connection between the layers can be favorably formed by applying the method for producing a circuit formation substrate and the material for production of the present invention.
  • the double-sided circuit forming substrate used in the present embodiment may be the substrate described in the first embodiment, or may be a substrate in which connection between layers is formed by a normal plating method or the like. Further, a configuration in which the substrate material 11 is temporarily pressure-bonded to the double-sided circuit formation substrate in the step shown in FIG.
  • FIGS. 3A to 3C A third embodiment of the present invention will be described below with reference to FIGS. 3A to 3C.
  • a via hole 13 is formed in a pre-prepared substrate material 11 using a glass fiber woven fabric 38 by using a laser.
  • the via hole 13 is formed by cutting the glass fiber woven fabric 38 as shown in FIG. 3B.
  • a welded portion 39 as shown in FIG. 3B is formed by a specific processing method.
  • the conductive paste 14 is filled into the via hole 13 after the welded part 39 is formed and the hot pressing process is performed, as shown in Fig. 3C, around the via hole 13 of the conductive paste 14 Spread is prevented. Therefore, the electrical interlayer connection by the conductive paste 14 is good.
  • the via hole 13 is formed by drilling, the welded portion 39 is formed by transforming the resin component and the like in the substrate material 11 by frictional heat or the like at the time of application and solidifying the glass fiber fabric 3 8 Can also be realized by fixing around the via hole 13.
  • the welded portion 39 does not need to be composed only of a reinforcing material such as glass fiber, and the resin component and the like in the substrate material 11 are hardened or deteriorated by heat or the like at the time of processing, so that the subsequent hot pressing step The same effect can be obtained if the fluidity at the point is lost.
  • the glass fiber woven fabric 38 is melted or deteriorated to form the welded portion 39 mainly composed of the glass fiber woven fabric 38.
  • Table 2 shows examples of the study results of the inventor.
  • Via holes 13 were processed under various conditions using three types of laser oscillators to produce a double-sided circuit-formed substrate, and the contents described in Embodiment 1 were used. 0 Similarly, the results of comparing the via connection resistance values are summarized.
  • the via connection resistance value is related to the laser wavelength.
  • the formation of a welded portion is confirmed at an oscillation wavelength of 10.6, but no welded portion is observed when an oscillation wavelength of 9.4 m is used. .
  • Table 2
  • welds When using various lasers such as excimer lasers, YAG harmonics, carbon dioxide lasers, etc., it is possible to form welds depending on the processing conditions. Heating is preferred for forming the weld.
  • the use of a carbon dioxide laser is advantageous in terms of processing speed and cost.
  • the laser-based processing method is more preferable.
  • Embodiment 4 will be described with reference to FIGS. 4A to 4H.
  • substrate material 41 is made of polyethylene terephthalate (PET) on both sides using glass fiber woven fabric as a reinforcing material. This is a 100 m thick pre-preder to which an m film 12 is attached. If necessary, the film 12 may be coated with a thermosetting resin such as an epoxy resin.
  • PET polyethylene terephthalate
  • This substrate material 41 differs from the substrate material 11 in the first embodiment in that a large amount of volatile components remain when a pre-preda is manufactured. From the weight change before and after drying for 160 hours, the volatile content is 3%.
  • FIGS. 4B to 4D Subsequent steps shown in FIGS. 4B to 4D are the same as in the first embodiment.
  • the substrate material 41 is introduced into a vacuum drying device (not shown), and dried in a vacuum of about 133 Pa for one hour.
  • a process of introducing hot air at 50 ° C into the vacuum drying apparatus and reducing the pressure again is performed three times.
  • the thickness of the substrate material 41 is reduced, and the reduction is about 2 / m.
  • the height of the protruding portion of the conductive base 14 from the substrate material 41 of about 20 m increases by about 1 m on each of the front and back sides of the substrate material, to about 22 m. Become.
  • a circuit 17 is formed by patterning the copper foil 15 by a method such as etching to obtain a double-sided circuit forming substrate as shown in FIG. 1H.
  • the height of the projecting portion of the conductive paste 14 is increased by only 2 m before the hot pressing. To improve the electrical connection.
  • the normal hot pressing process uses a vacuum press, it is considered that most of the volatile components in the substrate material are removed during the hot pressing process.
  • the amount of the component of the substrate material flowing during the hot pressing process is relatively large, which is disadvantageous in that the conductive paste is compressed in the thickness direction of the substrate to realize electrical connection.
  • the volatile components in the substrate material 41 are removed by vacuum drying before the hot pressing step, and the flow during hot pressing is controlled.
  • the height of the conductive paste 14 projecting from the substrate material 41 is increased, and the effective compression amount is increased.
  • the conductive paste 14 can be extremely efficiently compressed in the hot pressing step, and the electrical connection between the circuits 17 on the front and back of the circuit forming substrate becomes sufficient.
  • the method described above is also suitably applied to the substrate material 21 when manufacturing the multilayer circuit forming substrate as described in the second embodiment.
  • a high-boiling solvent such as BCA (butyl carbitol acetate) is contained as a volatile component in the production process of the substrate material 41.
  • the step of reducing the thickness of the substrate material 41 has been described using the vacuum drying method, it may be performed by a normal drying method involving heating under conditions that do not cause a problem in the physical properties of the substrate material 41. .
  • the interlayer connection portion protrudes from the substrate material even when a method of selectively etching the substrate material by a dry or wet etching method using a plasma excimer laser is used.
  • the amount to do can be secured. In this case, there is also an effect that the thickness reduction and the small amount of the substrate material are stabilized. (Embodiment 5)
  • a fifth embodiment of the present invention will be described below with reference to FIGS. 5A to 5C.
  • a via hole 13 is formed in a pre-prepared substrate material 51 using a glass fiber woven fabric 38 by using a laser.
  • the substrate material 51 contains a filler 5 10 as a solid content.
  • the usual substrate material is a glass fiber woven fabric 38, which is impregnated with a liquid material called a varnish obtained by diluting a thermosetting resin with a solvent or the like, and then volatilizes volatile components such as a solvent in a drying process to cure the thermosetting resin. It is manufactured by a method that adjusts By dispersing the filler in the varnish, a substrate material 51 used in the present embodiment is manufactured.
  • a silica-based filler on silica (Si0 2) from about. 1 to 2 m in diameter.
  • a low fluidized bed 5 11 is formed around the via hole 13.
  • the processing energy is absorbed by the filler 510 during laser processing and converted into heat, and the surrounding thermosetting resin is denatured. It is formed by a phenomenon that forms a layer with the filler 510 as a core. Its formation efficiency is much higher than without the filler.
  • the low-fluidized bed 5 11 1 may contain the glass fiber woven fabric 38 as a component.
  • the via hole 13 is filled with the conductive paste 14 and the hot pressing process is performed.
  • spread forms of electrical interlayer connection is good c low flow layer 5 1 1 by c therefore conductive paste 1 4 is prevented in the via hole 1 3 surrounding to form the via hole 1 3 drilling
  • the via hole 13 is formed by using a laser, it is preferable to absorb energy in the filer 50 and convert it to heat to form the low fluidized layer 511.
  • the formation of the low fluidized bed 511 is efficient when an oscillation wavelength of 9 m or more is used by the carbon dioxide laser.
  • a material other than silica may be used as the material of the filler 510, and the same effect can be obtained by using talc, gypsum powder or the like, or metal hydroxide (such as aluminum hydroxide).
  • the substrate material is made of a woven glass fiber fabric.
  • a non-woven fabric may be used instead of the glass fiber woven fabric.
  • Organic fibers such as aramid may be used instead of glass fibers.
  • a B-stage film may be used instead of the pre-predader as the substrate material.
  • a material in which a woven fabric and a nonwoven fabric are mixed for example, a material in which a glass fiber nonwoven fabric is sandwiched between two glass fibers may be used as a reinforcing material.
  • thermosetting resin in all the embodiments of the present invention has been described as an epoxy resin, the following may be used.
  • a circuit made of a metal foil or the like temporarily fixed to a support may be used instead of the copper foil.
  • a conductive paste in which conductive particles such as copper powder, a curing agent, and a thermosetting resin are kneaded as the interlayer connection portion.
  • a variety of compositions can be used, such as a mixture of a polymer material having an appropriate viscosity that is discharged into the substrate material during heat pressing and conductive particles, or a mixture of a solvent and the like.
  • post-shaped conductive protrusions formed by plating or the like, or conductive particles having a relatively large particle size that is not pasted can be used alone as an interlayer connection part. It is. Industrial applicability
  • any one of the following configurations is adopted.
  • a physical property value for controlling the resin flow in the hot pressing step is imparted, or the thickness of the substrate material can be efficiently reduced after the filling step.
  • the configuration shall include volatile components. According to the present invention, the electrical connection can be efficiently achieved by the inter-layer connection portion such as the conductive paste.
  • a woven fabric when used as a reinforcing material for the substrate material, it has a particular effect that the connection between layers can be stabilized while taking advantage of the dimensional stability and the like of the woven fabric. This is due to the process of controlling the fluidity or locally preventing the movement of the fiber at the part where the interlayer connection is to be performed, simultaneously with the drilling, or by reducing the thickness of the substrate material. As a result of the above, the reliability of electrical connection between layers using an interlayer connection portion such as a conductive paste is improved, and a high-quality, high-density circuit board can be provided.

Abstract

A method of manufacturing a circuit-formed substrate capable of increasing the reliability of an interlayer connection on the circuit-formed substrate and a material for manufacturing a circuit-formed substrate, the method comprising the steps of A) limiting resin flow in a hot press process, B) fusing or sticking reinforcement fibers to each other, C) reducing the thickness of substrate material after a filling process, and D) forming a low fluidized-layer with fillers mixed in the substrate material, the material comprising volatile components capable of providing physical properties to control the resin fluidity in the hot press process or efficiently reducing the thickness of the substrate material after the filling process.

Description

明 細 書  Specification
回路形成基板の製造方法と回路形成基板の製造用材料 技術分野  Method for manufacturing circuit-formed substrate and material for manufacturing circuit-formed substrate
本発明は、 各種電子機器に利用される回路形成基板の製造方法お よび回路形成基板の製造用材料に関する。 背景技術  The present invention relates to a method for manufacturing a circuit forming substrate used for various electronic devices and a material for manufacturing the circuit forming substrate. Background art
近年の電子機器の小型化 · 高密度化に伴って、 電子部品を搭載す る回路形成基板も従来の片面基板から両面、多層基板の採用が進み、 より多くの回路および部品を基板上に集積可能な高密度基板が開発 されている (たとえば、 日刊工業新聞社発行の 「表面実装技術」 1 9 9 7年 1月号、 高木清著;"目覚ましいビルドアップ多層 P W Bの 開発動向")。  In recent years, with the miniaturization and high density of electronic devices, the use of single-sided and double-sided, multi-layer boards has also been increasing for circuit formation boards on which electronic components are mounted, and more circuits and components are integrated on the board. Possible high-density substrates have been developed (for example, “Surface Mount Technology” published by Nikkan Kogyo Shimbun, January 1997, Kiyoshi Takagi; “Development of remarkable build-up multilayer PWB”).
図 6 A〜図 6 Gを用いて従来技術を説明する。  The prior art will be described with reference to FIGS. 6A to 6G.
図 6 Aに示す基板材料 6 1は回路形成基板に用いられるガラス繊 維織布に熱硬化性のエポキシ樹脂等を含浸し乾燥等の方法 より B ステージ状態としたプリプレダである。 基板材料 6 1 には熱ロール 等を用いたラミネート法によりフィルム 6 2を両面に貼り付ける。 次に、 図 6 B に示すようにレーザ等の加工法により基板材料 6 1 にビア穴 6 3を形成する。 そして図 6 C に示すように銅粉等の導電 性粒子と熱硬化性樹脂、 硬化剤、 溶剤などを混練しペースト状にし た導電性ペース ト 6 4をビア穴 6 3に充填する。 その後にフィルム 2を剥離すると図 6 Dに示すような導電性ペース ト 6 4が突出した 形状になる。 その両側に銅箔 6 5を配置して熱プレス装置 (図示せ ず) によって加熱加圧すると図 6 E に示すように基板材料 6 1は熱 硬化し、 導電性ペース ト 6 4は圧縮されて表裏の銅箔 6 5が電気的 に接続される。 その際に、 基板材料 6 1に含浸したエポキシ樹脂は 流動し外側に流出し流れ出し部 6 6を形成する。 その後に端部の余 分な部分を切り落として図 6 F のような形状とし、 さらにエツチン グなどの方法で銅箔 6 5を所望のパターンに加工して回路 6 7 とし、 図 6 Gに示すような両面の回路形成基板を得る。 The substrate material 61 shown in FIG. 6A is a pre-predator in which a glass fiber woven fabric used for a circuit forming substrate is impregnated with a thermosetting epoxy resin or the like, and is placed in a B stage state by a method such as drying. A film 62 is attached to both sides of the substrate material 61 by a laminating method using a hot roll or the like. Next, as shown in FIG. 6B, via holes 63 are formed in the substrate material 61 by a processing method such as laser. Then, as shown in FIG. 6C, a conductive paste 64 formed by kneading conductive particles such as copper powder and a thermosetting resin, a curing agent, and a solvent is filled in the via hole 63. After that, when the film 2 is peeled off, the conductive paste 64 as shown in FIG. When copper foil 65 is placed on both sides and heated and pressed by a hot press device (not shown), the substrate material 61 is thermally cured as shown in FIG. 6E, and the conductive paste 64 is compressed. The copper foil 65 on both sides is electrically connected. At this time, the epoxy resin impregnated in the substrate material 61 flows and flows out to form a flow-out portion 66. After that, an extra portion of the end is cut off to obtain a shape as shown in Fig. A circuit-formed substrate on both sides as shown in FIG. 6G is obtained.
しかしながら、 上記のような製造法では、 回路形成基板の表と裏 で電気的接続は不十分なものになる場合がある。 また多層回路形成 基板を上記のような製造法で形成した場合には表層と内層の回路に ついて同様の不良が発生することがある。  However, in the above-described manufacturing method, the electrical connection between the front and back of the circuit forming substrate may be insufficient. Further, when the multilayer circuit forming substrate is formed by the above-described manufacturing method, similar defects may occur in the circuit of the surface layer and the inner layer.
その主な原因は図 6 E に示すような導電性ペース ト 6 4中の導電 性粒子がビア穴 6 3の外部に流れ出す流出粒子 6 1 0が発生するこ とである。 理想的な電気的接続の実現には、 導電性ペースト 6 4は 図 6 E の上下方向に圧縮され、 効率的に導電性ペース ト中の導電性 粒子同士が強固に接触し、銅箔 6 5 とも強固に接触する必要がある。 しかしながら、 図 6 Dから図 6 E に至る工程中で流れ出し部 6 6が 形成されることからも解るように、 基板材料 6 1中の熱硬化性樹脂 は外側に向かって流動する。 その際に、 導電性ペース ト 6 4中の導 電性粒子が図 6 E の横方向に押し流され、 結果として効率的な導電 性ペースト 6 4の圧縮が実現出来ず、 導電性ペース ト 4による電気 的接続は不安定になる。 以上の説明では、 ガラス織布と熱硬化性樹 脂を用いた基板材料の場合を述べたが、 ガラス以外の無機繊維ゃァ ラミ ド等の有機繊維、 織布以外の不織布の補強材を用いた場合でも 同様である。  The main cause is the occurrence of outflow particles 610 in which the conductive particles in the conductive paste 64 flow out of the via holes 63 as shown in FIG. 6E. In order to realize an ideal electrical connection, the conductive paste 64 is compressed in the vertical direction in Fig. 6E, and the conductive particles in the conductive paste come into strong contact with each other efficiently. Need to be firmly in contact with them. However, the thermosetting resin in the substrate material 61 flows outward, as can be seen from the formation of the outflow portion 66 in the process from FIG. 6D to FIG. 6E. At that time, the conductive particles in the conductive paste 64 are swept away in the lateral direction of FIG. 6E, and as a result, the conductive paste 64 cannot be efficiently compressed. The electrical connection becomes unstable. In the above description, the case of a substrate material using a glass woven fabric and a thermosetting resin has been described.However, organic fibers such as inorganic fibers and polyamides other than glass and reinforcing materials for nonwoven fabrics other than the woven fabric are used. It is the same even if there is.
しかし、 織布を用いた場合には特に織布中の流動抵抗が小さいた め、 上述した熱硬化性樹脂の流動は顕著になり、 導電性ペース トに よる電気的接続は困難である。 さらに、 織布を構成する繊維がずれ る現象が悪影響を及ぼしている。 図 7 A〜図 7 Cを用いてその現象 を説明する。 図 7 Aに示すようにガラス繊維織布 6 8を用いた基板 材料 6 1にレーザを用いてビア穴 6 3を形成する。 その部分は上方 より見ると図 7 B に示すようにガラス繊維織布 6 8を切断してビア 穴 6 3が加工される。 その後に図 6 C〜図 6 E を用いて説明したよ うな工程を実施する。 その後の回路形成基板のビア穴 6 3部分を観 察すると、 図 7 C に示すように熱プレス時の加圧力や含浸樹脂の流 動等によって導電性ペース ト 6 4が周囲に広がりガラス繊維織布 6 8 も当初の規則正しい配列からビア穴 6 3の外側方向に動かされて いる。 このような現象が発生すると導電性ペース ト 6 4の圧縮が非 効率になる。 こうした現象は電気的接続の抵抗値ばらつきや信頼性 の点で、 このような回路形成基板の製造における課題である。 However, when a woven fabric is used, the flow resistance of the above-mentioned thermosetting resin becomes remarkable because the flow resistance in the woven fabric is particularly small, and it is difficult to make an electrical connection by a conductive paste. Furthermore, the phenomenon that the fibers constituting the woven fabric are shifted has an adverse effect. The phenomenon will be described with reference to FIGS. 7A to 7C. As shown in FIG. 7A, via holes 63 are formed in a substrate material 61 using a glass fiber woven fabric 68 using a laser. When viewed from above, the via hole 63 is formed by cutting the glass fiber woven cloth 68 as shown in FIG. 7B. Thereafter, the steps as described with reference to FIGS. 6C to 6E are performed. Observation of the via holes 63 on the circuit-forming board thereafter revealed that, as shown in Fig. 7C, the conductive paste 64 spread around due to the pressing force during hot pressing and the flow of the impregnated resin, etc. Cloth 6 8 is also moved outward from the via hole 63 from the initial regular arrangement. When such a phenomenon occurs, the compression of the conductive paste 64 becomes inefficient. Such phenomena are problems in the manufacture of such a circuit-formed substrate in terms of variation in electrical connection resistance and reliability.
近年、 回路形成基板として薄いものが要望されているので、 ガラ ス繊維織布にも薄い材料が多用される。 しかしそのような材料では ガラス繊維の充填度が低く、 繊維間の隙間が比較的大きいので上記 のような問題が顕著になる。 特にガラス繊維織布の厚みが 1 0 0 / m以下の場合に上記した現象が重大な問題となる。  In recent years, since thin substrates have been demanded as circuit forming substrates, thin materials are often used for glass fiber woven fabrics. However, in such a material, the degree of filling of the glass fiber is low, and the gap between the fibers is relatively large. In particular, when the thickness of the glass fiber woven fabric is 100 / m or less, the above phenomenon becomes a serious problem.
また、 導電性ペース ト 4の圧縮量を決める主要因は、 図 6 Dから 図 6 E における熱プレス工程で基板材料 6 1が厚み方向に圧縮され る量と、 図 6 Dで基板材料 6 1から導電性ペース ト 6 4が突出して いる量である。 高密度回路形成基板ではビア穴 6 3を通じて層間の 接続を行う箇所が膨大な点数であるため、 上記した 2つの主要因を 制御する以外に導電性ペース ト 6 4に圧縮作用を与える要素が必要 である。 発明の開示  The main factors that determine the amount of compression of the conductive paste 4 are the amount by which the substrate material 61 is compressed in the thickness direction in the hot pressing process in FIGS. 6D to 6E, and the amount of the substrate material 61 in FIG. 6D. This is the amount by which the conductive paste 64 protrudes from. In a high-density circuit board, since the number of points for connecting layers between via holes 63 is enormous, an element that exerts a compressive action on conductive paste 64 is required in addition to controlling the two main factors described above. It is. Disclosure of the invention
本発明の回路形成基板の製造方法においては、 熱プレス工程での 樹脂流動を制限する。 これにより、 導電性ペース ト等の層間接続部 による電気的接続を効率的に行う。  In the method for manufacturing a circuit-formed substrate according to the present invention, the resin flow in the hot pressing step is restricted. Thereby, the electrical connection by the interlayer connection part such as the conductive paste is efficiently performed.
また、 本発明の回路形成基板の製造用材料においては、 熱プレス 工程での流動を制御した樹脂を用いる。 これにより、 導電性ペース ト等の層間接続部による電気的接続を効率的に行う。  Further, in the material for manufacturing a circuit forming substrate of the present invention, a resin whose flow is controlled in the hot pressing step is used. Thereby, the electrical connection by the interlayer connection part such as the conductive paste is efficiently performed.
以上の結果として、 導電性ペースト等を用いた層間の電気的接続 の信頼性が大幅に向上し、 高密度で品質の優れた回路形成基板を提 供できる。 図面の簡単な説明  As a result, the reliability of electrical connection between layers using a conductive paste or the like is greatly improved, and a high-density, high-quality circuit-forming substrate can be provided. BRIEF DESCRIPTION OF THE FIGURES
図 1 A〜図 1 G は本発明の第 1の実施の形態の回路形成基板の製 造方法を示す工程断面図である。 FIGS. 1A to 1G show the manufacture of a circuit forming substrate according to the first embodiment of the present invention. It is a process sectional view showing a fabrication method.
図 2 A〜図 2 E は本発明の第 2の実施の形態の回路形成基板の製 造方法を示す工程断面図である。  2A to 2E are process cross-sectional views illustrating a method for manufacturing a circuit-formed substrate according to the second embodiment of the present invention.
図 3 Aは本発明の第 3の実施の形態の回路形成基板の製造方法に おけるビア形成工程の断面模式図である。  FIG. 3A is a schematic sectional view of a via forming step in the method for manufacturing a circuit-formed substrate according to the third embodiment of the present invention.
図 3 Bは本発明の第 3の実施の形態の回路形成基板の製造方法に おける導電性ペースト充填前のビア部上面図である。  FIG. 3B is a top view of a via portion before filling with a conductive paste in the method of manufacturing a circuit-formed substrate according to the third embodiment of the present invention.
図 3 C は本発明の第 3の実施の形態の回路形成基板の製造方法に おける導電性ペース ト充填後のビア部上面図である。  FIG. 3C is a top view of the via portion after filling the conductive paste in the method of manufacturing the circuit-formed substrate according to the third embodiment of the present invention.
図 4 A〜図 4 H は本発明の第 4の実施の形態の回路形成基板の製 造方法を示す工程断面図である。  4A to 4H are process cross-sectional views illustrating a method for manufacturing a circuit-formed substrate according to the fourth embodiment of the present invention.
図 5 Aは本発明の第 5の実施の形態の回路形成基板の製造方法に おけるビア形成工程の断面模式図である。  FIG. 5A is a schematic cross-sectional view of a via forming step in the method for manufacturing a circuit-formed substrate according to the fifth embodiment of the present invention.
図 5 B は本発明の第 5の実施の形態の回路形成基板の製造方法に おける導電性ペースト充填前のビア部上面図である。  FIG. 5B is a top view of a via portion before filling with a conductive paste in the method of manufacturing a circuit-formed substrate according to the fifth embodiment of the present invention.
図 5 C は本発明の第 5の実施の形態の回路形成基板の製造方法に おける導電性ペースト充填後のビア部上面図である。  FIG. 5C is a top view of the via portion after filling the conductive paste in the method of manufacturing a circuit-formed substrate according to the fifth embodiment of the present invention.
図 6 A〜図 6 G は従来技術における回路形成基板の製造方法を示 す工程断面図である。  6A to 6G are process cross-sectional views illustrating a method for manufacturing a circuit-formed substrate according to the related art.
図 7 Aは従来技術の回路形成基板の製造方法におけるビア形成ェ 程の断面模式図である。  FIG. 7A is a schematic cross-sectional view of a via formation process in a conventional method for manufacturing a circuit formation substrate.
図 7 Bは従来技術の回路形成基板の製造方法における導電性べ一 スト充填前のビア部上面図である。  FIG. 7B is a top view of the via portion before filling the conductive base in the conventional method of manufacturing a circuit-formed substrate.
図 7 C は従来技術の回路形成基板の製造方法における導電性べ一 ス 卜充填後のビア部上面図である。 発明を実施するための最良の形態  FIG. 7C is a top view of the via portion after filling the conductive base in the conventional method of manufacturing a circuit-formed substrate. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 図面を参照しながら本発明の実施の形態を説明する。 なお、 同様の構成をなすものには同じ符号を付け、詳細な説明は省略する。  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The components having the same configuration are denoted by the same reference numerals, and the detailed description is omitted.
(実施の形態 1 ) 図 1 A〜図 1 Gは本発明の第 1の実施の形態における回路形成基 板の製造方法および回路形成基板の製造用材料を示す工程断面図で ある。 (Embodiment 1) 1A to 1G are process cross-sectional views showing a method for manufacturing a circuit-forming substrate and materials for manufacturing the circuit-forming substrate according to the first embodiment of the present invention.
図 1 Aに示すようにまず、 ガラス繊維織布を補強材とし、 熱硬化 性のエポキシ樹脂を含浸した厚み 1 0 0 // mのプリプレダからなる 基板材料 1 1の両面に厚み 2 0 // mのフィルム 2を貼り合わせる。 フィルム 1 2にはポリエチレンテレフ夕レート (P E T ) を用いる。 必要に応じてフィルム 1 2にはエポキシ樹脂等の熱硬化性樹脂をコ —ティ ングしてもよい。  As shown in Fig. 1A, first, a board material made of a pre-predeer with a thickness of 100 0 // m and impregnated with a thermosetting epoxy resin using a glass fiber woven fabric as a reinforcing material Attach film 2 of m. The film 12 uses polyethylene terephthalate (PET). If necessary, a thermosetting resin such as an epoxy resin may be coated on the film 12.
その後に、 図 1 B に示すように炭酸ガスレーザを用いて直径約 2 0 0 mのビア穴 1 3を加工する。  Thereafter, as shown in FIG. 1B, a via hole 13 having a diameter of about 200 m is formed using a carbon dioxide gas laser.
その後に、 図 1 C に示すように導電性ペース ト 1 4をスクリーン 印刷等の方法でビア穴 1 3に充填する。 導電性ペース ト 1 4は約 5 m径の銅粉と熱硬化性樹脂と硬化剤とを混練したものである。 粘 度調整等の目的で導電性ペース ト 4には溶剤などを添加してもよい 次に、 図 1 Dに示すように基板材料 1 1の両面のフィルム 1 2を 剥離すると、 基板材料 1 1からフィルム 1 2の厚み程度に導電性べ 一スト 1 4が突出する。 その両面に銅箔 1 5を配置する。  Thereafter, as shown in FIG. 1C, the conductive paste 14 is filled in the via hole 13 by screen printing or the like. The conductive paste 14 is obtained by kneading copper powder having a diameter of about 5 m, a thermosetting resin, and a curing agent. A solvent or the like may be added to the conductive paste 4 for the purpose of adjusting viscosity or the like. Next, as shown in FIG. 1D, when the films 12 on both sides of the substrate material 11 are peeled off, the substrate material 1 1 The conductive base 14 protrudes from the film 12 to about the thickness of the film 12. Copper foil 15 is placed on both sides.
次に、 図中上下方向に加熱加圧する熱プレス工程を実施すると図 1 E に示すような形状になる。 その際に基板材料 1 1 中の熱硬化性 樹脂は流動し流れ出し部 1 6を形成する。  Next, when a hot press step of heating and pressing in the vertical direction in the figure is performed, the shape becomes as shown in FIG. 1E. At that time, the thermosetting resin in the substrate material 11 flows to form a flow-out portion 16.
次に、 図 1 F に示すように基板材料 1 1の周辺部を所望のサイズ に切断する。 銅箔 1 5をエッチング等の方法でパターン形成して回 路 1 7を形成し、 図 1 Gに示すような両面回路形成基板を得る。  Next, as shown in FIG. 1F, the peripheral portion of the substrate material 11 is cut into a desired size. A circuit 17 is formed by patterning the copper foil 15 by a method such as etching to obtain a double-sided circuit-formed substrate as shown in FIG. 1G.
以上のような工程にて熱プレス前の基板材料 1 1の質量に対して 熱プレス工程で流動し基板材料 1 1の周辺に流れ出した樹脂の質量、 すなわち図 1 Eの流れ出し部 1 6の質量の割合を樹脂流れ量とする。 背景技術で述べた、 導電性ペース ト 1 4による電気的接続が不十分 となる課題を解決するためには、 榭脂流れ量は少なく とも 2 0 %以 下でなければならない。 表 1 に樹脂流れ量について発明者が検討した実験結果の例を示す t 表 1 には以下の測定結果をまとめている。 The mass of the resin that flows in the hot pressing process and flows out around the substrate material 11 with respect to the mass of the substrate material 11 before hot pressing in the above process, that is, the mass of the flow-out portion 16 in FIG. 1E Is the resin flow rate. In order to solve the problem of insufficient electrical connection by the conductive paste 14 described in the background art, the resin flow rate must be at least 20% or less. The t Table 1 Table 1 shows examples of the experimental results by the inventors have studied the resin flow quantity summarizes the following measurement results.
1 ) 熱プレス工程前後の基板材料厚み  1) Substrate material thickness before and after hot pressing
2 ) 熱プレス工程で周辺部に発生した流れ出し部の重量と熱プレ ス工程前の基板材料重量より算出した樹脂流れ量  2) The amount of resin flow calculated from the weight of the flow-out part generated in the peripheral part in the heat press process and the weight of the substrate material before the heat press process
3 ) 5 0 0個のビア穴が基板表裏の銅箔により直列回路になるよ うなテス トパターン回路の電気抵抗値より求めた 1 力所あた りのビア接続抵抗値 (平均値)  3) Via connection resistance per one point (average value) determined from the electrical resistance of a test pattern circuit in which 500 via holes are connected in series with the copper foil on the front and back of the board
実験番号 1 のサンプルでは、 樹脂流れ量が 2 2 . 8 %となり、 ビ ァの接続抵抗は数 Ωから数百 Ωにばらつき、 電気的接続の無いビア も存在する。  In the sample of Experiment No. 1, the resin flow rate was 22.8%, the connection resistance of vias varied from several Ω to several hundred Ω, and some vias had no electrical connection.
また、 実験番号 1のサンプルについてビア部の断面を観察すると 導電性ペース ト 4中の導電粒子が流出している。  When the cross section of the via portion was observed for the sample of Experiment No. 1, the conductive particles in the conductive paste 4 were flowing out.
しかし、 樹脂流れ量を小さくするように熱プレスの条件等を検討 した実験番号 2から 7のサンプルではビア接続抵抗値は低下し、 2 0 %以下の樹脂流れ量に制御することで実用的なビア接続抵抗値が 得られる。  However, in the samples of Experiment Nos. 2 to 7 where the hot press conditions were examined to reduce the resin flow, the via connection resistance decreased, and practical control was achieved by controlling the resin flow to 20% or less. The via connection resistance is obtained.
また、 サンプルを高温高湿中等に長期間保存してビア接続抵抗の 経時変化を測定する等の信頼性評価でも 2 0 %以下の樹脂流れ量の 場合は良好な特性を示す。  In addition, the sample is stored for a long period of time in a high-temperature, high-humidity environment, etc., and the reliability is evaluated by measuring the change over time in the via connection resistance.
また、 表 1の結果から明らかなように 1 0 %以下の樹脂流れ量が 初期のビア接続抵抗値が得られる。 この場合、 信頼性についてもよ り良好な結果が得られる。  Also, as is clear from the results in Table 1, an initial via connection resistance value can be obtained when the resin flow rate is 10% or less. In this case, better results can be obtained for reliability.
電気的接続をより良好にするには樹脂流れ量をより低く抑えるこ とが有効である一方、 実験番号 7の結果からもわかるように、 熱プ レス工程で基板材料 1 を良好に成型するには 1 %以上の樹脂流れ量 が必要である。 表 1において埋まり性不良と記載しているのは、 以 下のような現象である。 熱プレス工程後の実験番号 7の基板には白 く見える部分があり、 拡大すると気泡や基板材料表面が凹凸状にな つている箇所が観察される。 これは樹脂の流動が少ないために、 内 層回路の凹凸を埋められずに気泡や凹凸が生じるもので、 プリ ント 配線板等の製造における白化現象と呼ばれる不良モードである。 白 化が発生した場合、 銅箔の引き剥がし強度や半田耐熱性等の特性が 低下する。 In order to improve the electrical connection, it is effective to reduce the resin flow rate.On the other hand, as can be seen from the results of Experiment No. 7, it is necessary to form the substrate material 1 well in the heat press process. Requires a resin flow of at least 1%. The following phenomena are described as poor filling in Table 1. The substrate of Experiment No. 7 after the hot pressing process has a part that looks white, and when it is enlarged, bubbles and parts where the surface of the substrate material is uneven are observed. This is because the flow of the resin is small. This is a failure mode called whitening in the manufacture of printed wiring boards and the like, in which bubbles and unevenness are generated without filling the unevenness of the layer circuit. When whitening occurs, the properties such as the peel strength of the copper foil and the soldering heat resistance are reduced.
Figure imgf000009_0001
Figure imgf000009_0001
上記した樹脂流れ量 2 0 %以下を達成する手段として、 熱プレス 工程での温度プロファイルにおいて、 昇温速度を毎分 3 °C以下に制 御することが有効である。  As a means for achieving the above-mentioned resin flow rate of 20% or less, it is effective to control the rate of temperature rise to 3 ° C / min or less in the temperature profile in the hot pressing step.
しかし、 熱プレス工程の所要時間が非常に長時間になる、 あるい は昇温速度を下げすぎて樹脂の成型性に悪影響を及ぼすことも考慮 して、 昇温速度は毎分 0 . 5 t:以上にすることが好ましい。  However, taking into account that the time required for the hot pressing process is extremely long, or that the heating rate is too low, which adversely affects the moldability of the resin, the heating rate is 0.5 t / min. : More preferably.
また、 基板材料 1 1 に含まれる樹脂等の加温時における粘度変化 を考慮して、 熱プレス工程中で流動性が高まる範囲の時間帯のみ昇 温速度を毎分 3 以下に制御し他の時間帯はそれより速い速度で昇 温してもよい。  Also, taking into account the viscosity change during heating of the resin etc. contained in the substrate material 11, the heating rate is controlled to 3 or less per minute only in the time range where the fluidity increases during the hot pressing process. During the time period, the temperature may be increased at a faster rate.
また、 基板材料 1 1の特性を制御して上記の効果を得ることも可 能である。 そのためには、 未硬化のエポキシ樹脂を加熱乾燥し、 揮 発成分、 残留溶剤量、 熱硬化の進行度を加熱温度、 時間によってコ ントロールし、 硬化時間を変化させる。 このような方法により、 熱 プレス時の基板材料の溶融や硬化の特性を表す硬化時間を 1 1 0秒 以下とする。 このような樹脂材料を含む基板材料を用いることによ り樹脂流れ量を 2 0 %以下とし、 導電性ペース トによる層間の電気 的接続を良好なものとできる。 It is also possible to control the characteristics of the substrate material 11 to obtain the above effects. To do this, the uncured epoxy resin is heated and dried, and the volatile components, the amount of residual solvent, and the degree of thermal curing are controlled by the heating temperature and time to change the curing time. With this method, the curing time, which indicates the melting and curing characteristics of the substrate material during hot pressing, is set to 110 seconds or less. By using a substrate material containing such a resin material, the flow rate of the resin is reduced to 20% or less, and the electric current between the layers by the conductive paste is reduced. Good connection can be achieved.
なお前述した埋まり性不良の発生を避けるため、 硬化時間は 1 0 秒以上とすることが好ましい。 さらに図 1 Eにおける銅箔 1 5と基 板材料 1 1 との接着性、 あるいは樹脂量のバラツキを吸収する等の 観点から、 5 0秒以上とすることがより好ましい。  The curing time is preferably 10 seconds or more in order to avoid the occurrence of the above-mentioned poor filling property. Further, from the viewpoint of the adhesion between the copper foil 15 and the substrate material 11 in FIG. 1E or the absorption of the resin amount, it is more preferable to set the time to 50 seconds or more.
(実施の形態 2 ) (Embodiment 2)
実施の形態 1は両面回路形成基板の例であつたが、 図 2 A〜図 2 Eに示すように多層回路形成基板を製造する際にも本発明を適用す ると好適である。  Although Embodiment 1 is an example of a double-sided circuit-formed substrate, it is preferable to apply the present invention also to manufacture a multilayer circuit-formed substrate as shown in FIGS. 2A to 2E.
まず、 図 2 Aに示すような両面回路形成基板を用意する。 次に図 2 B に示すように導電性ペースト 1 4を充填した基板材料 1 1 と銅 箔 1 5を両面回路形成基板の表裏に位置合わせして配置し、 熱プレ ス装置等で加熱加圧する。 これにより図 2 C のように基板材料 1 1 を成型、 硬化させる。 その際、 流動した基板材料 1の成分が流れ出 し部 2 6を形成する。  First, a double-sided circuit forming substrate as shown in FIG. 2A is prepared. Next, as shown in Fig. 2B, the board material 11 filled with the conductive paste 14 and the copper foil 15 are aligned and placed on the front and back of the double-sided circuit board, and heated and pressed by a heat press device or the like. . Thus, the substrate material 11 is molded and cured as shown in FIG. 2C. At that time, the component of the flowing substrate material 1 flows out to form a flow-out portion 26.
このような工程において、 実施の形態 1で説明したような手法に より、 2枚の基板材料 1 1 の重量に対して流れ出し部 2 6の重量(榭 脂流れ量) が 2 0 %以下になるようにする。  In such a process, the weight of the flow-out portion 26 (the amount of resin flow) becomes 20% or less with respect to the weight of the two substrate materials 11 by the method described in the first embodiment. To do.
次に、 周辺の余分な部分を切断して図 2 Dのような形状を得た後 に、 銅箔 1 5をエッチング等の方法でパターン形成して回路 2 7を 形成し、 図 2 Eに示すような 4層回路形成基板を得る。  Next, after cutting off the extraneous part in the periphery to obtain a shape as shown in Fig. 2D, the copper foil 15 is patterned by etching or the like to form a circuit 27, and Fig. 2E Obtain a 4-layer circuit forming substrate as shown.
このような多層回路形成基板の製造においても、 本発明の回路形 成基板の製造方法および製造用材料を適用することで、 層間の電気 的接続が良好に形成できる。  Even in the production of such a multilayer circuit formation substrate, the electrical connection between the layers can be favorably formed by applying the method for producing a circuit formation substrate and the material for production of the present invention.
なお、 多層回路形成基板を製造する際の内層回路形成基板の回路 凹凸を埋め込むためには 1 %以上の樹脂流れ量が必要である。 また 基板材料 1 1に含まれる樹脂の硬化時間の制御により樹脂流れ量を 2 0 %以下とする場合には、 内層回路の埋め込み性を考慮すると、 硬化時間は 5 0秒以上 1 1 0秒以下とすることが好ましい。 なお、 本実施の形態で用いた両面回路形成基板は実施の形態 1で 説明したものでも、 通常のめっき法等で層間の接続を形成した基板 でもよい。 また図 2 B に示す工程で両面回路形成基板に基板材料 1 1が仮圧着されたような構成にしてもよい。 It should be noted that a resin flow rate of 1% or more is required to fill in the circuit unevenness of the inner layer circuit forming substrate when manufacturing the multilayer circuit forming substrate. When the resin flow rate is controlled to 20% or less by controlling the curing time of the resin contained in the substrate material 11, the curing time is 50 seconds or more and 110 seconds or less in consideration of the embedding property of the inner layer circuit. It is preferable that The double-sided circuit forming substrate used in the present embodiment may be the substrate described in the first embodiment, or may be a substrate in which connection between layers is formed by a normal plating method or the like. Further, a configuration in which the substrate material 11 is temporarily pressure-bonded to the double-sided circuit formation substrate in the step shown in FIG.
(実施の形態 3 ) (Embodiment 3)
本発明の第 3の実施の形態について図 3 A〜図 3 Cを用いて以下 に説明する。  A third embodiment of the present invention will be described below with reference to FIGS. 3A to 3C.
図 3 Aに示すようにガラス繊維織布 3 8を用いたプリプレダ状態 の基板材料 1 1 にレーザを用いてビア穴 1 3を形成する。  As shown in FIG. 3A, a via hole 13 is formed in a pre-prepared substrate material 11 using a glass fiber woven fabric 38 by using a laser.
その部分は上方より見ると図 3 B に示すようにガラス繊維織布 3 8を切断してビア穴 1 3が加工される。 この際、 特定の加工法によ り図 3 Bに示すような溶着部 3 9が形成される。  When viewed from above, the via hole 13 is formed by cutting the glass fiber woven fabric 38 as shown in FIG. 3B. At this time, a welded portion 39 as shown in FIG. 3B is formed by a specific processing method.
溶着部 3 9が形成された後にビア穴 1 3に導電性ペースト 1 4を 充填し、 熱プレス工程を実施する場合は、 図 3 C に示すように導電 性ペースト 1 4のビア穴 1 3周囲への広がりは防止されている。 し たがって導電性ペース ト 1 4による電気的層間接続は良好である。 溶着部 3 9の形成はビア穴 1 3をドリル加工で形成する場合に加 ェ時の摩擦熱等で基板材料 1 1中の樹脂成分等を変質させて固形化 し、 ガラス繊維織布 3 8をビア穴 1 3の周辺で固定することでも実 現可能である。 このように溶着部 3 9はガラス繊維等の補強材のみ で構成される必要は無く、 基板材料 1 1中の樹脂成分等が加工時の 熱等により硬化あるいは変質して、 後の熱プレス工程での流動性が 無くなれば同様の効果が得られる。 しかしレーザを用いてビア穴 1 3を形成する際にガラス繊維織布 3 8を溶融あるいは変質させてガ ラス繊維織布 3 8を主体とする溶着部 3 9を形成することが好まし い。  When the conductive paste 14 is filled into the via hole 13 after the welded part 39 is formed and the hot pressing process is performed, as shown in Fig. 3C, around the via hole 13 of the conductive paste 14 Spread is prevented. Therefore, the electrical interlayer connection by the conductive paste 14 is good. When the via hole 13 is formed by drilling, the welded portion 39 is formed by transforming the resin component and the like in the substrate material 11 by frictional heat or the like at the time of application and solidifying the glass fiber fabric 3 8 Can also be realized by fixing around the via hole 13. As described above, the welded portion 39 does not need to be composed only of a reinforcing material such as glass fiber, and the resin component and the like in the substrate material 11 are hardened or deteriorated by heat or the like at the time of processing, so that the subsequent hot pressing step The same effect can be obtained if the fluidity at the point is lost. However, when forming the via holes 13 by using a laser, it is preferable that the glass fiber woven fabric 38 is melted or deteriorated to form the welded portion 39 mainly composed of the glass fiber woven fabric 38.
表 2に発明者の検討結果の例を示す。  Table 2 shows examples of the study results of the inventor.
3種類のレーザ発振機を用いて種々の条件でビア穴 1 3の加工を 行い両面回路形成基板を作製して、 実施の形態 1で説明した内容と 0 同じく ビア接続抵抗値を比較した結果をまとめている。 Via holes 13 were processed under various conditions using three types of laser oscillators to produce a double-sided circuit-formed substrate, and the contents described in Embodiment 1 were used. 0 Similarly, the results of comparing the via connection resistance values are summarized.
この結果からもわかるようにビア接続抵抗値はレーザの波長に関 連している。 ビア穴 1 3を加工した基板材料を詳細に観察すると 1 0 . 6 の発振波長では溶着部の形成が確認されるが、 9 . 4 mの発振波長を用いた場合には溶着部は確認されない。 表 2  As can be seen from these results, the via connection resistance value is related to the laser wavelength. When the substrate material processed via holes 13 is observed in detail, the formation of a welded portion is confirmed at an oscillation wavelength of 10.6, but no welded portion is observed when an oscillation wavelength of 9.4 m is used. . Table 2
Figure imgf000012_0001
エキシマレーザ、 Y A G高調波、 炭酸ガスレーザ等の各種のレー ザを用いる場合、加工条件によっては溶着部の形成が可能であるが、 エキシマレ一ザ等の加熱を伴わないアブレーシヨ ン加工よりも炭酸 ガスレーザの加熱加工が溶着部の形成に好ましい。
Figure imgf000012_0001
When using various lasers such as excimer lasers, YAG harmonics, carbon dioxide lasers, etc., it is possible to form welds depending on the processing conditions. Heating is preferred for forming the weld.
さらに、 上記したように 1 0 / m以上の波長を持つレーザを用い ることが溶着部 3 9の形成に効率的である。 実用的にも炭酸ガスレ 一ザの使用が加工スピード、 コス トの面から有利である。 また A) 加工効率、 発振効率、 B ) 発生したレーザビームに複数の発振波長 が含まれること、 C ) 微細加工への適用つまり光学系による集光性 等の観点から 1 0〜 1 l i mの範囲のレーザを主体とする加工法が より好ましい。  Further, as described above, using a laser having a wavelength of 10 / m or more is effective for forming the welded portion 39. Practically, the use of a carbon dioxide laser is advantageous in terms of processing speed and cost. In addition, A) the processing efficiency, oscillation efficiency, B) the generated laser beam contains multiple oscillation wavelengths, and C) the range of 10 to 1 lim from the viewpoint of application to micromachining, that is, the condensing property of the optical system. The laser-based processing method is more preferable.
(実施の形態 4 ) (Embodiment 4)
図 4 A〜図 4 Hを参照しながら実施の形態 4を説明する。  Embodiment 4 will be described with reference to FIGS. 4A to 4H.
図 4 Aに示すように基板材料 4 1 はガラス繊維織布を補強材とし て両面にポリエチレンテレフタレー ト (P E T) からなる厚み 2 0 mのフィルム 1 2を貼り合わせた厚み 1 0 0 mのプリプレダで ある。 必要に応じてフィルム 1 2にはエポキシ樹脂等の熱硬化性樹 脂をコーティ ングしても良い。 この基板材料 4 1は実施の形態 1に おける基板材料 1 1 と異なり、 プリプレダを製造する際に残留する 揮発成分を多く残している。 1 6 0 1時間の乾燥前後の重量変化 から、 揮発分は 3 %である。 As shown in Fig. 4A, substrate material 41 is made of polyethylene terephthalate (PET) on both sides using glass fiber woven fabric as a reinforcing material. This is a 100 m thick pre-preder to which an m film 12 is attached. If necessary, the film 12 may be coated with a thermosetting resin such as an epoxy resin. This substrate material 41 differs from the substrate material 11 in the first embodiment in that a large amount of volatile components remain when a pre-preda is manufactured. From the weight change before and after drying for 160 hours, the volatile content is 3%.
その後に続く、 図 4 B〜図 4 Dに示す工程は実施の形態 1 と同様 である。  Subsequent steps shown in FIGS. 4B to 4D are the same as in the first embodiment.
次に、 真空乾燥装置 (図示せず) に基板材料 4 1 を導入し、 1 3 3 P a程度の真空中で 1時間乾燥させる。 乾燥中は基板材料 4 1の 温度低下を防止するために 5 0 °Cの温風を真空乾燥装置内に導入し 再度減圧する工程を 3回実施する。 この工程で図 4 E に示すように 基板材料 4 1 は厚みが減少し、 その減少量は約 2 / mである。 その 結果として乾燥前には約 2 0 mの基板材料 4 1からの導電性べ一 ス ト 1 4の突出部の高さは基板材料の表裏で各々 1 m程度増加し、 2 2 m程度となる。  Next, the substrate material 41 is introduced into a vacuum drying device (not shown), and dried in a vacuum of about 133 Pa for one hour. During drying, in order to prevent the temperature of the substrate material 41 from lowering, a process of introducing hot air at 50 ° C into the vacuum drying apparatus and reducing the pressure again is performed three times. In this step, as shown in FIG. 4E, the thickness of the substrate material 41 is reduced, and the reduction is about 2 / m. As a result, before drying, the height of the protruding portion of the conductive base 14 from the substrate material 41 of about 20 m increases by about 1 m on each of the front and back sides of the substrate material, to about 22 m. Become.
次に図 4 F に示すように基板材料 4 1 の両面に銅箔 1 5を配置し、 図中上下方向に加熱加圧する熱プレス工程を実施し、 周辺部を切断 すると図 4 Gに示すような形状になる。  Next, as shown in Fig. 4F, copper foils 15 are placed on both sides of the substrate material 41, and a heat pressing step of heating and pressing vertically in the figure is performed. Shape.
さらに銅箔 1 5をエッチング等の方法でパターン形成して回路 1 7を形成し、 図 1 Hに示すような両面回路形成基板を得る。  Further, a circuit 17 is formed by patterning the copper foil 15 by a method such as etching to obtain a double-sided circuit forming substrate as shown in FIG. 1H.
以上のような工程にて回路形成基板を製造した場合に、 わずか 2 mであるが熱プレス前に導電性ペース ト 1 4の突出部高さを増加 させておく ことが、 導電性ペースによる層間の電気的接続を良好に する。  When a circuit-formed substrate is manufactured by the above process, the height of the projecting portion of the conductive paste 14 is increased by only 2 m before the hot pressing. To improve the electrical connection.
通常の熱プレス工程は真空プレスを用いるので基板材料中の揮発 分の多くは熱プレス工程中に取り除かれると考えられる。 そのよう な製造法では熱プレス工程中に基板材料の成分が流動する量が比較 的大きく、 導電性ペーストを基板厚み方向に圧縮して電気的接続を 発現させるには不利となる。 本実施の形態では熱プレス工程前に基板材料 4 1中の揮発成分を 真空乾燥により取り除き、 熱プレス時の流動を制御する。 また揮発 成分の除去により導電性ペース ト 1 4の基板材料 4 1からの突出高 さを増加させ、 実効的な圧縮量を増加させている。 これらにより、 導電性ペースト 1 4の熱プレス工程での圧縮が極めて効率的となり 回路形成基板表裏の回路 1 7の電気的接続が十分なものとなる。 以上述べた手法は、 実施の形態 2で説明したような多層回路形成 基板を製造する際の基板材料 2 1に適用しても好適である。 Since the normal hot pressing process uses a vacuum press, it is considered that most of the volatile components in the substrate material are removed during the hot pressing process. In such a manufacturing method, the amount of the component of the substrate material flowing during the hot pressing process is relatively large, which is disadvantageous in that the conductive paste is compressed in the thickness direction of the substrate to realize electrical connection. In the present embodiment, the volatile components in the substrate material 41 are removed by vacuum drying before the hot pressing step, and the flow during hot pressing is controlled. In addition, by removing the volatile components, the height of the conductive paste 14 projecting from the substrate material 41 is increased, and the effective compression amount is increased. As a result, the conductive paste 14 can be extremely efficiently compressed in the hot pressing step, and the electrical connection between the circuits 17 on the front and back of the circuit forming substrate becomes sufficient. The method described above is also suitably applied to the substrate material 21 when manufacturing the multilayer circuit forming substrate as described in the second embodiment.
本実施の形態の効果は実験の結果から、 基板材料 4 1の揮発分が 0 . 5 %以上で有効性が顕著であるが、 揮発分が多すぎると基板材 料 4 1の保存性が低下する場合もあり、 5 %以下にとどめることが 好ましい。  Experimental results show that the effect of the present embodiment is remarkable when the volatile content of the substrate material 41 is 0.5% or more, but the storage stability of the substrate material 41 decreases when the volatile content is too large. In some cases, it is preferable to keep the content to 5% or less.
また、 揮発分としては B C A (プチルカルビトールアセテート) 等の高沸点の溶剤を基板材料 4 1の製作過程で含有させておく こと が好ましい。  It is preferable that a high-boiling solvent such as BCA (butyl carbitol acetate) is contained as a volatile component in the production process of the substrate material 41.
なお、 基板材料 4 1の厚みを減少させる工程は真空乾燥法を用い て説明したが、 基板材料 4 1の物性に問題が発生しない条件での、 加熱を伴う通常の乾燥法で行ってもよい。  Although the step of reducing the thickness of the substrate material 41 has been described using the vacuum drying method, it may be performed by a normal drying method involving heating under conditions that do not cause a problem in the physical properties of the substrate material 41. .
また、 基板材料の厚みを減少させる工程において、 プラズマゃェ キシマレ一ザを用いた乾式あるいは湿式のエッチング法により選択 的に基板材料をエッチングする方法を用いても層間接続部が基板材 料より突出する量を確保できる。 またこの場合、 基板材料の厚み減 少量が安定する等の効果もある。 (実施の形態 5 )  Also, in the process of reducing the thickness of the substrate material, the interlayer connection portion protrudes from the substrate material even when a method of selectively etching the substrate material by a dry or wet etching method using a plasma excimer laser is used. The amount to do can be secured. In this case, there is also an effect that the thickness reduction and the small amount of the substrate material are stabilized. (Embodiment 5)
本発明の第 5の実施の形態について図 5 A〜図 5 C を用いて以下 に説明する。  A fifth embodiment of the present invention will be described below with reference to FIGS. 5A to 5C.
図 5 Aに示すようにガラス繊維織布 3 8を用いたプリプレダ状態 の基板材料 5 1 にレーザを用いてビア穴 1 3を形成する。 基板材料 5 1 には固形分としてのフィラー 5 1 0が含まれている。 通常の基板材料はガラス繊維織布 3 8に熱硬化性樹脂を溶剤等で 希釈したワニスと呼ばれる液状材料を含浸した後に乾燥工程にて溶 剤等の揮発分を揮発させ熱硬化樹脂の硬化度を調整する方法で製造 される。 このワニス中にフィ ラーを分散させておく ことで本実施の 形態で使用するような基板材料 5 1 を製造する。 本実施の形態では 直径約 1〜 2 mのシリカ ( Si02) を用いたシリカ系フィ ラーを用 いる。 As shown in FIG. 5A, a via hole 13 is formed in a pre-prepared substrate material 51 using a glass fiber woven fabric 38 by using a laser. The substrate material 51 contains a filler 5 10 as a solid content. The usual substrate material is a glass fiber woven fabric 38, which is impregnated with a liquid material called a varnish obtained by diluting a thermosetting resin with a solvent or the like, and then volatilizes volatile components such as a solvent in a drying process to cure the thermosetting resin. It is manufactured by a method that adjusts By dispersing the filler in the varnish, a substrate material 51 used in the present embodiment is manufactured. In this embodiment there use a silica-based filler on silica (Si0 2) from about. 1 to 2 m in diameter.
図 5 A に示すように、 ビア穴 1 3の周囲には低流動層 5 1 1が形 成されている。 この低流動層 5 1 1 はレーザ加工時に加工エネルギ 一がフィ ラー 5 1 0 に吸収され熱に変換され周囲の熱硬化性樹脂が 変性する現象と、 変性した熱硬化性樹脂が固形分としてのフィ ラー 5 1 0 を核として層となる現象等により形成される。 フイ ラ一 5 1 0が無い場合より もその形成効率ははるかに高い。 また低流動層 5 1 1 にはガラス繊維織布 3 8が成分として含まれることも当然あり 得る。  As shown in FIG. 5A, a low fluidized bed 5 11 is formed around the via hole 13. In this low fluidized bed 511, the processing energy is absorbed by the filler 510 during laser processing and converted into heat, and the surrounding thermosetting resin is denatured. It is formed by a phenomenon that forms a layer with the filler 510 as a core. Its formation efficiency is much higher than without the filler. Naturally, the low-fluidized bed 5 11 1 may contain the glass fiber woven fabric 38 as a component.
低流動層 5 1 1が形成された後、 ビア穴 1 3 に導電性ペース ト 1 4を充填し、 熱プレス工程を実施する場合は、 図 5 Cに示すように 導電性ペース ト 1 4のビア穴 1 3周囲への広がりは防止されている c したがって導電性ペース ト 1 4による電気的層間接続は良好である c 低流動層 5 1 1 の形成はドリル加工でビア穴 1 3 を形成する場合 の摩擦熱等で基板材料 5 1 中の樹脂成分等を変質させてフィ ラー 5 1 0 とともに固形化することでも実現可能である。 しかしレーザを 用いてビア穴 1 3 を形成する際にフイ ラ一 5 1 0にエネルギーを吸 収させて熱変換し低流動層 5 1 1 を形成することが好ましい。 After the low fluidized bed 5 11 is formed, the via hole 13 is filled with the conductive paste 14 and the hot pressing process is performed. spread forms of electrical interlayer connection is good c low flow layer 5 1 1 by c therefore conductive paste 1 4 is prevented in the via hole 1 3 surrounding to form the via hole 1 3 drilling It can also be realized by altering the resin component and the like in the substrate material 51 by frictional heat or the like in the case and solidifying it together with the filler 5 10. However, when the via hole 13 is formed by using a laser, it is preferable to absorb energy in the filer 50 and convert it to heat to form the low fluidized layer 511.
なお、 この工程で用いるレーザの波長に関して、 炭酸ガスレーザ によって 9 m以上の発振波長を用いた場合に低流動層 5 1 1 の形 成が効率的である。 また、 フィ ラー 5 1 0の材質としてシリカ以外 の材料を用いてもよく、 タルク、 石膏粉等あるいは金属の水酸化物 等 (水酸化アルミ等) でも同様の効果が得られる。  Regarding the wavelength of the laser used in this step, the formation of the low fluidized bed 511 is efficient when an oscillation wavelength of 9 m or more is used by the carbon dioxide laser. Further, a material other than silica may be used as the material of the filler 510, and the same effect can be obtained by using talc, gypsum powder or the like, or metal hydroxide (such as aluminum hydroxide).
以上述べた全ての実施の形態で基板材料は、 ガラス繊維織布に熱 硬化性樹脂を含浸し Bステージ化したものとして説明したが、 ガラ ス繊維織布の変わりに不織布を用いてもよい。 ガラス繊維の代わり にァラミ ド等の有機繊維を用いてもよい。 In all of the embodiments described above, the substrate material is made of a woven glass fiber fabric. Although the description has been made assuming that the resin is impregnated with the curable resin and B-staged, a non-woven fabric may be used instead of the glass fiber woven fabric. Organic fibers such as aramid may be used instead of glass fibers.
また発明の形態 1 、 2 、 4では基板材料にプリプレダに代えて B ステージフィルムを用いてもよい。  In the first, second, and fourth embodiments, a B-stage film may be used instead of the pre-predader as the substrate material.
また、 織布と不織布を混成した材料、 たとえば 2枚のガラス繊維 の間にガラス繊維不織布を挟み込んだような材料を補強材として用 いてもよい。  Further, a material in which a woven fabric and a nonwoven fabric are mixed, for example, a material in which a glass fiber nonwoven fabric is sandwiched between two glass fibers may be used as a reinforcing material.
また、 本発明の全ての実施の形態における熱硬化性樹脂はェポキ シ系樹脂として説明したが、 以下のようなものを用いてもよい。 ェ ポキシ · メラミン系樹脂、 不飽和ポリエステル系樹脂、 フエノール 系樹脂、 ポリイミ ド系樹脂、 シァネー ト系樹脂、 シアン酸エステル 系樹脂、 ナフタレン系樹脂、 ユリア系樹脂、 アミノ系樹脂、 アルキ ド系樹脂、 ケィ素系樹脂、 フラン系樹脂、 ポリ ウレタン系樹脂、 ァ ミノアルキド系樹脂、 アク リル系樹脂、 フッ素系樹脂、 ポリ フエ二 レンエーテル系樹脂、 シァネートエステル系樹脂等の単独、 あるい は 2種以上混合した熱硬化性樹脂組成物あるいは熱可塑樹脂で変性 された熱硬化性樹脂組成物。 必要に応じて難燃剤や無機充填剤の添 加も可能である。  Although the thermosetting resin in all the embodiments of the present invention has been described as an epoxy resin, the following may be used. Epoxy / melamine resin, unsaturated polyester resin, phenolic resin, polyimide resin, cyanate resin, cyanate ester resin, naphthalene resin, urea resin, amino resin, alkyd resin, Single or two types of silicone resin, furan resin, polyurethane resin, amino alkyd resin, acryl resin, fluorine resin, polyphenylene ether resin, cyanate ester resin, etc. A thermosetting resin composition mixed with the above or a thermosetting resin composition modified with a thermoplastic resin. If necessary, flame retardants and inorganic fillers can be added.
また、 銅箔の代わりに支持体に仮止めされた金属箔等からなる回 路を用いることもできる。  Further, a circuit made of a metal foil or the like temporarily fixed to a support may be used instead of the copper foil.
また、 層間接続部として銅粉等の導電性粒子と硬化剤と熱硬化性 樹脂とを混練した導電性ペース トを用いて説明した。 代わりに熱プ レス時に基板材料中に排出されてしまうような適当な粘度の高分子 材料と導電性粒子を混練したもの、 あるいは溶剤等を添加したもの など多種の組成が利用可能である。 さ らに、 導電性ペース ト以外に めっき等により形成したポス ト状の導電性突起や、 ペース ト化して いない比較的大きな粒径の導電性粒子を単独で層間接続部として用 いることも可能である。 産業上の利用可能性 Also, the description has been given using a conductive paste in which conductive particles such as copper powder, a curing agent, and a thermosetting resin are kneaded as the interlayer connection portion. Instead, a variety of compositions can be used, such as a mixture of a polymer material having an appropriate viscosity that is discharged into the substrate material during heat pressing and conductive particles, or a mixture of a solvent and the like. Furthermore, in addition to the conductive paste, post-shaped conductive protrusions formed by plating or the like, or conductive particles having a relatively large particle size that is not pasted can be used alone as an interlayer connection part. It is. Industrial applicability
本発明の回路形成基板の製造方法においては、 以下のいずれかの 構成とする。 A ) 熱プレス工程での樹脂流動を制限する。 B ) 補強 繊維同士を融着もしくは接着する。 C ) 充填工程の後に基板材料の 厚みを減少させる。 D ) 基板材料中に混在するフイ ラ一で低流動層 を形成する。 また、 本発明の回路形成基板の製造用材料においては、 熱プレス工程での樹脂流動が制御される物性値を付与する、 あるい は充填工程の後に基板材料の厚みが効率的に現象できるよう揮発成 分を含む構成とする。 この本発明によれば、 導電性ペースト等の層 間接続部による電気的接続の発現が効率的に行える。  In the method for manufacturing a circuit forming substrate according to the present invention, any one of the following configurations is adopted. A) Limit the resin flow during the hot pressing process. B) Reinforcing fibers are fused or bonded together. C) Reduce the thickness of the substrate material after the filling process. D) A low fluidized bed is formed with the filler mixed in the substrate material. Further, in the material for manufacturing a circuit-formed substrate of the present invention, a physical property value for controlling the resin flow in the hot pressing step is imparted, or the thickness of the substrate material can be efficiently reduced after the filling step. The configuration shall include volatile components. According to the present invention, the electrical connection can be efficiently achieved by the inter-layer connection portion such as the conductive paste.
特に、 基板材料の補強材に織布を用いた場合には、 織布の持つ寸 法安定性などの利点を生かしながら、 層間の接続を安定化できると いう格別の効果を発揮する。 これは流動性の制御あるいは層間接続 を行う部分に対して繊維の動きを局所的に防止する処理を穴加工と 同時に施す、あるいは基板材料の厚みを減少させる等の処理による。 以上の結果として、 導電性ペース ト等の層間接続部を用いた層間 の電気的接続の信頼性が向上し、 高品質の高密度回路形成基板を提 供できる。  In particular, when a woven fabric is used as a reinforcing material for the substrate material, it has a particular effect that the connection between layers can be stabilized while taking advantage of the dimensional stability and the like of the woven fabric. This is due to the process of controlling the fluidity or locally preventing the movement of the fiber at the part where the interlayer connection is to be performed, simultaneously with the drilling, or by reducing the thickness of the substrate material. As a result of the above, the reliability of electrical connection between layers using an interlayer connection portion such as a conductive paste is improved, and a high-quality, high-density circuit board can be provided.

Claims

BW 求 の 範 囲 BW request range
1 . 層間接続部を形成するための穴を有する Bステージ状態基 板材料を少なく とも含む基板材料を積層する積層工程と、 前記基板材料を加熱と加圧とを伴う熱プレス工程と、 を含み 前記熱プレス工程において前記 Bステージ状態基板材料が 周囲に流れ出す流れ量が、 前記基板材料の 2 0 %重量以下である、 回路形成基板の製造方法。  1. A laminating step of laminating a substrate material including at least a B-stage state substrate material having a hole for forming an interlayer connection, and a hot pressing step involving heating and pressing the substrate material. The circuit forming substrate manufacturing method, wherein a flow amount of the B-stage state substrate material flowing out to the periphery in the hot pressing step is 20% by weight or less of the substrate material.
2 . 前記積層工程において前記 Bステージ状態基板材料ととも に以下のうち少なく とも 1 を積層する、  2. In the laminating step, at least one of the following is laminated with the B-stage state substrate material:
請求項 1 に記載の回路形成基板の製造方法。  A method for manufacturing the circuit-formed substrate according to claim 1.
( 1 ) 金属箔  (1) Metal foil
( 2 ) 支持体に貼りつけられた金属箔  (2) Metal foil attached to the support
( 3 ) 支持体に貼りつけられ回路パターン  (3) Circuit pattern attached to the support
( 4 ) 回路パターンを備えた Cステージ状態基板材料 ( 5 ) 金属箔を備えた Cステージ状態基板材料  (4) C-stage substrate material with circuit pattern (5) C-stage substrate material with metal foil
3 . 前記 Bステージ状態基板材料が少なく とも金属箔と回路パ ターンのうちいずれか一方を備える、  3. The B-stage state substrate material includes at least one of a metal foil and a circuit pattern,
請求項 1 に記載の回路形成基板の製造方法。  A method for manufacturing the circuit-formed substrate according to claim 1.
4 . 前記熱プレス工程において、 少なく とも Bステージ状態基板 材料の流動する領域での昇温速度が毎分 3 °C以下である、 4. In the hot pressing step, at least a temperature rising rate in a region where the substrate material flows in the B-stage state is 3 ° C or less per minute.
請求項 1 に記載の回路形成基板の製造方法。  A method for manufacturing the circuit-formed substrate according to claim 1.
5 . 少なく とも Bステージ状態基板材料を含む基板材料を積層 する積層工程と、 5. A laminating step of laminating a substrate material including at least a B-stage state substrate material;
前記 Bステージ状態基板材料に眉間接続部を形成するため の穴を形成する穴形成工程と、 を含み、  A hole forming step of forming a hole for forming a connection between eyebrows in the B-stage state substrate material;
前記穴形成工程において Bステージ状態基板材料の成分を 溶融あるいは変質させる、  Melting or altering the components of the B-stage state substrate material in the hole forming step;
回路形成基板の製造方法。  A method for manufacturing a circuit forming substrate.
6 . 前記前記穴形成工程において、 前記 Bステージ状態基板材料 中の補強材と補強繊維のうち少なく ともいずれか一方を固着する、 7 請求項 5 に記載の回路形成基板の製造方法。 6. In the hole forming step, at least one of a reinforcing material and a reinforcing fiber in the B-stage state substrate material is fixed. 7. A method for manufacturing a circuit-formed substrate according to claim 5.
7 前一一記穴形成工程がエネルギービーム加工である、  7 The hole forming process is energy beam processing.
請求項 5 に記載の回路形成基板の製造方法。  A method for manufacturing the circuit-formed substrate according to claim 5.
8 前記エネルギービーム加工がレーザ加工である、  8 The energy beam processing is laser processing,
請求項 7 に記載の回路形成基板の製造方法。  A method for manufacturing the circuit-formed substrate according to claim 7.
9 前記レーザ加工が炭酸ガスレーザである、  9 The laser processing is a carbon dioxide laser,
請求項 8 に記載の回路形成基板の製造方法。  A method for manufacturing the circuit-formed substrate according to claim 8.
1 0 レーザ波長が 1 0 以上である、  10 laser wavelength is 10 or more,
請求項 9 に記載の回路形成基板の製造方法。  A method for manufacturing a circuit-formed substrate according to claim 9.
1 1 少なく とも Bステージ状態基板材料を含む基板材料を積層す る積層工程と、  1 1 A laminating step of laminating a substrate material including at least the B-stage state substrate material;
前記 Bステージ状態基板材料に層間接続部を形成するため の穴を形成する穴形成工程と、  A hole forming step of forming a hole for forming an interlayer connection portion in the B-stage state substrate material;
前記 Bステージ状態基板材料の厚みを減少させる積層準備 工程と、 を含む、  A laminating preparation step of reducing the thickness of the B-stage state substrate material.
回路形成基板の製造方法。  A method for manufacturing a circuit forming substrate.
2 前記穴に導電性物質を充填する充填工程と、 をさらに備え、 前記積層準備工程を前記充填工程の後に実施する、  2 a filling step of filling the hole with a conductive material, further comprising: performing the lamination preparation step after the filling step;
求項 1 1 に記載の回路形成基板の製造方法。  A method for manufacturing a circuit-formed substrate according to claim 11.
1 3 . 前記積層準備工程で前記 Βステージ状態基板材料中の揮発成 分を揮発させる、  13. Volatile volatile components in the substrate material in the 基板 stage state in the lamination preparation step;
請求項 1 1記載の回路形成基板の製造方法。  A method for manufacturing a circuit-formed substrate according to claim 11.
1 4 . 前記積層準備工程で前記 Βステージ状態基板材料をエツチン グする、  14. Etch the Βstage state substrate material in the lamination preparation step;
求項 ί己載の回路形成基板の製造方法,  Request 方法 manufacturing method of self-loaded circuit forming substrate,
1 5 . 少なく とも Βステージ状態基板材料を含む基板材料を積層す る積層工程と、  15. A laminating step of laminating a substrate material including at least a stage-state substrate material;
前記 Βステージ状態基板材料に層間接続部を形成するため の穴を形成する穴形成工程と、 を含み、  A hole forming step of forming a hole for forming an interlayer connection part in the stage-state substrate material;
前記穴加工工程において前記穴周辺に前記 Βステージ状態 基板材料中の固形分を含む低流動層が形成される、 In the hole drilling process, the Β stage state around the hole A low fluidized bed containing solids in the substrate material is formed,
回路形成基板の製造方法。  A method for manufacturing a circuit forming substrate.
1 6 . 前記穴形成工程がエネルギービーム加工である、  1 6. The hole forming step is energy beam processing.
請求項 1 5 に記載の回路形成基板の製造方法。  A method for manufacturing a circuit-formed substrate according to claim 15.
1 7 . 前記エネルギービーム加工がレーザ加工である、  17. The energy beam processing is laser processing.
請求項 1 6に記載の回路形成基板の製造方法。  A method for manufacturing a circuit-formed substrate according to claim 16.
1 8 . 前記レーザ加工が炭酸ガスレーザである、  1 8. The laser processing is a carbon dioxide laser,
請求項 1 7 に記載の回路形成基板の製造方法。  A method for manufacturing the circuit-formed substrate according to claim 17.
1 9 . レーザ波長が 9 m以上である、  1 9. The laser wavelength is 9m or more,
請求項 1 8に記載の回路形成基板の製造方法。  19. The method for manufacturing a circuit-formed substrate according to claim 18.
2 0 . 2層以上の回路形成基板を製造するために層間接続部を設け る Bステージ状態基板材料であって、 20. A B-stage state substrate material which is provided with an interlayer connection for producing a circuit forming substrate having two or more layers,
熱プレス時の流れ量が 2 0重量%以下である、  The flow rate during hot pressing is 20% by weight or less,
回路形成基板の製造用材料。  Materials for manufacturing circuit-formed substrates.
2 1 . 2層以上の回路形成基板を製造するために層間接続部を設け る Bステージ状態基板材料に含まれる材料であって、 21.1 A material included in the B-stage state substrate material in which an interlayer connection portion is provided for manufacturing a circuit forming substrate having two or more layers,
硬化時間が 1 1 0秒以下である、  Curing time is 110 seconds or less,
回路形成基板の製造用材料。  Materials for manufacturing circuit-formed substrates.
2 2 . 2層以上の回路形成基板を製造するために層間接続部を設け る Bステージ状態基板材料であって、 22. A B-stage state substrate material which is provided with an interlayer connection part for manufacturing a circuit forming substrate having two or more layers,
揮発分を 0 . 5重量%以上含む、  Contains 0.5% by weight or more of volatile matter,
回路形成基板の製造用材料。  Materials for manufacturing circuit-formed substrates.
2 3 . 2層以上の回路形成基板を製造するために層間接続部を設け る Bステージ状態基板材料であって、 23. A B-stage state substrate material that is provided with an interlayer connection for manufacturing a circuit forming substrate having two or more layers,
前記層間接続部を設けるための穴を形成する工程において 前記穴の周囲に低流動層を形成する固形分を含む、  In the step of forming a hole for providing the interlayer connection portion, including a solid content forming a low fluidized bed around the hole,
回路形成基板の製造用材料。  Materials for manufacturing circuit-formed substrates.
2 4 . 前記固形分が無機質材料のフィ ラーを主体とする、 24. The solid content is mainly composed of a filler made of an inorganic material.
請求項 2 2記載の回路形成基板の製造用材料。  A material for producing the circuit-formed substrate according to claim 22.
PCT/JP2002/007262 2001-07-18 2002-07-17 Method and material for manufacturing circuit-formed substrate WO2003009660A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE60235301T DE60235301D1 (en) 2001-07-18 2002-07-17 MANUFACTURING PROCESS OF A PCB
JP2003514862A JPWO2003009660A1 (en) 2001-07-18 2002-07-17 Method for manufacturing circuit-formed substrate and material for manufacturing circuit-formed substrate
US10/380,661 US7059044B2 (en) 2001-07-18 2002-07-17 Method and material for manufacturing circuit-formed substrate
EP02749309A EP1408726B1 (en) 2001-07-18 2002-07-17 Method of manufacturing a printed wiring board

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001-217774 2001-07-18
JP2001217774 2001-07-18

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WO2003009660A1 true WO2003009660A1 (en) 2003-01-30

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EP (1) EP1408726B1 (en)
JP (1) JPWO2003009660A1 (en)
CN (2) CN1794902B (en)
DE (1) DE60235301D1 (en)
TW (1) TW558931B (en)
WO (1) WO2003009660A1 (en)

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CN1465218A (en) 2003-12-31
EP1408726B1 (en) 2010-02-10
US20040067348A1 (en) 2004-04-08
CN1794902A (en) 2006-06-28
EP1408726A1 (en) 2004-04-14
DE60235301D1 (en) 2010-03-25
EP1408726A4 (en) 2007-09-19
CN100473261C (en) 2009-03-25
US7059044B2 (en) 2006-06-13
CN1794902B (en) 2010-05-26
TW558931B (en) 2003-10-21

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