WO2003009660A1 - Method and material for manufacturing circuit-formed substrate - Google Patents
Method and material for manufacturing circuit-formed substrate Download PDFInfo
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- WO2003009660A1 WO2003009660A1 PCT/JP2002/007262 JP0207262W WO03009660A1 WO 2003009660 A1 WO2003009660 A1 WO 2003009660A1 JP 0207262 W JP0207262 W JP 0207262W WO 03009660 A1 WO03009660 A1 WO 03009660A1
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- substrate material
- substrate
- forming
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4632—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating thermoplastic or uncured resin sheets comprising printed circuits without added adhesive materials between the sheets
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
- H05K3/4655—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern by using a laminate characterized by the insulating layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/0373—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0191—Dielectric layers wherein the thickness of the dielectric plays an important role
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0206—Materials
- H05K2201/0209—Inorganic, non-metallic particles
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0275—Fibers and reinforcement materials
- H05K2201/029—Woven fibrous reinforcement or textile
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09581—Applying an insulating coating on the walls of holes
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0191—Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/065—Binding insulating layers without adhesive, e.g. by local heating or welding, before lamination of the whole PCB
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/08—Treatments involving gases
- H05K2203/083—Evaporation or sublimation of a compound, e.g. gas bubble generating agent
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/002—Etching of the substrate by chemical or physical means by liquid chemical etching
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49133—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting
- Y10T29/49135—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting and shaping, e.g., cutting or bending, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
Definitions
- the present invention relates to a method for manufacturing a circuit forming substrate used for various electronic devices and a material for manufacturing the circuit forming substrate.
- the substrate material 61 shown in FIG. 6A is a pre-predator in which a glass fiber woven fabric used for a circuit forming substrate is impregnated with a thermosetting epoxy resin or the like, and is placed in a B stage state by a method such as drying.
- a film 62 is attached to both sides of the substrate material 61 by a laminating method using a hot roll or the like.
- via holes 63 are formed in the substrate material 61 by a processing method such as laser.
- a conductive paste 64 formed by kneading conductive particles such as copper powder and a thermosetting resin, a curing agent, and a solvent is filled in the via hole 63.
- the conductive paste 64 as shown in FIG.
- copper foil 65 is placed on both sides and heated and pressed by a hot press device (not shown), the substrate material 61 is thermally cured as shown in FIG. 6E, and the conductive paste 64 is compressed.
- the copper foil 65 on both sides is electrically connected.
- the epoxy resin impregnated in the substrate material 61 flows and flows out to form a flow-out portion 66.
- an extra portion of the end is cut off to obtain a shape as shown in Fig.
- a circuit-formed substrate on both sides as shown in FIG. 6G is obtained.
- the electrical connection between the front and back of the circuit forming substrate may be insufficient.
- similar defects may occur in the circuit of the surface layer and the inner layer.
- the main cause is the occurrence of outflow particles 610 in which the conductive particles in the conductive paste 64 flow out of the via holes 63 as shown in FIG. 6E.
- the conductive paste 64 is compressed in the vertical direction in Fig. 6E, and the conductive particles in the conductive paste come into strong contact with each other efficiently. Need to be firmly in contact with them.
- the thermosetting resin in the substrate material 61 flows outward, as can be seen from the formation of the outflow portion 66 in the process from FIG. 6D to FIG. 6E.
- the conductive particles in the conductive paste 64 are swept away in the lateral direction of FIG. 6E, and as a result, the conductive paste 64 cannot be efficiently compressed.
- the electrical connection becomes unstable.
- FIGS. 7A to 7C As shown in FIG. 7A, via holes 63 are formed in a substrate material 61 using a glass fiber woven fabric 68 using a laser. When viewed from above, the via hole 63 is formed by cutting the glass fiber woven cloth 68 as shown in FIG. 7B. Thereafter, the steps as described with reference to FIGS. 6C to 6E are performed.
- the main factors that determine the amount of compression of the conductive paste 4 are the amount by which the substrate material 61 is compressed in the thickness direction in the hot pressing process in FIGS. 6D to 6E, and the amount of the substrate material 61 in FIG. 6D. This is the amount by which the conductive paste 64 protrudes from.
- an element that exerts a compressive action on conductive paste 64 is required in addition to controlling the two main factors described above. It is. Disclosure of the invention
- the resin flow in the hot pressing step is restricted. Thereby, the electrical connection by the interlayer connection part such as the conductive paste is efficiently performed.
- a resin whose flow is controlled in the hot pressing step is used. Thereby, the electrical connection by the interlayer connection part such as the conductive paste is efficiently performed.
- FIGS. 1A to 1G show the manufacture of a circuit forming substrate according to the first embodiment of the present invention. It is a process sectional view showing a fabrication method.
- FIGS. 2A to 2E are process cross-sectional views illustrating a method for manufacturing a circuit-formed substrate according to the second embodiment of the present invention.
- FIG. 3A is a schematic sectional view of a via forming step in the method for manufacturing a circuit-formed substrate according to the third embodiment of the present invention.
- FIG. 3B is a top view of a via portion before filling with a conductive paste in the method of manufacturing a circuit-formed substrate according to the third embodiment of the present invention.
- FIG. 3C is a top view of the via portion after filling the conductive paste in the method of manufacturing the circuit-formed substrate according to the third embodiment of the present invention.
- 4A to 4H are process cross-sectional views illustrating a method for manufacturing a circuit-formed substrate according to the fourth embodiment of the present invention.
- FIG. 5A is a schematic cross-sectional view of a via forming step in the method for manufacturing a circuit-formed substrate according to the fifth embodiment of the present invention.
- FIG. 5B is a top view of a via portion before filling with a conductive paste in the method of manufacturing a circuit-formed substrate according to the fifth embodiment of the present invention.
- FIG. 5C is a top view of the via portion after filling the conductive paste in the method of manufacturing a circuit-formed substrate according to the fifth embodiment of the present invention.
- 6A to 6G are process cross-sectional views illustrating a method for manufacturing a circuit-formed substrate according to the related art.
- FIG. 7A is a schematic cross-sectional view of a via formation process in a conventional method for manufacturing a circuit formation substrate.
- FIG. 7B is a top view of the via portion before filling the conductive base in the conventional method of manufacturing a circuit-formed substrate.
- FIG. 7C is a top view of the via portion after filling the conductive base in the conventional method of manufacturing a circuit-formed substrate.
- FIG. 1A to 1G are process cross-sectional views showing a method for manufacturing a circuit-forming substrate and materials for manufacturing the circuit-forming substrate according to the first embodiment of the present invention.
- a board material made of a pre-predeer with a thickness of 100 0 // m and impregnated with a thermosetting epoxy resin using a glass fiber woven fabric as a reinforcing material Attach film 2 of m.
- the film 12 uses polyethylene terephthalate (PET). If necessary, a thermosetting resin such as an epoxy resin may be coated on the film 12.
- a via hole 13 having a diameter of about 200 m is formed using a carbon dioxide gas laser.
- the conductive paste 14 is filled in the via hole 13 by screen printing or the like.
- the conductive paste 14 is obtained by kneading copper powder having a diameter of about 5 m, a thermosetting resin, and a curing agent. A solvent or the like may be added to the conductive paste 4 for the purpose of adjusting viscosity or the like.
- FIG. 1D when the films 12 on both sides of the substrate material 11 are peeled off, the substrate material 1 1
- the conductive base 14 protrudes from the film 12 to about the thickness of the film 12. Copper foil 15 is placed on both sides.
- thermosetting resin in the substrate material 11 flows to form a flow-out portion 16.
- a circuit 17 is formed by patterning the copper foil 15 by a method such as etching to obtain a double-sided circuit-formed substrate as shown in FIG. 1G.
- the mass of the resin that flows in the hot pressing process and flows out around the substrate material 11 with respect to the mass of the substrate material 11 before hot pressing in the above process, that is, the mass of the flow-out portion 16 in FIG. 1E Is the resin flow rate.
- the resin flow rate In order to solve the problem of insufficient electrical connection by the conductive paste 14 described in the background art, the resin flow rate must be at least 20% or less.
- Table 1 shows examples of the experimental results by the inventors have studied the resin flow quantity summarizes the following measurement results.
- connection resistance per one point (average value) determined from the electrical resistance of a test pattern circuit in which 500 via holes are connected in series with the copper foil on the front and back of the board
- the sample is stored for a long period of time in a high-temperature, high-humidity environment, etc., and the reliability is evaluated by measuring the change over time in the via connection resistance.
- the heating rate is 0.5 t / min. : More preferably.
- the heating rate is controlled to 3 or less per minute only in the time range where the fluidity increases during the hot pressing process. During the time period, the temperature may be increased at a faster rate.
- the uncured epoxy resin is heated and dried, and the volatile components, the amount of residual solvent, and the degree of thermal curing are controlled by the heating temperature and time to change the curing time.
- the curing time which indicates the melting and curing characteristics of the substrate material during hot pressing, is set to 110 seconds or less.
- the curing time is preferably 10 seconds or more in order to avoid the occurrence of the above-mentioned poor filling property. Further, from the viewpoint of the adhesion between the copper foil 15 and the substrate material 11 in FIG. 1E or the absorption of the resin amount, it is more preferable to set the time to 50 seconds or more.
- Embodiment 1 is an example of a double-sided circuit-formed substrate, it is preferable to apply the present invention also to manufacture a multilayer circuit-formed substrate as shown in FIGS. 2A to 2E.
- a double-sided circuit forming substrate as shown in FIG. 2A is prepared.
- the board material 11 filled with the conductive paste 14 and the copper foil 15 are aligned and placed on the front and back of the double-sided circuit board, and heated and pressed by a heat press device or the like. .
- the substrate material 11 is molded and cured as shown in FIG. 2C.
- the component of the flowing substrate material 1 flows out to form a flow-out portion 26.
- the weight of the flow-out portion 26 (the amount of resin flow) becomes 20% or less with respect to the weight of the two substrate materials 11 by the method described in the first embodiment. To do.
- the copper foil 15 is patterned by etching or the like to form a circuit 27, and Fig. 2E Obtain a 4-layer circuit forming substrate as shown.
- the electrical connection between the layers can be favorably formed by applying the method for producing a circuit formation substrate and the material for production of the present invention.
- the double-sided circuit forming substrate used in the present embodiment may be the substrate described in the first embodiment, or may be a substrate in which connection between layers is formed by a normal plating method or the like. Further, a configuration in which the substrate material 11 is temporarily pressure-bonded to the double-sided circuit formation substrate in the step shown in FIG.
- FIGS. 3A to 3C A third embodiment of the present invention will be described below with reference to FIGS. 3A to 3C.
- a via hole 13 is formed in a pre-prepared substrate material 11 using a glass fiber woven fabric 38 by using a laser.
- the via hole 13 is formed by cutting the glass fiber woven fabric 38 as shown in FIG. 3B.
- a welded portion 39 as shown in FIG. 3B is formed by a specific processing method.
- the conductive paste 14 is filled into the via hole 13 after the welded part 39 is formed and the hot pressing process is performed, as shown in Fig. 3C, around the via hole 13 of the conductive paste 14 Spread is prevented. Therefore, the electrical interlayer connection by the conductive paste 14 is good.
- the via hole 13 is formed by drilling, the welded portion 39 is formed by transforming the resin component and the like in the substrate material 11 by frictional heat or the like at the time of application and solidifying the glass fiber fabric 3 8 Can also be realized by fixing around the via hole 13.
- the welded portion 39 does not need to be composed only of a reinforcing material such as glass fiber, and the resin component and the like in the substrate material 11 are hardened or deteriorated by heat or the like at the time of processing, so that the subsequent hot pressing step The same effect can be obtained if the fluidity at the point is lost.
- the glass fiber woven fabric 38 is melted or deteriorated to form the welded portion 39 mainly composed of the glass fiber woven fabric 38.
- Table 2 shows examples of the study results of the inventor.
- Via holes 13 were processed under various conditions using three types of laser oscillators to produce a double-sided circuit-formed substrate, and the contents described in Embodiment 1 were used. 0 Similarly, the results of comparing the via connection resistance values are summarized.
- the via connection resistance value is related to the laser wavelength.
- the formation of a welded portion is confirmed at an oscillation wavelength of 10.6, but no welded portion is observed when an oscillation wavelength of 9.4 m is used. .
- Table 2
- welds When using various lasers such as excimer lasers, YAG harmonics, carbon dioxide lasers, etc., it is possible to form welds depending on the processing conditions. Heating is preferred for forming the weld.
- the use of a carbon dioxide laser is advantageous in terms of processing speed and cost.
- the laser-based processing method is more preferable.
- Embodiment 4 will be described with reference to FIGS. 4A to 4H.
- substrate material 41 is made of polyethylene terephthalate (PET) on both sides using glass fiber woven fabric as a reinforcing material. This is a 100 m thick pre-preder to which an m film 12 is attached. If necessary, the film 12 may be coated with a thermosetting resin such as an epoxy resin.
- PET polyethylene terephthalate
- This substrate material 41 differs from the substrate material 11 in the first embodiment in that a large amount of volatile components remain when a pre-preda is manufactured. From the weight change before and after drying for 160 hours, the volatile content is 3%.
- FIGS. 4B to 4D Subsequent steps shown in FIGS. 4B to 4D are the same as in the first embodiment.
- the substrate material 41 is introduced into a vacuum drying device (not shown), and dried in a vacuum of about 133 Pa for one hour.
- a process of introducing hot air at 50 ° C into the vacuum drying apparatus and reducing the pressure again is performed three times.
- the thickness of the substrate material 41 is reduced, and the reduction is about 2 / m.
- the height of the protruding portion of the conductive base 14 from the substrate material 41 of about 20 m increases by about 1 m on each of the front and back sides of the substrate material, to about 22 m. Become.
- a circuit 17 is formed by patterning the copper foil 15 by a method such as etching to obtain a double-sided circuit forming substrate as shown in FIG. 1H.
- the height of the projecting portion of the conductive paste 14 is increased by only 2 m before the hot pressing. To improve the electrical connection.
- the normal hot pressing process uses a vacuum press, it is considered that most of the volatile components in the substrate material are removed during the hot pressing process.
- the amount of the component of the substrate material flowing during the hot pressing process is relatively large, which is disadvantageous in that the conductive paste is compressed in the thickness direction of the substrate to realize electrical connection.
- the volatile components in the substrate material 41 are removed by vacuum drying before the hot pressing step, and the flow during hot pressing is controlled.
- the height of the conductive paste 14 projecting from the substrate material 41 is increased, and the effective compression amount is increased.
- the conductive paste 14 can be extremely efficiently compressed in the hot pressing step, and the electrical connection between the circuits 17 on the front and back of the circuit forming substrate becomes sufficient.
- the method described above is also suitably applied to the substrate material 21 when manufacturing the multilayer circuit forming substrate as described in the second embodiment.
- a high-boiling solvent such as BCA (butyl carbitol acetate) is contained as a volatile component in the production process of the substrate material 41.
- the step of reducing the thickness of the substrate material 41 has been described using the vacuum drying method, it may be performed by a normal drying method involving heating under conditions that do not cause a problem in the physical properties of the substrate material 41. .
- the interlayer connection portion protrudes from the substrate material even when a method of selectively etching the substrate material by a dry or wet etching method using a plasma excimer laser is used.
- the amount to do can be secured. In this case, there is also an effect that the thickness reduction and the small amount of the substrate material are stabilized. (Embodiment 5)
- a fifth embodiment of the present invention will be described below with reference to FIGS. 5A to 5C.
- a via hole 13 is formed in a pre-prepared substrate material 51 using a glass fiber woven fabric 38 by using a laser.
- the substrate material 51 contains a filler 5 10 as a solid content.
- the usual substrate material is a glass fiber woven fabric 38, which is impregnated with a liquid material called a varnish obtained by diluting a thermosetting resin with a solvent or the like, and then volatilizes volatile components such as a solvent in a drying process to cure the thermosetting resin. It is manufactured by a method that adjusts By dispersing the filler in the varnish, a substrate material 51 used in the present embodiment is manufactured.
- a silica-based filler on silica (Si0 2) from about. 1 to 2 m in diameter.
- a low fluidized bed 5 11 is formed around the via hole 13.
- the processing energy is absorbed by the filler 510 during laser processing and converted into heat, and the surrounding thermosetting resin is denatured. It is formed by a phenomenon that forms a layer with the filler 510 as a core. Its formation efficiency is much higher than without the filler.
- the low-fluidized bed 5 11 1 may contain the glass fiber woven fabric 38 as a component.
- the via hole 13 is filled with the conductive paste 14 and the hot pressing process is performed.
- spread forms of electrical interlayer connection is good c low flow layer 5 1 1 by c therefore conductive paste 1 4 is prevented in the via hole 1 3 surrounding to form the via hole 1 3 drilling
- the via hole 13 is formed by using a laser, it is preferable to absorb energy in the filer 50 and convert it to heat to form the low fluidized layer 511.
- the formation of the low fluidized bed 511 is efficient when an oscillation wavelength of 9 m or more is used by the carbon dioxide laser.
- a material other than silica may be used as the material of the filler 510, and the same effect can be obtained by using talc, gypsum powder or the like, or metal hydroxide (such as aluminum hydroxide).
- the substrate material is made of a woven glass fiber fabric.
- a non-woven fabric may be used instead of the glass fiber woven fabric.
- Organic fibers such as aramid may be used instead of glass fibers.
- a B-stage film may be used instead of the pre-predader as the substrate material.
- a material in which a woven fabric and a nonwoven fabric are mixed for example, a material in which a glass fiber nonwoven fabric is sandwiched between two glass fibers may be used as a reinforcing material.
- thermosetting resin in all the embodiments of the present invention has been described as an epoxy resin, the following may be used.
- a circuit made of a metal foil or the like temporarily fixed to a support may be used instead of the copper foil.
- a conductive paste in which conductive particles such as copper powder, a curing agent, and a thermosetting resin are kneaded as the interlayer connection portion.
- a variety of compositions can be used, such as a mixture of a polymer material having an appropriate viscosity that is discharged into the substrate material during heat pressing and conductive particles, or a mixture of a solvent and the like.
- post-shaped conductive protrusions formed by plating or the like, or conductive particles having a relatively large particle size that is not pasted can be used alone as an interlayer connection part. It is. Industrial applicability
- any one of the following configurations is adopted.
- a physical property value for controlling the resin flow in the hot pressing step is imparted, or the thickness of the substrate material can be efficiently reduced after the filling step.
- the configuration shall include volatile components. According to the present invention, the electrical connection can be efficiently achieved by the inter-layer connection portion such as the conductive paste.
- a woven fabric when used as a reinforcing material for the substrate material, it has a particular effect that the connection between layers can be stabilized while taking advantage of the dimensional stability and the like of the woven fabric. This is due to the process of controlling the fluidity or locally preventing the movement of the fiber at the part where the interlayer connection is to be performed, simultaneously with the drilling, or by reducing the thickness of the substrate material. As a result of the above, the reliability of electrical connection between layers using an interlayer connection portion such as a conductive paste is improved, and a high-quality, high-density circuit board can be provided.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE60235301T DE60235301D1 (en) | 2001-07-18 | 2002-07-17 | MANUFACTURING PROCESS OF A PCB |
JP2003514862A JPWO2003009660A1 (en) | 2001-07-18 | 2002-07-17 | Method for manufacturing circuit-formed substrate and material for manufacturing circuit-formed substrate |
US10/380,661 US7059044B2 (en) | 2001-07-18 | 2002-07-17 | Method and material for manufacturing circuit-formed substrate |
EP02749309A EP1408726B1 (en) | 2001-07-18 | 2002-07-17 | Method of manufacturing a printed wiring board |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001-217774 | 2001-07-18 | ||
JP2001217774 | 2001-07-18 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2003009660A1 true WO2003009660A1 (en) | 2003-01-30 |
Family
ID=19052042
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2002/007262 WO2003009660A1 (en) | 2001-07-18 | 2002-07-17 | Method and material for manufacturing circuit-formed substrate |
Country Status (7)
Country | Link |
---|---|
US (1) | US7059044B2 (en) |
EP (1) | EP1408726B1 (en) |
JP (1) | JPWO2003009660A1 (en) |
CN (2) | CN1794902B (en) |
DE (1) | DE60235301D1 (en) |
TW (1) | TW558931B (en) |
WO (1) | WO2003009660A1 (en) |
Cited By (4)
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WO2013031822A1 (en) * | 2011-08-29 | 2013-03-07 | 京セラ株式会社 | Thin-film wiring substrate and substrate for probe card |
JP5196056B1 (en) * | 2012-06-14 | 2013-05-15 | パナソニック株式会社 | Composite multilayer wiring board and manufacturing method thereof |
WO2013186966A1 (en) * | 2012-06-14 | 2013-12-19 | パナソニック株式会社 | Composite multilayer wiring board and method for manufacturing same |
JPWO2016084375A1 (en) * | 2014-11-28 | 2017-09-07 | 日本ゼオン株式会社 | Manufacturing method of multilayer printed wiring board |
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JP2008103548A (en) * | 2006-10-19 | 2008-05-01 | Sumitomo Electric Ind Ltd | Multilayer printed wiring board, and its manufacturing method |
JP4713682B1 (en) * | 2010-02-25 | 2011-06-29 | パナソニック株式会社 | Multilayer wiring board and method for manufacturing multilayer wiring board |
JP4616927B1 (en) * | 2010-02-25 | 2011-01-19 | パナソニック株式会社 | WIRING BOARD, WIRING BOARD MANUFACTURING METHOD, AND VIA PASTE |
JP5589595B2 (en) * | 2010-06-21 | 2014-09-17 | 富士通株式会社 | Wiring board and manufacturing method thereof |
JP4795488B1 (en) * | 2011-01-18 | 2011-10-19 | パナソニック株式会社 | WIRING BOARD, WIRING BOARD MANUFACTURING METHOD, AND VIA PASTE |
US11600421B2 (en) * | 2017-04-14 | 2023-03-07 | The Diller Corporation | Laminate with induction coils |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5484647A (en) * | 1993-09-21 | 1996-01-16 | Matsushita Electric Industrial Co., Ltd. | Connecting member of a circuit substrate and method of manufacturing multilayer circuit substrates by using the same |
JPH08230106A (en) * | 1995-02-28 | 1996-09-10 | Hitachi Chem Co Ltd | Manufacture of copper foil-clad laminate |
JPH10158472A (en) * | 1996-11-28 | 1998-06-16 | Hitachi Chem Co Ltd | Epoxy resin composition, epoxy resin varnish, epoxy resin prepreg and multilayer printed wiring board made by using this epoxy resin prepreg as prepreg for bonding |
JPH10256726A (en) * | 1997-03-11 | 1998-09-25 | Matsushita Electric Ind Co Ltd | Manufacture of multilayer printed board |
JPH1117295A (en) * | 1997-06-27 | 1999-01-22 | Matsushita Electric Ind Co Ltd | Manufacture of prepreg for circuit board and prepreg for circuit board and manufacture of circuit board using the same device |
JPH1168275A (en) * | 1997-08-20 | 1999-03-09 | Matsushita Electric Ind Co Ltd | Circuit forming board, method and apparatus for forming circuit forming board |
JPH11177199A (en) * | 1997-12-05 | 1999-07-02 | Matsushita Electric Ind Co Ltd | Printed wiring board and its manufacture |
JP2000036666A (en) * | 1998-07-16 | 2000-02-02 | Matsushita Electric Ind Co Ltd | Multilayer printed wiring board and its manufacture |
JP2000307246A (en) * | 1999-04-26 | 2000-11-02 | Matsushita Electric Ind Co Ltd | Manufacture of circuit forming substrate and material thereof |
JP2001085838A (en) * | 1999-09-14 | 2001-03-30 | Matsushita Electric Works Ltd | Method for manufacturing multilayer laminated plate |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4816403A (en) * | 1986-08-04 | 1989-03-28 | Louisiana State University | Detoxification of chlorinated aromatic compounds by organism NRRL B-18086 |
US5445962A (en) * | 1988-08-05 | 1995-08-29 | Atallah; Yousef H. | Microorganisms |
JPH0392348A (en) * | 1989-09-04 | 1991-04-17 | Hitachi Chem Co Ltd | Preparation of laminated sheet |
US5538789A (en) * | 1990-02-09 | 1996-07-23 | Toranaga Technologies, Inc. | Composite substrates for preparation of printed circuits |
US5194713A (en) * | 1991-10-17 | 1993-03-16 | International Business Machines Corporation | Removal of excimer laser debris using carbon dioxide laser |
JPH05226848A (en) * | 1991-11-12 | 1993-09-03 | Nec Corp | Laminated layer thermo-compression jig |
US5563328A (en) * | 1992-08-19 | 1996-10-08 | Board Of Regents, University Of Nebraska-Lincoln | Promoters from chlorella virus genes providing for expression of genes in prokaryotic and eukaryotic hosts |
JP3057924B2 (en) * | 1992-09-22 | 2000-07-04 | 松下電器産業株式会社 | Double-sided printed circuit board and method of manufacturing the same |
JP3146712B2 (en) * | 1993-01-12 | 2001-03-19 | 松下電器産業株式会社 | Double-sided printed circuit board and method of manufacturing the same |
US5362865A (en) * | 1993-09-02 | 1994-11-08 | Monsanto Company | Enhanced expression in plants using non-translated leader sequences |
JP3087152B2 (en) * | 1993-09-08 | 2000-09-11 | 富士通株式会社 | Method for manufacturing resin film multilayer circuit board |
US5545818A (en) * | 1994-03-11 | 1996-08-13 | Calgene Inc. | Expression of Bacillus thuringiensis cry proteins in plant plastids |
US5656422A (en) * | 1994-10-05 | 1997-08-12 | Idaho Research Foundation, Inc. | Compositions and methods for detection of 2,4-dichlorophenoxyacetic acid and related compounds |
DE4444708A1 (en) * | 1994-12-15 | 1996-06-20 | Basf Ag | Use of auxin-type herbicides for the treatment of transgenic crop plants |
TW389780B (en) * | 1995-09-13 | 2000-05-11 | Hitachi Chemical Co Ltd | Prepreg for printed circuit board |
JP3197213B2 (en) * | 1996-05-29 | 2001-08-13 | 松下電器産業株式会社 | Printed wiring board and method of manufacturing the same |
CN1273762A (en) * | 1998-05-06 | 2000-11-15 | 日本碍子株式会社 | Printed circit board material and method of manufacturing board material and intermediate block body for board material |
US6224965B1 (en) * | 1999-06-25 | 2001-05-01 | Honeywell International Inc. | Microfiber dielectrics which facilitate laser via drilling |
JP3522165B2 (en) * | 1999-08-31 | 2004-04-26 | 京セラ株式会社 | Wiring board and manufacturing method thereof |
-
2002
- 2002-07-17 TW TW091115942A patent/TW558931B/en not_active IP Right Cessation
- 2002-07-17 EP EP02749309A patent/EP1408726B1/en not_active Expired - Fee Related
- 2002-07-17 DE DE60235301T patent/DE60235301D1/en not_active Expired - Lifetime
- 2002-07-17 JP JP2003514862A patent/JPWO2003009660A1/en active Pending
- 2002-07-17 CN CN2005101286878A patent/CN1794902B/en not_active Expired - Fee Related
- 2002-07-17 US US10/380,661 patent/US7059044B2/en not_active Expired - Fee Related
- 2002-07-17 CN CNB028024214A patent/CN100473261C/en not_active Expired - Fee Related
- 2002-07-17 WO PCT/JP2002/007262 patent/WO2003009660A1/en active Application Filing
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5484647A (en) * | 1993-09-21 | 1996-01-16 | Matsushita Electric Industrial Co., Ltd. | Connecting member of a circuit substrate and method of manufacturing multilayer circuit substrates by using the same |
JPH08230106A (en) * | 1995-02-28 | 1996-09-10 | Hitachi Chem Co Ltd | Manufacture of copper foil-clad laminate |
JPH10158472A (en) * | 1996-11-28 | 1998-06-16 | Hitachi Chem Co Ltd | Epoxy resin composition, epoxy resin varnish, epoxy resin prepreg and multilayer printed wiring board made by using this epoxy resin prepreg as prepreg for bonding |
JPH10256726A (en) * | 1997-03-11 | 1998-09-25 | Matsushita Electric Ind Co Ltd | Manufacture of multilayer printed board |
JPH1117295A (en) * | 1997-06-27 | 1999-01-22 | Matsushita Electric Ind Co Ltd | Manufacture of prepreg for circuit board and prepreg for circuit board and manufacture of circuit board using the same device |
JPH1168275A (en) * | 1997-08-20 | 1999-03-09 | Matsushita Electric Ind Co Ltd | Circuit forming board, method and apparatus for forming circuit forming board |
JPH11177199A (en) * | 1997-12-05 | 1999-07-02 | Matsushita Electric Ind Co Ltd | Printed wiring board and its manufacture |
JP2000036666A (en) * | 1998-07-16 | 2000-02-02 | Matsushita Electric Ind Co Ltd | Multilayer printed wiring board and its manufacture |
JP2000307246A (en) * | 1999-04-26 | 2000-11-02 | Matsushita Electric Ind Co Ltd | Manufacture of circuit forming substrate and material thereof |
JP2001085838A (en) * | 1999-09-14 | 2001-03-30 | Matsushita Electric Works Ltd | Method for manufacturing multilayer laminated plate |
Non-Patent Citations (1)
Title |
---|
See also references of EP1408726A4 * |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013031822A1 (en) * | 2011-08-29 | 2013-03-07 | 京セラ株式会社 | Thin-film wiring substrate and substrate for probe card |
JPWO2013031822A1 (en) * | 2011-08-29 | 2015-03-23 | 京セラ株式会社 | Thin film wiring board and probe card board |
US9326378B2 (en) | 2011-08-29 | 2016-04-26 | Kyocera Corporation | Thin-film wiring substrate and substrate for probe card |
JP5196056B1 (en) * | 2012-06-14 | 2013-05-15 | パナソニック株式会社 | Composite multilayer wiring board and manufacturing method thereof |
WO2013186966A1 (en) * | 2012-06-14 | 2013-12-19 | パナソニック株式会社 | Composite multilayer wiring board and method for manufacturing same |
JPWO2016084375A1 (en) * | 2014-11-28 | 2017-09-07 | 日本ゼオン株式会社 | Manufacturing method of multilayer printed wiring board |
US10568212B2 (en) | 2014-11-28 | 2020-02-18 | Intel Corporation | Manufacturing method for multi-layer printed circuit board |
Also Published As
Publication number | Publication date |
---|---|
JPWO2003009660A1 (en) | 2004-11-11 |
CN1465218A (en) | 2003-12-31 |
EP1408726B1 (en) | 2010-02-10 |
US20040067348A1 (en) | 2004-04-08 |
CN1794902A (en) | 2006-06-28 |
EP1408726A1 (en) | 2004-04-14 |
DE60235301D1 (en) | 2010-03-25 |
EP1408726A4 (en) | 2007-09-19 |
CN100473261C (en) | 2009-03-25 |
US7059044B2 (en) | 2006-06-13 |
CN1794902B (en) | 2010-05-26 |
TW558931B (en) | 2003-10-21 |
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