WO2002075926B1 - Antifuse reroute of dies - Google Patents

Antifuse reroute of dies

Info

Publication number
WO2002075926B1
WO2002075926B1 PCT/US2002/007916 US0207916W WO02075926B1 WO 2002075926 B1 WO2002075926 B1 WO 2002075926B1 US 0207916 W US0207916 W US 0207916W WO 02075926 B1 WO02075926 B1 WO 02075926B1
Authority
WO
WIPO (PCT)
Prior art keywords
die
antifuse
circuit
routing
contact pads
Prior art date
Application number
PCT/US2002/007916
Other languages
French (fr)
Other versions
WO2002075926A3 (en
WO2002075926A2 (en
Inventor
Kevin Duesman
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to AU2002252359A priority Critical patent/AU2002252359A1/en
Priority to KR1020037012049A priority patent/KR100649911B1/en
Priority to JP2002574230A priority patent/JP4128081B2/en
Priority to EP02721425.3A priority patent/EP1386398B1/en
Publication of WO2002075926A2 publication Critical patent/WO2002075926A2/en
Publication of WO2002075926A3 publication Critical patent/WO2002075926A3/en
Publication of WO2002075926B1 publication Critical patent/WO2002075926B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/12—Apparatus or processes for interconnecting storage elements, e.g. for threading magnetic cores
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Abstract

A semiconductor die is provided with an internally programmable router to assign signal paths to select connection points. A switching matrix incorporating at least one antifuse is utilized to selectively route signal paths on the semiconductor die. The chips can then be used individually, for example to reconfigure chip pin assignments to operate in a plurality of different socket layouts, or where features or controls of a chip are selectively enabled or disabled. A further alternative involves programming a first chip, then stacking piggyback, or one on top of the other, the first chip onto a second chip. The contact pins are electrically coupled together, thus avoiding the need for external frames and pin rerouting schemes to form stacked chips. In the stacked chip configuration, control pins are rerouted to align with unused pins on the chip stacked against.

Claims

AMENDED CLAIMS[Received by the International Bureau on 04 November 2003 ( 04.11.03): original claims 1-76 replaced by amended claims 1-46]
1. A signal routing circuit comprising: a first signal path having a first segment and a plurality of second segments, each of said plurality of second segments independent from one another; a routing matrix circuit in-line with said first signal path disposed between said first segment and said plurality of second segments, said routing matrix circuit programmable for each of said plurality of second segments between a first state wherein contact is made to said first segment, and a second state wherein contact is broken to said first segment; and a programming circuit coupled to said routing matrix circuit, said programming circuit arranged to selectively program said routing matrix circuit between said first and second states for each of said plurality of second segments.
2. The signal routing circuit according to claim 1, wherein said first segment is further coupled to a logic circuit and each of said second segments are further coupled to an associated contact pad.
3. The signal routing circuit according to claim 1 , wherein each of said second segments are further coupled to a logic circuit and said first segment is further coupled to a contact pad.
4. The signal routing circuit according to claim 1 , further comprising a plurality of first segments coupled to said routing matrix, wherein said routing matrix is programmable to selectively couple and decouple any of said plurality of first segments to any of said plurality of second segments. -18-
5. The signal routing circuit according to claim 1, wherein said routing matrix circuit comprises an antifuse disposed serially between said first segment and a select one of said second segments, wherein said programming circuit is arranged to program said antifuse between said first and second states.
6. The signal routing circuit according to claim 5, wherein said routing matrix circuit includes a first circuit arranged to isolate said antifuse from said first segment and said select one of said second segments during programming.
7. The signal routing circuit according to claim 5, wherein said routing matrix circuit further comprises a first programming switch positioned serially between said antifuse and said first segment and a second programming switch positioned serially between said antifuse and said select one of said second segments, said first and second programming switches operatively coupled to said programming circuit and arranged to isolate said antifuse from said select one of said second segments during programming.
8. The signal routing circuit according to claim 1 , wherein said routing matrix circuit comprises an antifuse disposed serially between said first segment and each of said second segments, wherein said programming circuit is arranged to program each antifuse between said first and second states.
9. The signal routing circuit according to claim 1 , wherein: said routing matrix comprises a switching matrix disposed between said first and second segments of said first signal path; said switching matrix is programmable between said first and second states; said programming circuit further comprises at least one antifuse and a sensing circuit coupling said at least one antifuse to said switching matrix; and said programming circuit is arranged to selectively program said antifuse to control said switching matrix between said first and second states. -19-
10. The signal routing circuit according to claim 9, wherein said sensing circuit outputs at least one switch control signal coding the programmed state of said at least one antifuse, and said switching matrix is operatively controlled by said at least one control signal.
11. The signal routing circuit according to claim 10, wherein said switching matrix further comprises decoding logic to control switching thereof by said at least one control signal.
12. The signal routing circuit according to claim 9, wherein said at least one antifuse is electrically isolated from said first and second segments of said first signal path during programming.
13. A semiconductor die stack comprising: a first die having: an internal signal path; a plurality of contact pads independent from one another; a routing matrix circuit disposed between said internal signal path and said plurality of contact pads, said routing matrix circuit programmable for each of said plurality of contact pads between a first state wherein contact is made to said internal signal path, and a second state wherein contact is broken to said internal signal path; and a programming circuit coupled to said routing matrix circuit, said programming circuit arranged to selectively program said routing matrix circuit between said first and second states for each of said plurality of contact pads; and, a second die having a plurality of contact pads, wherein said first and second dies are stacked together and select ones of said plurality of contact pads of said first die are coupled to associated ones of said plurality of contact pads of said second die. -20-
14. The semiconductor die stack according to claim 13, wherein said first and second dies are piggybacked together such that a select one of said plurality of contact pads of said first die aligns substantially vertically, and is coupled to an associated one of said plurality of contact pads of said second die.
15. The semiconductor die stack according to claim 13, wherein said first die further comprises at least one unused contact pad coupled to an associated one of said plurality of contact pads of said second die, and decoupled from at least one unused contact pad of said second die.
16. The semiconductor die stack according to claim 13, wherein: said plurality of contact pads of said first die further comprise at least one first die input/output pad and at least one first die select pad; and, said plurality of contact pads of said second die further comprise at least one second die input/output pad and at least one second die select pad; wherein each first die input/output pad is coupled to an associated one second die input/output pad, each first die select pad is coupled to an associated one unused contact pad of said second die, and each second die select pad is coupled to an associated one unused contact pad of said first die.
17. The semiconductor die stack according to claim 13, wherein: said plurality of contact pads of said first die further comprise at least one first die input/output pad and at least one first die select pad; and, said plurality of contact pads of said second die further comprise at least one second die input/output pad and at least one second die select pad; wherein each first die select pad is coupled to an associated one second die select pad, each first die input/output pad is coupled to an associated one unused contact pad of said second die, and each second die input/output pad is coupled to an associated one unused contact pad of said first die. -21-
18. The semiconductor die stack according to claim 13, wherein said rerouting matrix circuit comprises at least one antifuse serially positioned between said internal signal path and a select one of said plurality of contact pads.
19. The semiconductor die stack according to claim 18, wherein said rerouting matrix circuit further comprises a first circuit arranged to isolate each antifuse during programming.
20. The semiconductor die stack according to claim 13, wherein said rerouting matrix circuit further comprises: at least one antifuse; an antifuse programming circuit coupled to said at least one antifuse; an antifuse sensing circuit coupled to said at least one antifuse; and at least one switch between said internal signal path and at least one of said plurality of contact pads operatively controlled by said antifuse sensing circuit.
21. The semiconductor die stack according to claim 20, wherein said rerouting matrix circuit further comprises a first circuit arranged to isolate each antifuse during programming.
22. The semiconductor die stack according to claim 13, wherein said second die further comprises a second routing matrix circuit programmable to reroute an internal signal path of said second die from a first one of said plurality of contact pads on said second die to a second one of said plurality of contact pads on said second die. -22-
23. The semiconductor die stack according to claim 13, wherein each of said first and second semiconductor dies are individually packaged in a respective chip package and said respective chip packages are stacked together such that said select ones of said plurality of contact pads of said first die are coupled to associated ones of said plurality of contact pads of said second die via contact pins of said respective chip packages.
24. A method of routing a signal in a semiconductor device comprising: providing a routing matrix circuit; coupling a first signal path to said routing matrix circuit; and coupling a plurality of second signal paths to said routing matrix, wherein each of said second signal paths is independent from one another, said routing matrix circuit programmable to selectively connect said first signal path to zero or more of said plurality of second signal paths, wherein said first signal path is isolated from the remainder ones of said plurality of second signal paths.
25. The method of routing a signal according to claim 24, further comprising coupling said first signal path to a logic circuit and coupling each of said plurality of second signal paths to contact pads.
26. The method of routing a signal according to claim 24, further comprising coupling said first signal path to a contact pad and coupling each of said plurality of second signal paths to a logic circuit.
27. The method of routing a signal according to claim 24, further comprising coupling a plurality of first signal paths to said routing matrix and configuring said routing matrix to be programmable to selectively couple and decouple any of said plurality of first signal paths to any of said plurality of second signal paths. -23-
28. The method of routing a signal according to claim 24, wherein the act of providing said routing matrix comprises coupling an antifuse serially between said first signal path and a select one of said second signal paths.
29. The method of routing a signal according to claim 28, further comprising programming said antifuse, wherein said act of programming said antifuse comprises: isolating said first signal path and said plurality of second signal paths from said select one antifuse; applying a programming voltage to said antifuse after isolating said antifuse; and de-isolating said select antifuse.
30. The method of routing a signal according to claim 29, wherein said act of isolating said select one antifuse comprises: positioning serially, a first transistor between said routing matrix circuit and said first signal path; positioning serially, a second transistor between said routing matrix circuit and said select one of said plurality of second signal paths; positioning said select one antifuse serially between said first and second transistors; and controlling a gate on each of said first and second transistors to isolate said antifuse.
31. The method of routing a signal according to claim 24, wherein the act of providing a routing matrix comprises providing an antifuse disposed serially between said first signal path and each of said plurality of second signal paths, wherein each antifuse is programmable to selectively couple and decouple said first signal path to an associated second signal path. -24-
32. The method of routing a signal according to claim 24, wherein: said act of providing a routing matrix circuit comprises: coupling a switching matrix between said first signal path and said plurality of second signal paths; providing at least one antifuse; and coupling a sensing circuit between said at least one antifuse and said switching matrix; said method further comprising: providing a programming circuit coupled to said at least one antifuse arranged to selectively program said routing matrix circuit.
33. The method of routing a signal according to claim 32, further comprising: coding the state of said at least one antifuse into a switch control signal; outputting said switch control signal; and operatively controlling said switching matrix by said switch control signal.
34. The method of routing a signal according to claim 31 , further comprising using decoding logic to control said switching matrix using said switch control signal.
35. The method of routing a signal according to claim 31 , further comprising electrically isolating said at least one antifuse from said first and second signal paths during programming.
36. A method of interconnecting semiconductor dies comprising: providing a first die comprising: providing an internal signal path; providing a plurality of contact pads independent from one another; providing a routing matrix circuit; coupling said internal signal path to said routing matrix circuit; and coupling said plurality of contact pads to said routing matrix, said routing matrix circuit programmable to selectively connect said internal signal path to zero or more -25-
of said plurality of contact pads, wherein said internal signal path is isolated from the remainder ones of said plurality of contact pads. providing a second die having a plurality of contact pads; and stacking said first and second dies together such that select ones of said plurality of contact pads of said first die are coupled to associated ones of said plurality of contact pads of said second die.
37. The method according to claim 36, wherein said act of stacking said first and second dies comprises piggybacking said first and second dies together such that a select one of said plurality of contact pads of said first die aligns substantially vertically, and is coupled to an associated one of said plurality of contact pads of said second die.
38. The method according to claim 36, wherein said act of providing a first die having a plurality of contact pads comprises: providing at least one unused contact pad; and coupling at least one unused contact pad of said first die to a select one of said plurality of contact pads of said second die, wherein said select one of said plurality of contact pads of said second die is not an unused pad.
39. The method according to claim 36, wherein: said act of providing said first die having a plurality of contact pads comprises providing at least one first die input/output pad and at least one first die select pad; said act of providing said second die having a plurality of contact pads comprises providing at least one second die input/output pad and at least one second die select pad; coupling each first die input/output pad an associated one second die input/output pad; -26-
coupling each first die select pad to an associated one unused contact pad of said second die; and coupling each second die select pad to an associated one unused contact pad of said first die.
40. The method according to claim 36, wherein: said act of providing said first die having a plurality of contact pads comprises providing at least one first die input/output pad and at least one first die select pad; said act of providing said second die having a plurality of contact pads comprises providing at least one second die input/output pad and at least one second die select pad; coupling each first die select pad to an associated one second die select pad; coupling each first die input/output pad to an associated one unused contact pad of said second die; and coupling each second die input/output pad to an associated one unused contact pad of said first die.
41. The method according to claim 36, wherein said act of providing said first die with said rerouting matrix circuit comprises providing an antifuse serially positioned between said internal signal path and a select one of said plurality of contact pads.
42. The method according to claim 41 , further comprising isolating said antifuse from said internal signal path and said select one of said plurality of contact pads during programming of said antifuse.
43. The method according to claim 36, wherein said act of providing said first die with said rerouting matrix circuit comprises: providing at least one antifuse; coupling an antifuse programming circuit to each antifuse; coupling an antifuse sensing circuit to each antifuse; -27-
positioning at least one switch between said internal signal path and at least one of said plurality of contact pads; and coupling said each switch to said antifuse sensing circuit; and configuring each switch to be operatively controllable by said antifuse sensing circuit.
44. The method according to claim 43, further comprising isolating each antifuse from said internal signal path and said plurality of contact pads during antifuse programming.
45. The method according to claim 36, further comprising providing said second die with a second routing matrix circuit programmable to reroute an internal signal path of said second die from a first one of said plurality of contact pads on said second die to a second one of said plurality of contact pads on said second die.
46. The method according to claim 36, wherein the act of providing first and second dies further comprises providing said first and second dies individually packaged in a respective chip package and wherein said act of stacking said first and second dies together further comprises stacking said respective chip packages such that select ones of said plurality of contact pads of said first die are coupled to associated ones of said plurality of contact pads of said second die via contact pins of said respective chip packages.
PCT/US2002/007916 2001-03-15 2002-03-15 Antifuse reroute of dies WO2002075926A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU2002252359A AU2002252359A1 (en) 2001-03-15 2002-03-15 Antifuse reroute of dies
KR1020037012049A KR100649911B1 (en) 2001-03-15 2002-03-15 Antifuse reroute of dies
JP2002574230A JP4128081B2 (en) 2001-03-15 2002-03-15 Route by die antifuse
EP02721425.3A EP1386398B1 (en) 2001-03-15 2002-03-15 Antifuse reroute of dies

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/809,537 2001-03-15
US09/809,537 US6417695B1 (en) 2001-03-15 2001-03-15 Antifuse reroute of dies

Publications (3)

Publication Number Publication Date
WO2002075926A2 WO2002075926A2 (en) 2002-09-26
WO2002075926A3 WO2002075926A3 (en) 2003-11-06
WO2002075926B1 true WO2002075926B1 (en) 2003-12-18

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/007916 WO2002075926A2 (en) 2001-03-15 2002-03-15 Antifuse reroute of dies

Country Status (7)

Country Link
US (4) US6417695B1 (en)
EP (3) EP2088675A3 (en)
JP (1) JP4128081B2 (en)
KR (1) KR100649911B1 (en)
CN (1) CN1316744C (en)
AU (1) AU2002252359A1 (en)
WO (1) WO2002075926A2 (en)

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