WO2002075926A3 - Antifuse reroute of dies - Google Patents

Antifuse reroute of dies Download PDF

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Publication number
WO2002075926A3
WO2002075926A3 PCT/US2002/007916 US0207916W WO02075926A3 WO 2002075926 A3 WO2002075926 A3 WO 2002075926A3 US 0207916 W US0207916 W US 0207916W WO 02075926 A3 WO02075926 A3 WO 02075926A3
Authority
WO
WIPO (PCT)
Prior art keywords
chip
stacked
pins
semiconductor die
antifuse
Prior art date
Application number
PCT/US2002/007916
Other languages
French (fr)
Other versions
WO2002075926B1 (en
WO2002075926A2 (en
Inventor
Kevin Duesman
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to AU2002252359A priority Critical patent/AU2002252359A1/en
Priority to KR1020037012049A priority patent/KR100649911B1/en
Priority to JP2002574230A priority patent/JP4128081B2/en
Priority to EP02721425.3A priority patent/EP1386398B1/en
Publication of WO2002075926A2 publication Critical patent/WO2002075926A2/en
Publication of WO2002075926A3 publication Critical patent/WO2002075926A3/en
Publication of WO2002075926B1 publication Critical patent/WO2002075926B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/12—Apparatus or processes for interconnecting storage elements, e.g. for threading magnetic cores
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)

Abstract

A semiconductor die is provided with an internally programmable router to assign signal paths to select connection points. A switching matrix incorporating at least one antifuse is utilized to selectively route signal paths on the semiconductor die. The chips can then be used individually, for example to reconfigure chip pin assignments to operate in a plurality of different socket layouts, or where features or controls of a chip are selectively enabled or disabled. A further alternative involves programming a first chip, then stacking piggyback, or one on top of the other, the first chip onto a second chip. The contact pins are electrically coupled together, thus avoiding the need for external frames and pin rerouting schemes to form stacked chips. In the stacked chip configuration, control pins are rerouted to align with unused pins on the chip stacked against.
PCT/US2002/007916 2001-03-15 2002-03-15 Antifuse reroute of dies WO2002075926A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU2002252359A AU2002252359A1 (en) 2001-03-15 2002-03-15 Antifuse reroute of dies
KR1020037012049A KR100649911B1 (en) 2001-03-15 2002-03-15 Antifuse reroute of dies
JP2002574230A JP4128081B2 (en) 2001-03-15 2002-03-15 Route by die antifuse
EP02721425.3A EP1386398B1 (en) 2001-03-15 2002-03-15 Antifuse reroute of dies

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/809,537 2001-03-15
US09/809,537 US6417695B1 (en) 2001-03-15 2001-03-15 Antifuse reroute of dies

Publications (3)

Publication Number Publication Date
WO2002075926A2 WO2002075926A2 (en) 2002-09-26
WO2002075926A3 true WO2002075926A3 (en) 2003-11-06
WO2002075926B1 WO2002075926B1 (en) 2003-12-18

Family

ID=25201564

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/007916 WO2002075926A2 (en) 2001-03-15 2002-03-15 Antifuse reroute of dies

Country Status (7)

Country Link
US (4) US6417695B1 (en)
EP (3) EP2088675A3 (en)
JP (1) JP4128081B2 (en)
KR (1) KR100649911B1 (en)
CN (1) CN1316744C (en)
AU (1) AU2002252359A1 (en)
WO (1) WO2002075926A2 (en)

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Also Published As

Publication number Publication date
US6466053B2 (en) 2002-10-15
US20020130687A1 (en) 2002-09-19
US6633183B2 (en) 2003-10-14
CN1316744C (en) 2007-05-16
US20020149391A1 (en) 2002-10-17
CN1518797A (en) 2004-08-04
US6633180B2 (en) 2003-10-14
EP2285002A3 (en) 2014-07-09
EP2285002A2 (en) 2011-02-16
EP1386398A2 (en) 2004-02-04
KR100649911B1 (en) 2006-11-27
US20030012071A1 (en) 2003-01-16
US6417695B1 (en) 2002-07-09
EP2088675A2 (en) 2009-08-12
JP4128081B2 (en) 2008-07-30
EP1386398B1 (en) 2015-12-30
KR20030093243A (en) 2003-12-06
JP2004535661A (en) 2004-11-25
EP2088675A3 (en) 2014-07-09
AU2002252359A1 (en) 2002-10-03
WO2002075926B1 (en) 2003-12-18
WO2002075926A2 (en) 2002-09-26

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